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authorAdrian Bunk <bunk@stusta.de>2007-02-12 03:54:50 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-12 12:48:41 -0500
commite019630e78e3482c2386d18cbdc7a4c54f7a809c (patch)
tree4b4bac38f1b501bac9a54ce8f08a1a6f1b26123f /drivers/video/virgefb.c
parenta268422de8bf1b4c0cb97987b6c329c9f6a3da4b (diff)
[PATCH] remove broken video drivers
Remove some video drivers that: - had already been marked as BROKEN in 2.6.0 three years ago and - are still marked as BROKEN. These are the following drivers: - FB_CYBER - FB_VIRGE - FB_RETINAZ3 - FB_SUN3 Drivers that had been marked as BROKEN for such a long time seem to be unlikely to be revived in the forseeable future. But if anyone wants to ever revive any of these drivers, the code is still present in the older kernel releases. Signed-off-by: Adrian Bunk <bunk@stusta.de> Acked-By: Geert Uytterhoeven <geert@linux-m68k.org> Cc: James Simmons <jsimmons@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/virgefb.c')
-rw-r--r--drivers/video/virgefb.c2526
1 files changed, 0 insertions, 2526 deletions
diff --git a/drivers/video/virgefb.c b/drivers/video/virgefb.c
deleted file mode 100644
index b9fb6fb3600d..000000000000
--- a/drivers/video/virgefb.c
+++ /dev/null
@@ -1,2526 +0,0 @@
1/*
2 * linux/drivers/video/virgefb.c -- CyberVision64/3D frame buffer device
3 *
4 * Copyright (C) 1997 André Heynatz
5 *
6 *
7 * This file is based on the CyberVision frame buffer device (cyberfb.c):
8 *
9 * Copyright (C) 1996 Martin Apel
10 * Geert Uytterhoeven
11 *
12 * Zorro II additions :
13 *
14 * Copyright (C) 1998-2000 Christian T. Steigies
15 *
16 * Initialization additions :
17 *
18 * Copyright (C) 1998-2000 Ken Tyler
19 *
20 * Parts of the Initialization code are based on Cyberfb.c by Allan Bair,
21 * and on the NetBSD CyberVision64 frame buffer driver by Michael Teske who gave
22 * permission for its use.
23 *
24 * Many thanks to Frank Mariak for his assistance with ZORRO 2 access and other
25 * mysteries.
26 *
27 *
28 *
29 * This file is subject to the terms and conditions of the GNU General Public
30 * License. See the file COPYING in the main directory of this archive
31 * for more details.
32 */
33
34#undef VIRGEFBDEBUG
35#undef VIRGEFBDUMP
36
37#include <linux/module.h>
38#include <linux/kernel.h>
39#include <linux/errno.h>
40#include <linux/string.h>
41#include <linux/mm.h>
42#include <linux/slab.h>
43#include <linux/delay.h>
44#include <linux/zorro.h>
45#include <linux/fb.h>
46#include <linux/init.h>
47#include <asm/uaccess.h>
48#include <asm/system.h>
49#include <asm/amigahw.h>
50#include <asm/io.h>
51#include <asm/irq.h>
52#include <video/fbcon.h>
53#include <video/fbcon-cfb8.h>
54#include <video/fbcon-cfb16.h>
55#include <video/fbcon-cfb32.h>
56
57#include "virgefb.h"
58
59#ifdef VIRGEFBDEBUG
60#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
61#else
62#define DPRINTK(fmt, args...)
63#endif
64
65#ifdef VIRGEFBDUMP
66static void cv64_dump(void);
67#define DUMP cv64_dump()
68#else
69#define DUMP
70#endif
71
72/*
73 * Macros for register access and zorro control
74 */
75
76static inline void mb_inline(void) { mb(); } /* for use in comma expressions */
77
78/* Set zorro 2 map */
79
80#define SelectIO \
81 mb(); \
82 if (on_zorro2) { \
83 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x01); \
84 mb(); \
85 }
86
87#define SelectMMIO \
88 mb(); \
89 if (on_zorro2) { \
90 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x02); \
91 mb(); \
92 }
93
94#define SelectCFG \
95 mb(); \
96 if (on_zorro2) { \
97 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x03); \
98 mb(); \
99 }
100
101/* Set pass through, 0 = amiga, !=0 = cv64/3d */
102
103#define SetVSwitch(x) \
104 mb(); \
105 (*(volatile u16 *)((u8 *)(vcode_switch_base)) = \
106 (u16)(x ? 0 : 1)); \
107 mb();
108
109/* Zorro2 endian 'aperture' */
110
111#define ENDIAN_BYTE 2
112#define ENDIAN_WORD 1
113#define ENDIAN_LONG 0
114
115#define Select_Zorro2_FrameBuffer(x) \
116 do { \
117 if (on_zorro2) { \
118 mb(); \
119 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x08)) = \
120 (x * 0x40)); \
121 mb(); \
122 } \
123 } while (0)
124
125/* SetPortVal - only used for interrupt enable (not yet implemented) */
126
127#if 0
128#define SetPortVal(x) \
129 mb(); \
130 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x0c)) = \
131 (u16)x); \
132 mb();
133#endif
134
135/* IO access */
136
137#define byte_access_io(x) (((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14))
138#define byte_access_mmio(x) (((x) & 0xfffc) | (((x) & 3)^3))
139
140/* Write 8 bit VGA register - used once for chip wakeup */
141
142#define wb_vgaio(reg, dat) \
143 SelectIO; \
144 (*(volatile u8 *)(vgaio_regs + ((u32)byte_access_io(reg) & 0xffff)) = \
145 (dat & 0xff)); \
146 SelectMMIO;
147
148/* Read 8 bit VGA register - only used in dump (SelectIO not needed on read ?) */
149
150#ifdef VIRGEFBDUMP
151#define rb_vgaio(reg) \
152 ({ \
153 u8 __zzyzx; \
154 SelectIO; \
155 __zzyzx = (*(volatile u8 *)((vgaio_regs)+(u32)byte_access_io(reg))); \
156 SelectMMIO; \
157 __zzyzx; \
158 })
159#endif
160
161/* MMIO access */
162
163/* Read 8 bit MMIO register */
164
165#define rb_mmio(reg) \
166 (mb_inline(), \
167 (*(volatile u8 *)(mmio_regs + 0x8000 + (u32)byte_access_mmio(reg))))
168
169/* Write 8 bit MMIO register */
170
171#define wb_mmio(reg,dat) \
172 mb(); \
173 (*(volatile u8 *)(mmio_regs + 0x8000 + (byte_access_mmio((reg) & 0xffff))) = \
174 (dat & 0xff)); \
175 mb();
176
177/* Read 32 bit MMIO register */
178
179#define rl_mmio(reg) \
180 (mb_inline(), \
181 (*((volatile u32 *)((u8 *)((mmio_regs + (on_zorro2 ? 0x20000 : 0)) + (reg))))))
182
183/* Write 32 bit MMIO register */
184
185#define wl_mmio(reg,dat) \
186 mb(); \
187 ((*(volatile u32 *)((u8 *)((mmio_regs + (on_zorro2 ? 0x20000 : 0)) + (reg)))) = \
188 (u32)(dat)); \
189 mb();
190
191/* Write to virge graphics register */
192
193#define wgfx(reg, dat) do { wb_mmio(GCT_ADDRESS, (reg)); wb_mmio(GCT_ADDRESS_W, (dat)); } while (0)
194
195/* Write to virge sequencer register */
196
197#define wseq(reg, dat) do { wb_mmio(SEQ_ADDRESS, (reg)); wb_mmio(SEQ_ADDRESS_W, (dat)); } while (0)
198
199/* Write to virge CRT controller register */
200
201#define wcrt(reg, dat) do { wb_mmio(CRT_ADDRESS, (reg)); wb_mmio(CRT_ADDRESS_W, (dat)); } while (0)
202
203/* Write to virge attribute register */
204
205#define watr(reg, dat) \
206 do { \
207 volatile unsigned char watr_tmp; \
208 watr_tmp = rb_mmio(ACT_ADDRESS_RESET); \
209 wb_mmio(ACT_ADDRESS_W, (reg)); \
210 wb_mmio(ACT_ADDRESS_W, (dat)); \
211 udelay(10); \
212 } while (0)
213
214/* end of macros */
215
216struct virgefb_par {
217 struct fb_var_screeninfo var;
218 __u32 type;
219 __u32 type_aux;
220 __u32 visual;
221 __u32 line_length;
222};
223
224static struct virgefb_par current_par;
225
226static int current_par_valid = 0;
227
228static struct display disp;
229static struct fb_info fb_info;
230
231static union {
232#ifdef FBCON_HAS_CFB16
233 u16 cfb16[16];
234#endif
235#ifdef FBCON_HAS_CFB32
236 u32 cfb32[16];
237#endif
238} fbcon_cmap;
239
240/*
241 * Switch for Chipset Independency
242 */
243
244static struct fb_hwswitch {
245
246 /* Initialisation */
247
248 int (*init)(void);
249
250 /* Display Control */
251
252 int (*encode_fix)(struct fb_fix_screeninfo *fix, struct virgefb_par *par);
253 int (*decode_var)(struct fb_var_screeninfo *var, struct virgefb_par *par);
254 int (*encode_var)(struct fb_var_screeninfo *var, struct virgefb_par *par);
255 int (*getcolreg)(u_int regno, u_int *red, u_int *green, u_int *blue,
256 u_int *transp, struct fb_info *info);
257 void (*blank)(int blank);
258} *fbhw;
259
260static unsigned char blit_maybe_busy = 0;
261
262/*
263 * Frame Buffer Name
264 */
265
266static char virgefb_name[16] = "CyberVision/3D";
267
268/*
269 * CyberVision64/3d Graphics Board
270 */
271
272static unsigned char virgefb_colour_table [256][3];
273static unsigned long v_ram;
274static unsigned long v_ram_size;
275static volatile unsigned char *mmio_regs;
276static volatile unsigned char *vgaio_regs;
277
278static unsigned long v_ram_phys;
279static unsigned long mmio_regs_phys;
280static unsigned long vcode_switch_base;
281static unsigned char on_zorro2;
282
283/*
284 * Offsets from start of video ram to appropriate ZIII aperture
285 */
286
287#ifdef FBCON_HAS_CFB8
288#define CYBMEM_OFFSET_8 0x800000 /* BGRX */
289#endif
290#ifdef FBCON_HAS_CFB16
291#define CYBMEM_OFFSET_16 0x400000 /* GBXR */
292#endif
293#ifdef FBCON_HAS_CFB32
294#define CYBMEM_OFFSET_32 0x000000 /* XRGB */
295#endif
296
297/*
298 * MEMCLOCK was 32MHz, 64MHz works, 72MHz doesn't (on my board)
299 */
300
301#define MEMCLOCK 50000000
302
303/*
304 * Predefined Video Modes
305 */
306
307static struct {
308 const char *name;
309 struct fb_var_screeninfo var;
310} virgefb_predefined[] __initdata = {
311#ifdef FBCON_HAS_CFB8
312 {
313 "640x480-8", { /* Cybervision 8 bpp */
314 640, 480, 640, 480, 0, 0, 8, 0,
315 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
316 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 160, 136, 82, 61, 88, 2,
317 0, FB_VMODE_NONINTERLACED
318 }
319 }, {
320 "768x576-8", { /* Cybervision 8 bpp */
321 768, 576, 768, 576, 0, 0, 8, 0,
322 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
323 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
324 0, FB_VMODE_NONINTERLACED
325 }
326 }, {
327 "800x600-8", { /* Cybervision 8 bpp */
328 800, 600, 800, 600, 0, 0, 8, 0,
329 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
330 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
331 0, FB_VMODE_NONINTERLACED
332 }
333 }, {
334 #if 0
335 "1024x768-8", { /* Cybervision 8 bpp */
336 1024, 768, 1024, 768, 0, 0, 8, 0,
337 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
338 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
339 0, FB_VMODE_NONINTERLACED
340 }
341 #else
342 "1024x768-8", {
343 1024, 768, 1024, 768, 0, 0, 8, 0,
344 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
345 #if 0
346 0, 0, -1, -1, FB_ACCELF_TEXT, 12500, 184, 40, 40, 2, 96, 1,
347 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
348 }
349 #else
350 0, 0, -1, -1, FB_ACCELF_TEXT, 12699, 176, 16, 28, 1, 96, 3,
351 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
352 }
353 #endif
354 #endif
355 }, {
356 "1152x886-8", { /* Cybervision 8 bpp */
357 1152, 886, 1152, 886, 0, 0, 8, 0,
358 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
359 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
360 0, FB_VMODE_NONINTERLACED
361 }
362 }, {
363 "1280x1024-8", { /* Cybervision 8 bpp */
364 1280, 1024, 1280, 1024, 0, 0, 8, 0,
365 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
366 #if 0
367 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
368 }
369 #else
370 0, 0, -1, -1, FB_ACCELF_TEXT, 7414, 232, 64, 38, 1, 112, 3,
371 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
372 }
373 #endif
374 }, {
375 "1600x1200-8", { /* Cybervision 8 bpp */
376 1600, 1200, 1600, 1200, 0, 0, 8, 0,
377 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
378 #if 0
379 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
380 0, FB_VMODE_NONINTERLACED
381 }
382 #else
383 0, 0, -1, -1, FB_ACCELF_TEXT, 6411, 256, 32, 52, 10, 160, 8,
384 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
385 }
386 #endif
387 },
388#endif
389
390#ifdef FBCON_HAS_CFB16
391 {
392 "640x480-16", { /* Cybervision 16 bpp */
393 640, 480, 640, 480, 0, 0, 16, 0,
394 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
395 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 152, 144, 82, 61, 88, 2,
396 0, FB_VMODE_NONINTERLACED
397 }
398 }, {
399 "768x576-16", { /* Cybervision 16 bpp */
400 768, 576, 768, 576, 0, 0, 16, 0,
401 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
402 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
403 0, FB_VMODE_NONINTERLACED
404 }
405 }, {
406 "800x600-16", { /* Cybervision 16 bpp */
407 800, 600, 800, 600, 0, 0, 16, 0,
408 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
409 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
410 0, FB_VMODE_NONINTERLACED
411 }
412 }, {
413#if 0
414 "1024x768-16", { /* Cybervision 16 bpp */
415 1024, 768, 1024, 768, 0, 0, 16, 0,
416 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
417 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
418 0, FB_VMODE_NONINTERLACED
419 }
420#else
421 "1024x768-16", {
422 1024, 768, 1024, 768, 0, 0, 16, 0,
423 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
424 0, 0, -1, -1, FB_ACCELF_TEXT, 12500, 184, 40, 40, 2, 96, 1,
425 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
426 }
427#endif
428 }, {
429 "1152x886-16", { /* Cybervision 16 bpp */
430 1152, 886, 1152, 886, 0, 0, 16, 0,
431 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
432 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
433 0, FB_VMODE_NONINTERLACED
434 }
435 }, {
436 "1280x1024-16", { /* Cybervision 16 bpp */
437 1280, 1024, 1280, 1024, 0, 0, 16, 0,
438 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
439 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
440 0, FB_VMODE_NONINTERLACED
441 }
442 }, {
443 "1600x1200-16", { /* Cybervision 16 bpp */
444 1600, 1200, 1600, 1200, 0, 0, 16, 0,
445 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
446 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
447 0, FB_VMODE_NONINTERLACED
448 }
449 },
450#endif
451
452#ifdef FBCON_HAS_CFB32
453 {
454 "640x480-32", { /* Cybervision 32 bpp */
455 640, 480, 640, 480, 0, 0, 32, 0,
456 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
457 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 160, 136, 82, 61, 88, 2,
458 0, FB_VMODE_NONINTERLACED
459 }
460 }, {
461 "768x576-32", { /* Cybervision 32 bpp */
462 768, 576, 768, 576, 0, 0, 32, 0,
463 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
464 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
465 0, FB_VMODE_NONINTERLACED
466 }
467 }, {
468 "800x600-32", { /* Cybervision 32 bpp */
469 800, 600, 800, 600, 0, 0, 32, 0,
470 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
471 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
472 0, FB_VMODE_NONINTERLACED
473 }
474 }, {
475 "1024x768-32", { /* Cybervision 32 bpp */
476 1024, 768, 1024, 768, 0, 0, 32, 0,
477 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
478 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
479 0, FB_VMODE_NONINTERLACED
480 }
481 }, {
482 "1152x886-32", { /* Cybervision 32 bpp */
483 1152, 886, 1152, 886, 0, 0, 32, 0,
484 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
485 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
486 0, FB_VMODE_NONINTERLACED
487 }
488 }, {
489 "1280x1024-32", { /* Cybervision 32 bpp */
490 1280, 1024, 1280, 1024, 0, 0, 32, 0,
491 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
492 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
493 0, FB_VMODE_NONINTERLACED
494 }
495 }, {
496 "1600x1200-32", { /* Cybervision 32 bpp */
497 1600, 1200, 1600, 1200, 0, 0, 32, 0,
498 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
499 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
500 0, FB_VMODE_NONINTERLACED
501 }
502 },
503#endif
504
505/* interlaced modes */
506
507#ifdef FBCON_HAS_CFB8
508 {
509 "1024x768-8i", { /* Cybervision 8 bpp */
510 1024, 768, 1024, 768, 0, 0, 8, 0,
511 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
512 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
513 0, FB_VMODE_INTERLACED
514 }
515 }, {
516 "1280x1024-8i", { /* Cybervision 8 bpp */
517 1280, 1024, 1280, 1024, 0, 0, 8, 0,
518 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
519 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
520 0, FB_VMODE_INTERLACED
521 }
522 }, {
523 "1600x1200-8i", { /* Cybervision 8 bpp */
524 1600, 1200, 1600, 1200, 0, 0, 8, 0,
525 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
526 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
527 0, FB_VMODE_INTERLACED
528 }
529 },
530#endif
531
532#ifdef FBCON_HAS_CFB16
533 {
534 "1024x768-16i", { /* Cybervision 16 bpp */
535 1024, 768, 1024, 768, 0, 0, 16, 0,
536 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
537 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
538 0, FB_VMODE_INTERLACED
539 }
540 }, {
541 "1280x1024-16i", { /* Cybervision 16 bpp */
542 1280, 1024, 1280, 1024, 0, 0, 16, 0,
543 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
544 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
545 0, FB_VMODE_INTERLACED
546 }
547 }, {
548 "1600x1200-16i", { /* Cybervision 16 bpp */
549 1600, 1200, 1600, 1200, 0, 0, 16, 0,
550 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
551 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
552 0, FB_VMODE_INTERLACED
553 }
554 },
555#endif
556
557#ifdef FBCON_HAS_CFB32
558 {
559 "1024x768-32i", { /* Cybervision 32 bpp */
560 1024, 768, 1024, 768, 0, 0, 32, 0,
561 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
562 0, 0, -1, -1, FB_ACCELF_TEXT, 22222, 216, 144, 39, 2, 72, 1,
563 0, FB_VMODE_INTERLACED
564 }
565 }, {
566 "1280x1024-32i", { /* Cybervision 32 bpp */
567 1280, 1024, 1280, 1024, 0, 0, 32, 0,
568 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {23, 0, 0},
569 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
570 0, FB_VMODE_INTERLACED
571 }
572 }, {
573 "1600x1200-32i", { /* Cybervision 32 bpp */
574 1600, 1200, 1600, 1200, 0, 0, 32, 0,
575 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
576 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
577 0, FB_VMODE_INTERLACED
578 }
579 },
580#endif
581
582/* doublescan modes */
583
584#ifdef FBCON_HAS_CFB8
585 {
586 "320x240-8d", { /* Cybervision 8 bpp */
587 320, 240, 320, 240, 0, 0, 8, 0,
588 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
589 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
590 0, FB_VMODE_DOUBLE
591 }
592 },
593#endif
594
595#ifdef FBCON_HAS_CFB16
596 {
597 "320x240-16d", { /* Cybervision 16 bpp */
598 320, 240, 320, 240, 0, 0, 16, 0,
599 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
600 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
601 0, FB_VMODE_DOUBLE
602 }
603 },
604#endif
605
606#ifdef FBCON_HAS_CFB32
607 {
608 "320x240-32d", { /* Cybervision 32 bpp */
609 320, 240, 320, 240, 0, 0, 32, 0,
610 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
611 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
612 0, FB_VMODE_DOUBLE
613 }
614 },
615#endif
616};
617
618#define NUM_TOTAL_MODES ARRAY_SIZE(virgefb_predefined)
619
620/*
621 * Default to 800x600 for video=virge8:, virge16: or virge32:
622 */
623
624#ifdef FBCON_HAS_CFB8
625#define VIRGE8_DEFMODE (2)
626#endif
627
628#ifdef FBCON_HAS_CFB16
629#define VIRGE16_DEFMODE (9)
630#endif
631
632#ifdef FBCON_HAS_CFB32
633#define VIRGE32_DEFMODE (16)
634#endif
635
636static struct fb_var_screeninfo virgefb_default;
637static int virgefb_inverse = 0;
638
639/*
640 * Interface used by the world
641 */
642
643int virgefb_setup(char*);
644static int virgefb_get_fix(struct fb_fix_screeninfo *fix, int con,
645 struct fb_info *info);
646static int virgefb_get_var(struct fb_var_screeninfo *var, int con,
647 struct fb_info *info);
648static int virgefb_set_var(struct fb_var_screeninfo *var, int con,
649 struct fb_info *info);
650static int virgefb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
651 struct fb_info *info);
652static int virgefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
653 u_int transp, struct fb_info *info);
654static int virgefb_blank(int blank, struct fb_info *info);
655
656/*
657 * Interface to the low level console driver
658 */
659
660int virgefb_init(void);
661static int virgefb_switch(int con, struct fb_info *info);
662static int virgefb_updatevar(int con, struct fb_info *info);
663
664/*
665 * Text console acceleration
666 */
667
668#ifdef FBCON_HAS_CFB8
669static struct display_switch fbcon_virge8;
670#endif
671
672#ifdef FBCON_HAS_CFB16
673static struct display_switch fbcon_virge16;
674#endif
675
676#ifdef FBCON_HAS_CFB32
677static struct display_switch fbcon_virge32;
678#endif
679
680/*
681 * Hardware Specific Routines
682 */
683
684static int virge_init(void);
685static int virgefb_encode_fix(struct fb_fix_screeninfo *fix,
686 struct virgefb_par *par);
687static int virgefb_decode_var(struct fb_var_screeninfo *var,
688 struct virgefb_par *par);
689static int virgefb_encode_var(struct fb_var_screeninfo *var,
690 struct virgefb_par *par);
691static int virgefb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
692 u_int *transp, struct fb_info *info);
693static void virgefb_gfx_on_off(int blank);
694static inline void virgefb_wait_for_idle(void);
695static void virgefb_BitBLT(u_short curx, u_short cury, u_short destx, u_short desty,
696 u_short width, u_short height, u_short stride, u_short depth);
697static void virgefb_RectFill(u_short x, u_short y, u_short width, u_short height,
698 u_short color, u_short stride, u_short depth);
699
700/*
701 * Internal routines
702 */
703
704static void virgefb_get_par(struct virgefb_par *par);
705static void virgefb_set_par(struct virgefb_par *par);
706static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive);
707static void virgefb_set_disp(int con, struct fb_info *info);
708static int virgefb_get_video_mode(const char *name);
709static void virgefb_set_video(struct fb_var_screeninfo *var);
710
711/*
712 * Additions for Initialization
713 */
714
715static void virgefb_load_video_mode(struct fb_var_screeninfo *video_mode);
716static int cv3d_has_4mb(void);
717static unsigned short virgefb_compute_clock(unsigned long freq);
718static inline unsigned char rattr(short);
719static inline unsigned char rseq(short);
720static inline unsigned char rcrt(short);
721static inline unsigned char rgfx(short);
722static inline void gfx_on_off(int toggle);
723static void virgefb_pci_init(void);
724
725/* -------------------- Hardware specific routines ------------------------- */
726
727/*
728 * Functions for register access
729 */
730
731/* Read attribute controller register */
732
733static inline unsigned char rattr(short idx)
734{
735 volatile unsigned char rattr_tmp;
736
737 rattr_tmp = rb_mmio(ACT_ADDRESS_RESET);
738 wb_mmio(ACT_ADDRESS_W, idx);
739 return (rb_mmio(ACT_ADDRESS_R));
740}
741
742/* Read sequencer register */
743
744static inline unsigned char rseq(short idx)
745{
746 wb_mmio(SEQ_ADDRESS, idx);
747 return (rb_mmio(SEQ_ADDRESS_R));
748}
749
750/* Read CRT controller register */
751
752static inline unsigned char rcrt(short idx)
753{
754 wb_mmio(CRT_ADDRESS, idx);
755 return (rb_mmio(CRT_ADDRESS_R));
756}
757
758/* Read graphics controller register */
759
760static inline unsigned char rgfx(short idx)
761{
762 wb_mmio(GCT_ADDRESS, idx);
763 return (rb_mmio(GCT_ADDRESS_R));
764}
765
766
767/*
768 * Initialization
769 */
770
771/* PCI init */
772
773void virgefb_pci_init(void) {
774
775 DPRINTK("ENTER\n");
776
777 SelectCFG;
778
779 if (on_zorro2) {
780 *((short *)(vgaio_regs + 0x00000010)) = 0;
781 *((long *)(vgaio_regs + 0x00000004)) = 0x02000003;
782 } else {
783 *((short *)(vgaio_regs + 0x000e0010)) = 0;
784 *((long *)(vgaio_regs + 0x000e0004)) = 0x02000003;
785 }
786
787 /* SelectIO is in wb_vgaio macro */
788 wb_vgaio(SREG_VIDEO_SUBS_ENABLE, 0x01);
789 /* SelectMMIO is in wb_vgaio macro */
790
791 DPRINTK("EXIT\n");
792
793 return;
794}
795
796/*
797 * Initalize all mode independent regs, find mem size and clear mem
798*/
799
800static int virge_init(void)
801{
802 int i;
803 unsigned char tmp;
804
805 DPRINTK("ENTER\n");
806
807 virgefb_pci_init();
808
809 wb_mmio(GREG_MISC_OUTPUT_W, 0x07); /* colour, ram enable, clk sel */
810
811 wseq(SEQ_ID_UNLOCK_EXT, 0x06); /* unlock extensions */
812 tmp = rb_mmio(GREG_MISC_OUTPUT_R);
813 wcrt(CRT_ID_REGISTER_LOCK_1, 0x48); /* unlock CR2D to CR3F */
814
815 wcrt(CRT_ID_BACKWAD_COMP_1, 0x00); /* irq disable */
816
817 wcrt(CRT_ID_REGISTER_LOCK_2, 0xa5); /* unlock CR40 to CRFF and more */
818 wcrt(CRT_ID_REGISTER_LOCK,0x00); /* unlock h and v timing */
819 wcrt(CRT_ID_SYSTEM_CONFIG, 0x01); /* unlock enhanced programming registers */
820
821 wb_mmio(GREG_FEATURE_CONTROL_W, 0x00);
822
823 wcrt(CRT_ID_EXT_MISC_CNTL, 0x00); /* b2 = 0 to allow VDAC mmio access */
824#if 0
825 /* write strap options ... ? */
826 wcrt(CRT_ID_CONFIG_1, 0x08);
827 wcrt(CRT_ID_CONFIG_2, 0xff); /* 0x0x2 bit needs to be set ?? */
828 wcrt(CRT_ID_CONFIG_3, 0x0f);
829 wcrt(CRT_ID_CONFIG_4, 0x1a);
830#endif
831 wcrt(CRT_ID_EXT_MISC_CNTL_1, 0x82); /* PCI DE and software reset S3D engine */
832 /* EXT_MISC_CNTL_1, CR66 bit 0 should be the same as bit 0 MR_ADVANCED_FUNCTION_CONTROL - check */
833 wl_mmio(MR_ADVANCED_FUNCTION_CONTROL, 0x00000011); /* enhanced mode, linear addressing */
834
835/* crtc registers */
836
837 wcrt(CRT_ID_PRESET_ROW_SCAN, 0x00);
838
839 /* Disable h/w cursor */
840
841 wcrt(CRT_ID_CURSOR_START, 0x00);
842 wcrt(CRT_ID_CURSOR_END, 0x00);
843 wcrt(CRT_ID_START_ADDR_HIGH, 0x00);
844 wcrt(CRT_ID_START_ADDR_LOW, 0x00);
845 wcrt(CRT_ID_CURSOR_LOC_HIGH, 0x00);
846 wcrt(CRT_ID_CURSOR_LOC_LOW, 0x00);
847 wcrt(CRT_ID_EXT_MODE, 0x00);
848 wcrt(CRT_ID_HWGC_MODE, 0x00);
849 wcrt(CRT_ID_HWGC_ORIGIN_X_HI, 0x00);
850 wcrt(CRT_ID_HWGC_ORIGIN_X_LO, 0x00);
851 wcrt(CRT_ID_HWGC_ORIGIN_Y_HI, 0x00);
852 wcrt(CRT_ID_HWGC_ORIGIN_Y_LO, 0x00);
853 i = rcrt(CRT_ID_HWGC_MODE);
854 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
855 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
856 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
857 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
858 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
859 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
860 wcrt(CRT_ID_HWGC_START_AD_HI, 0x00);
861 wcrt(CRT_ID_HWGC_START_AD_LO, 0x00);
862 wcrt(CRT_ID_HWGC_DSTART_X, 0x00);
863 wcrt(CRT_ID_HWGC_DSTART_Y, 0x00);
864
865 wcrt(CRT_ID_UNDERLINE_LOC, 0x00);
866
867 wcrt(CRT_ID_MODE_CONTROL, 0xe3);
868 wcrt(CRT_ID_BACKWAD_COMP_2, 0x22); /* blank bdr bit 5 blanking only on 8 bit */
869
870 wcrt(CRT_ID_EX_SYNC_1, 0x00);
871
872 /* memory */
873
874 wcrt(CRT_ID_EXT_SYS_CNTL_3, 0x00);
875 wcrt(CRT_ID_MEMORY_CONF, 0x08); /* config enhanced map */
876 wcrt(CRT_ID_EXT_MEM_CNTL_1, 0x08); /* MMIO Select (0x0c works as well)*/
877 wcrt(CRT_ID_EXT_MEM_CNTL_2, 0x02); /* why 02 big endian 00 works ? */
878 wcrt(CRT_ID_EXT_MEM_CNTL_4, 0x9f); /* config big endian - 0x00 ? */
879 wcrt(CRT_ID_LAW_POS_HI, 0x00);
880 wcrt(CRT_ID_LAW_POS_LO, 0x00);
881 wcrt(CRT_ID_EXT_MISC_CNTL_1, 0x81);
882 wcrt(CRT_ID_MISC_1, 0x90); /* must follow CRT_ID_EXT_MISC_CNTL_1 */
883 wcrt(CRT_ID_LAW_CNTL, 0x13); /* force 4 Meg for test */
884 if (cv3d_has_4mb()) {
885 v_ram_size = 0x00400000;
886 wcrt(CRT_ID_LAW_CNTL, 0x13); /* 4 MB */
887 } else {
888 v_ram_size = 0x00200000;
889 wcrt(CRT_ID_LAW_CNTL, 0x12); /* 2 MB */
890 }
891
892 if (on_zorro2)
893 v_ram_size -= 0x60000; /* we need some space for the registers */
894
895 wcrt(CRT_ID_EXT_SYS_CNTL_4, 0x00);
896 wcrt(CRT_ID_EXT_DAC_CNTL, 0x00); /* 0x10 for X11 cursor mode */
897
898/* sequencer registers */
899
900 wseq(SEQ_ID_CLOCKING_MODE, 0x01); /* 8 dot clock */
901 wseq(SEQ_ID_MAP_MASK, 0xff);
902 wseq(SEQ_ID_CHAR_MAP_SELECT, 0x00);
903 wseq(SEQ_ID_MEMORY_MODE, 0x02);
904 wseq(SEQ_ID_RAMDAC_CNTL, 0x00);
905 wseq(SEQ_ID_SIGNAL_SELECT, 0x00);
906 wseq(SEQ_ID_EXT_SEQ_REG9, 0x00); /* MMIO and PIO reg access enabled */
907 wseq(SEQ_ID_EXT_MISC_SEQ, 0x00);
908 wseq(SEQ_ID_CLKSYN_CNTL_1, 0x00);
909 wseq(SEQ_ID_EXT_SEQ, 0x00);
910
911/* graphic registers */
912
913 wgfx(GCT_ID_SET_RESET, 0x00);
914 wgfx(GCT_ID_ENABLE_SET_RESET, 0x00);
915 wgfx(GCT_ID_COLOR_COMPARE, 0x00);
916 wgfx(GCT_ID_DATA_ROTATE, 0x00);
917 wgfx(GCT_ID_READ_MAP_SELECT, 0x00);
918 wgfx(GCT_ID_GRAPHICS_MODE, 0x40);
919 wgfx(GCT_ID_MISC, 0x01);
920 wgfx(GCT_ID_COLOR_XCARE, 0x0f);
921 wgfx(GCT_ID_BITMASK, 0xff);
922
923/* attribute registers */
924
925 for(i = 0; i <= 15; i++)
926 watr(ACT_ID_PALETTE0 + i, i);
927 watr(ACT_ID_ATTR_MODE_CNTL, 0x41);
928 watr(ACT_ID_OVERSCAN_COLOR, 0xff);
929 watr(ACT_ID_COLOR_PLANE_ENA, 0x0f);
930 watr(ACT_ID_HOR_PEL_PANNING, 0x00);
931 watr(ACT_ID_COLOR_SELECT, 0x00);
932
933 wb_mmio(VDAC_MASK, 0xff);
934
935/* init local cmap as greyscale levels */
936
937 for (i = 0; i < 256; i++) {
938 virgefb_colour_table [i][0] = i;
939 virgefb_colour_table [i][1] = i;
940 virgefb_colour_table [i][2] = i;
941 }
942
943/* clear framebuffer memory */
944
945 memset((char*)v_ram, 0x00, v_ram_size);
946
947 DPRINTK("EXIT\n");
948 return 0;
949}
950
951
952/*
953 * This function should fill in the `fix' structure based on the
954 * values in the `par' structure.
955 */
956
957static int virgefb_encode_fix(struct fb_fix_screeninfo *fix,
958 struct virgefb_par *par)
959{
960 DPRINTK("ENTER set video phys addr\n");
961
962 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
963 strcpy(fix->id, virgefb_name);
964 if (on_zorro2)
965 fix->smem_start = v_ram_phys;
966 switch (par->var.bits_per_pixel) {
967#ifdef FBCON_HAS_CFB8
968 case 8:
969 if (on_zorro2)
970 Select_Zorro2_FrameBuffer(ENDIAN_BYTE);
971 else
972 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_8);
973 break;
974#endif
975#ifdef FBCON_HAS_CFB16
976 case 16:
977 if (on_zorro2)
978 Select_Zorro2_FrameBuffer(ENDIAN_WORD);
979 else
980 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_16);
981 break;
982#endif
983#ifdef FBCON_HAS_CFB32
984 case 32:
985 if (on_zorro2)
986 Select_Zorro2_FrameBuffer(ENDIAN_LONG);
987 else
988 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_32);
989 break;
990#endif
991 }
992
993 fix->smem_len = v_ram_size;
994 fix->mmio_start = mmio_regs_phys;
995 fix->mmio_len = 0x10000; /* TODO: verify this for the CV64/3D */
996
997 fix->type = FB_TYPE_PACKED_PIXELS;
998 fix->type_aux = 0;
999 if (par->var.bits_per_pixel == 8)
1000 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1001 else
1002 fix->visual = FB_VISUAL_TRUECOLOR;
1003
1004 fix->xpanstep = 0;
1005 fix->ypanstep = 0;
1006 fix->ywrapstep = 0;
1007 fix->line_length = par->var.xres_virtual*par->var.bits_per_pixel/8;
1008 fix->accel = FB_ACCEL_S3_VIRGE;
1009 DPRINTK("EXIT v_ram_phys = 0x%8.8lx\n", (unsigned long)fix->smem_start);
1010 return 0;
1011}
1012
1013
1014/*
1015 * Fill the `par' structure based on the values in `var'.
1016 * TODO: Verify and adjust values, return -EINVAL if bad.
1017 */
1018
1019static int virgefb_decode_var(struct fb_var_screeninfo *var,
1020 struct virgefb_par *par)
1021{
1022 DPRINTK("ENTER\n");
1023 par->var.xres = var->xres;
1024 par->var.yres = var->yres;
1025 par->var.xres_virtual = var->xres_virtual;
1026 par->var.yres_virtual = var->yres_virtual;
1027 /* roundup and validate */
1028 par->var.xres = (par->var.xres+7) & ~7;
1029 par->var.xres_virtual = (par->var.xres_virtual+7) & ~7;
1030 if (par->var.xres_virtual < par->var.xres)
1031 par->var.xres_virtual = par->var.xres;
1032 if (par->var.yres_virtual < par->var.yres)
1033 par->var.yres_virtual = par->var.yres;
1034 par->var.xoffset = var->xoffset;
1035 par->var.yoffset = var->yoffset;
1036 par->var.bits_per_pixel = var->bits_per_pixel;
1037 if (par->var.bits_per_pixel <= 8)
1038 par->var.bits_per_pixel = 8;
1039 else if (par->var.bits_per_pixel <= 16)
1040 par->var.bits_per_pixel = 16;
1041 else
1042 par->var.bits_per_pixel = 32;
1043#ifndef FBCON_HAS_CFB32
1044 if (par->var.bits_per_pixel == 32)
1045 par->var.bits_per_pixel = 16;
1046#endif
1047#ifndef FBCON_HAS_CFB16
1048 if (par->var.bits_per_pixel == 16)
1049 par->var.bits_per_pixel = 8;
1050#endif
1051 par->var.grayscale = var->grayscale;
1052 par->var.red = var->red;
1053 par->var.green = var->green;
1054 par->var.blue = var->blue;
1055 par->var.transp = var->transp;
1056 par->var.nonstd = var->nonstd;
1057 par->var.activate = var->activate;
1058 par->var.height = var->height;
1059 par->var.width = var->width;
1060 if (var->accel_flags & FB_ACCELF_TEXT) {
1061 par->var.accel_flags = FB_ACCELF_TEXT;
1062 } else {
1063 par->var.accel_flags = 0;
1064 }
1065 par->var.pixclock = var->pixclock;
1066 par->var.left_margin = var->left_margin;
1067 par->var.right_margin = var->right_margin;
1068 par->var.upper_margin = var->upper_margin;
1069 par->var.lower_margin = var->lower_margin;
1070 par->var.hsync_len = var->hsync_len;
1071 par->var.vsync_len = var->vsync_len;
1072 par->var.sync = var->sync;
1073 par->var.vmode = var->vmode;
1074 DPRINTK("EXIT\n");
1075 return 0;
1076}
1077
1078/*
1079 * Fill the `var' structure based on the values in `par' and maybe
1080 * other values read out of the hardware.
1081 */
1082
1083static int virgefb_encode_var(struct fb_var_screeninfo *var,
1084 struct virgefb_par *par)
1085{
1086 DPRINTK("ENTER\n");
1087 memset(var, 0, sizeof(struct fb_var_screeninfo)); /* need this ? */
1088 var->xres = par->var.xres;
1089 var->yres = par->var.yres;
1090 var->xres_virtual = par->var.xres_virtual;
1091 var->yres_virtual = par->var.yres_virtual;
1092 var->xoffset = par->var.xoffset;
1093 var->yoffset = par->var.yoffset;
1094 var->bits_per_pixel = par->var.bits_per_pixel;
1095 var->grayscale = par->var.grayscale;
1096 var->red = par->var.red;
1097 var->green = par->var.green;
1098 var->blue = par->var.blue;
1099 var->transp = par->var.transp;
1100 var->nonstd = par->var.nonstd;
1101 var->activate = par->var.activate;
1102 var->height = par->var.height;
1103 var->width = par->var.width;
1104 var->accel_flags = par->var.accel_flags;
1105 var->pixclock = par->var.pixclock;
1106 var->left_margin = par->var.left_margin;
1107 var->right_margin = par->var.right_margin;
1108 var->upper_margin = par->var.upper_margin;
1109 var->lower_margin = par->var.lower_margin;
1110 var->hsync_len = par->var.hsync_len;
1111 var->vsync_len = par->var.vsync_len;
1112 var->sync = par->var.sync;
1113 var->vmode = par->var.vmode;
1114 DPRINTK("EXIT\n");
1115 return 0;
1116}
1117
1118/*
1119 * Set a single color register. The values supplied are already
1120 * rounded down to the hardware's capabilities (according to the
1121 * entries in the var structure). Return != 0 for invalid regno.
1122 */
1123
1124static int virgefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1125 u_int transp, struct fb_info *info)
1126{
1127 DPRINTK("ENTER\n");
1128 if (((current_par.var.bits_per_pixel==8) && (regno>255)) ||
1129 ((current_par.var.bits_per_pixel!=8) && (regno>15))) {
1130 DPRINTK("EXIT\n");
1131 return 1;
1132 }
1133 if (((current_par.var.bits_per_pixel==8) && (regno<256)) ||
1134 ((current_par.var.bits_per_pixel!=8) && (regno<16))) {
1135 virgefb_colour_table [regno][0] = red >> 10;
1136 virgefb_colour_table [regno][1] = green >> 10;
1137 virgefb_colour_table [regno][2] = blue >> 10;
1138 }
1139
1140 switch (current_par.var.bits_per_pixel) {
1141#ifdef FBCON_HAS_CFB8
1142 case 8:
1143 wb_mmio(VDAC_ADDRESS_W, (unsigned char)regno);
1144 wb_mmio(VDAC_DATA, ((unsigned char)(red >> 10)));
1145 wb_mmio(VDAC_DATA, ((unsigned char)(green >> 10)));
1146 wb_mmio(VDAC_DATA, ((unsigned char)(blue >> 10)));
1147 break;
1148#endif
1149#ifdef FBCON_HAS_CFB16
1150 case 16:
1151 fbcon_cmap.cfb16[regno] =
1152 ((red & 0xf800) |
1153 ((green & 0xfc00) >> 5) |
1154 ((blue & 0xf800) >> 11));
1155 break;
1156#endif
1157#ifdef FBCON_HAS_CFB32
1158 case 32:
1159 fbcon_cmap.cfb32[regno] =
1160 /* transp = 0's or 1's ? */
1161 (((red & 0xff00) << 8) |
1162 ((green & 0xff00) >> 0) |
1163 ((blue & 0xff00) >> 8));
1164 break;
1165#endif
1166 }
1167 DPRINTK("EXIT\n");
1168 return 0;
1169}
1170
1171
1172/*
1173 * Read a single color register and split it into
1174 * colors/transparent. Return != 0 for invalid regno.
1175 */
1176
1177static int virgefb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
1178 u_int *transp, struct fb_info *info)
1179{
1180 int t;
1181
1182 DPRINTK("ENTER\n");
1183 if (regno > 255) {
1184 DPRINTK("EXIT\n");
1185 return 1;
1186 }
1187 if (((current_par.var.bits_per_pixel==8) && (regno<256)) ||
1188 ((current_par.var.bits_per_pixel!=8) && (regno<16))) {
1189
1190 t = virgefb_colour_table [regno][0];
1191 *red = (t<<10) | (t<<4) | (t>>2);
1192 t = virgefb_colour_table [regno][1];
1193 *green = (t<<10) | (t<<4) | (t>>2);
1194 t = virgefb_colour_table [regno][2];
1195 *blue = (t<<10) | (t<<4) | (t>>2);
1196 }
1197 *transp = 0;
1198 DPRINTK("EXIT\n");
1199 return 0;
1200}
1201
1202
1203/*
1204 * (Un)Blank the screen
1205 */
1206
1207static void virgefb_gfx_on_off(int blank)
1208{
1209 DPRINTK("ENTER\n");
1210 gfx_on_off(blank);
1211 DPRINTK("EXIT\n");
1212}
1213
1214/*
1215 * CV3D low-level support
1216 */
1217
1218
1219static inline void wait_3d_fifo_slots(int n) /* WaitQueue */
1220{
1221 do {
1222 mb();
1223 } while (((rl_mmio(MR_SUBSYSTEM_STATUS_R) >> 8) & 0x1f) < (n + 2));
1224}
1225
1226static inline void virgefb_wait_for_idle(void) /* WaitIdle */
1227{
1228 while(!(rl_mmio(MR_SUBSYSTEM_STATUS_R) & 0x2000)) ;
1229 blit_maybe_busy = 0;
1230}
1231
1232 /*
1233 * BitBLT - Through the Plane
1234 */
1235
1236static void virgefb_BitBLT(u_short curx, u_short cury, u_short destx, u_short desty,
1237 u_short width, u_short height, u_short stride, u_short depth)
1238{
1239 unsigned int blitcmd = S3V_BITBLT | S3V_DRAW | S3V_BLT_COPY;
1240
1241 switch (depth) {
1242#ifdef FBCON_HAS_CFB8
1243 case 8 :
1244 blitcmd |= S3V_DST_8BPP;
1245 break;
1246#endif
1247#ifdef FBCON_HAS_CFB16
1248 case 16 :
1249 blitcmd |= S3V_DST_16BPP;
1250 break;
1251#endif
1252#ifdef FBCON_HAS_CFB32
1253 case 32 :
1254 /* 32 bit uses 2 by 16 bit values, see fbcon_virge32_bmove */
1255 blitcmd |= S3V_DST_16BPP;
1256 break;
1257#endif
1258 }
1259
1260 /* Set drawing direction */
1261 /* -Y, X maj, -X (default) */
1262 if (curx > destx) {
1263 blitcmd |= (1 << 25); /* Drawing direction +X */
1264 } else {
1265 curx += (width - 1);
1266 destx += (width - 1);
1267 }
1268
1269 if (cury > desty) {
1270 blitcmd |= (1 << 26); /* Drawing direction +Y */
1271 } else {
1272 cury += (height - 1);
1273 desty += (height - 1);
1274 }
1275
1276 wait_3d_fifo_slots(8); /* wait on fifo slots for 8 writes */
1277
1278 if (blit_maybe_busy)
1279 virgefb_wait_for_idle();
1280 blit_maybe_busy = 1;
1281
1282 wl_mmio(BLT_PATTERN_COLOR, 1); /* pattern fb color */
1283 wl_mmio(BLT_MONO_PATTERN_0, ~0);
1284 wl_mmio(BLT_MONO_PATTERN_1, ~0);
1285 wl_mmio(BLT_SIZE_X_Y, ((width << 16) | height));
1286 wl_mmio(BLT_SRC_X_Y, ((curx << 16) | cury));
1287 wl_mmio(BLT_DEST_X_Y, ((destx << 16) | desty));
1288 wl_mmio(BLT_SRC_DEST_STRIDE, (((stride << 16) | stride) /* & 0x0ff80ff8 */)); /* why is this needed now ? */
1289 wl_mmio(BLT_COMMAND_SET, blitcmd);
1290}
1291
1292/*
1293 * Rectangle Fill Solid
1294 */
1295
1296static void virgefb_RectFill(u_short x, u_short y, u_short width, u_short height,
1297 u_short color, u_short stride, u_short depth)
1298{
1299 unsigned int blitcmd = S3V_RECTFILL | S3V_DRAW |
1300 S3V_BLT_CLEAR | S3V_MONO_PAT | (1 << 26) | (1 << 25);
1301
1302 switch (depth) {
1303#ifdef FBCON_HAS_CFB8
1304 case 8 :
1305 blitcmd |= S3V_DST_8BPP;
1306 break;
1307#endif
1308#ifdef FBCON_HAS_CFB16
1309 case 16 :
1310 blitcmd |= S3V_DST_16BPP;
1311 break;
1312#endif
1313#ifdef FBCON_HAS_CFB32
1314 case 32 :
1315 /* 32 bit uses 2 times 16 bit values, see fbcon_virge32_clear */
1316 blitcmd |= S3V_DST_16BPP;
1317 break;
1318#endif
1319 }
1320
1321 wait_3d_fifo_slots(5); /* wait on fifo slots for 5 writes */
1322
1323 if (blit_maybe_busy)
1324 virgefb_wait_for_idle();
1325 blit_maybe_busy = 1;
1326
1327 wl_mmio(BLT_PATTERN_COLOR, (color & 0xff));
1328 wl_mmio(BLT_SIZE_X_Y, ((width << 16) | height));
1329 wl_mmio(BLT_DEST_X_Y, ((x << 16) | y));
1330 wl_mmio(BLT_SRC_DEST_STRIDE, (((stride << 16) | stride) /* & 0x0ff80ff8 */));
1331 wl_mmio(BLT_COMMAND_SET, blitcmd);
1332}
1333
1334/*
1335 * Move cursor to x, y
1336 */
1337
1338#if 0
1339static void virgefb_move_cursor(u_short x, u_short y)
1340{
1341 DPRINTK("Yuck .... MoveCursor on a 3D\n");
1342 return 0;
1343}
1344#endif
1345
1346/* -------------------- Interfaces to hardware functions -------------------- */
1347
1348static struct fb_hwswitch virgefb_hw_switch = {
1349 .init = virge_init,
1350 .encode_fix = virgefb_encode_fix,
1351 .decode_var = virgefb_decode_var,
1352 .encode_var = virgefb_encode_var,
1353 .getcolreg = virgefb_getcolreg,
1354 .blank = virgefb_gfx_on_off
1355};
1356
1357
1358/* -------------------- Generic routines ------------------------------------ */
1359
1360
1361/*
1362 * Fill the hardware's `par' structure.
1363 */
1364
1365static void virgefb_get_par(struct virgefb_par *par)
1366{
1367 DPRINTK("ENTER\n");
1368 if (current_par_valid) {
1369 *par = current_par;
1370 } else {
1371 fbhw->decode_var(&virgefb_default, par);
1372 }
1373 DPRINTK("EXIT\n");
1374}
1375
1376
1377static void virgefb_set_par(struct virgefb_par *par)
1378{
1379 DPRINTK("ENTER\n");
1380 current_par = *par;
1381 current_par_valid = 1;
1382 DPRINTK("EXIT\n");
1383}
1384
1385
1386static void virgefb_set_video(struct fb_var_screeninfo *var)
1387{
1388/* Set clipping rectangle to current screen size */
1389
1390 unsigned int clip;
1391
1392 DPRINTK("ENTER\n");
1393 wait_3d_fifo_slots(4);
1394 clip = ((0 << 16) | (var->xres - 1));
1395 wl_mmio(BLT_CLIP_LEFT_RIGHT, clip);
1396 clip = ((0 << 16) | (var->yres - 1));
1397 wl_mmio(BLT_CLIP_TOP_BOTTOM, clip);
1398 wl_mmio(BLT_SRC_BASE, 0); /* seems we need to clear these two */
1399 wl_mmio(BLT_DEST_BASE, 0);
1400
1401/* Load the video mode defined by the 'var' data */
1402
1403 virgefb_load_video_mode(var);
1404 DPRINTK("EXIT\n");
1405}
1406
1407/*
1408Merge these two functions, Geert's suggestion.
1409static int virgefb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info);
1410static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive);
1411*/
1412
1413static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive)
1414{
1415 int err, activate;
1416 struct virgefb_par par;
1417
1418 DPRINTK("ENTER\n");
1419 if ((err = fbhw->decode_var(var, &par))) {
1420 DPRINTK("EXIT\n");
1421 return (err);
1422 }
1423
1424 activate = var->activate;
1425 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW && isactive)
1426 virgefb_set_par(&par);
1427 fbhw->encode_var(var, &par);
1428 var->activate = activate;
1429 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW && isactive)
1430 virgefb_set_video(var);
1431 DPRINTK("EXIT\n");
1432 return 0;
1433}
1434
1435
1436/*
1437 * Get the Fixed Part of the Display
1438 */
1439
1440static int virgefb_get_fix(struct fb_fix_screeninfo *fix, int con,
1441 struct fb_info *info)
1442{
1443 struct virgefb_par par;
1444 int error = 0;
1445
1446 DPRINTK("ENTER\n");
1447 if (con == -1)
1448 virgefb_get_par(&par);
1449 else
1450 error = fbhw->decode_var(&fb_display[con].var, &par);
1451
1452 if (!error)
1453 error = fbhw->encode_fix(fix, &par);
1454 DPRINTK("EXIT\n");
1455 return(error);
1456}
1457
1458
1459/*
1460 * Get the User Defined Part of the Display
1461 */
1462
1463static int virgefb_get_var(struct fb_var_screeninfo *var, int con,
1464 struct fb_info *info)
1465{
1466 struct virgefb_par par;
1467 int error = 0;
1468
1469 DPRINTK("ENTER\n");
1470 if (con == -1) {
1471 virgefb_get_par(&par);
1472 error = fbhw->encode_var(var, &par);
1473 disp.var = *var; /* ++Andre: don't know if this is the right place */
1474 } else {
1475 *var = fb_display[con].var;
1476 }
1477 DPRINTK("EXIT\n");
1478 return(error);
1479}
1480
1481static void virgefb_set_disp(int con, struct fb_info *info)
1482{
1483 struct fb_fix_screeninfo fix;
1484 struct display *display;
1485
1486 DPRINTK("ENTER\n");
1487 if (con >= 0)
1488 display = &fb_display[con];
1489 else
1490 display = &disp; /* used during initialization */
1491
1492 virgefb_get_fix(&fix, con, info);
1493 if (con == -1)
1494 con = 0;
1495 if(on_zorro2) {
1496 info->screen_base = (char*)v_ram;
1497 } else {
1498 switch (display->var.bits_per_pixel) {
1499#ifdef FBCON_HAS_CFB8
1500 case 8:
1501 info->screen_base = (char*)(v_ram + CYBMEM_OFFSET_8);
1502 break;
1503#endif
1504#ifdef FBCON_HAS_CFB16
1505 case 16:
1506 info->screen_base = (char*)(v_ram + CYBMEM_OFFSET_16);
1507 break;
1508#endif
1509#ifdef FBCON_HAS_CFB32
1510 case 32:
1511 info->screen_base = (char*)(v_ram + CYBMEM_OFFSET_32);
1512 break;
1513#endif
1514 }
1515 }
1516 display->visual = fix.visual;
1517 display->type = fix.type;
1518 display->type_aux = fix.type_aux;
1519 display->ypanstep = fix.ypanstep;
1520 display->ywrapstep = fix.ywrapstep;
1521 display->can_soft_blank = 1;
1522 display->inverse = virgefb_inverse;
1523 display->line_length = display->var.xres_virtual*
1524 display->var.bits_per_pixel/8;
1525
1526 switch (display->var.bits_per_pixel) {
1527#ifdef FBCON_HAS_CFB8
1528 case 8:
1529 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1530 display->dispsw = &fbcon_virge8;
1531#warning FIXME: We should reinit the graphics engine here
1532 } else
1533 display->dispsw = &fbcon_cfb8;
1534 break;
1535#endif
1536#ifdef FBCON_HAS_CFB16
1537 case 16:
1538 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1539 display->dispsw = &fbcon_virge16;
1540 } else
1541 display->dispsw = &fbcon_cfb16;
1542 display->dispsw_data = &fbcon_cmap.cfb16;
1543 break;
1544#endif
1545#ifdef FBCON_HAS_CFB32
1546 case 32:
1547 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1548 display->dispsw = &fbcon_virge32;
1549 } else
1550 display->dispsw = &fbcon_cfb32;
1551 display->dispsw_data = &fbcon_cmap.cfb32;
1552 break;
1553#endif
1554 default:
1555 display->dispsw = &fbcon_dummy;
1556 break;
1557 }
1558 DPRINTK("EXIT v_ram virt = 0x%8.8lx\n",(unsigned long)display->screen_base);
1559}
1560
1561
1562/*
1563 * Set the User Defined Part of the Display
1564 */
1565
1566static int virgefb_set_var(struct fb_var_screeninfo *var, int con,
1567 struct fb_info *info)
1568{
1569 int err, oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel;
1570
1571 DPRINTK("ENTER\n");
1572
1573 if ((err = virgefb_do_fb_set_var(var, con == info->currcon))) {
1574 DPRINTK("EXIT\n");
1575 return(err);
1576 }
1577 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1578 oldxres = fb_display[con].var.xres;
1579 oldyres = fb_display[con].var.yres;
1580 oldvxres = fb_display[con].var.xres_virtual;
1581 oldvyres = fb_display[con].var.yres_virtual;
1582 oldbpp = fb_display[con].var.bits_per_pixel;
1583 oldaccel = fb_display[con].var.accel_flags;
1584 fb_display[con].var = *var;
1585 if (oldxres != var->xres || oldyres != var->yres ||
1586 oldvxres != var->xres_virtual ||
1587 oldvyres != var->yres_virtual ||
1588 oldbpp != var->bits_per_pixel ||
1589 oldaccel != var->accel_flags) {
1590 virgefb_set_disp(con, info);
1591 if (fb_info.changevar)
1592 (*fb_info.changevar)(con);
1593 fb_alloc_cmap(&fb_display[con].cmap, 0, 0);
1594 do_install_cmap(con, info);
1595 }
1596 }
1597 var->activate = 0;
1598 DPRINTK("EXIT\n");
1599 return 0;
1600}
1601
1602
1603/*
1604 * Get the Colormap
1605 */
1606
1607static int virgefb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1608 struct fb_info *info)
1609{
1610 DPRINTK("ENTER\n");
1611 if (con == info->currcon) { /* current console? */
1612 DPRINTK("EXIT - console is current console, fb_get_cmap\n");
1613 return(fb_get_cmap(cmap, kspc, fbhw->getcolreg, info));
1614 } else if (fb_display[con].cmap.len) { /* non default colormap? */
1615 DPRINTK("Use console cmap\n");
1616 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1617 } else {
1618 DPRINTK("Use default cmap\n");
1619 fb_copy_cmap(fb_default_cmap(fb_display[con].var.bits_per_pixel==8 ? 256 : 16),
1620 cmap, kspc ? 0 : 2);
1621 }
1622 DPRINTK("EXIT\n");
1623 return 0;
1624}
1625
1626static struct fb_ops virgefb_ops = {
1627 .owner = THIS_MODULE,
1628 .fb_get_fix = virgefb_get_fix,
1629 .fb_get_var = virgefb_get_var,
1630 .fb_set_var = virgefb_set_var,
1631 .fb_get_cmap = virgefb_get_cmap,
1632 .fb_set_cmap = gen_set_cmap,
1633 .fb_setcolreg = virgefb_setcolreg,
1634 .fb_blank = virgefb_blank,
1635};
1636
1637int __init virgefb_setup(char *options)
1638{
1639 char *this_opt;
1640 fb_info.fontname[0] = '\0';
1641
1642 DPRINTK("ENTER\n");
1643 if (!options || !*options) {
1644 DPRINTK("EXIT\n");
1645 return 0;
1646 }
1647
1648 while ((this_opt = strsep(&options, ",")) != NULL) {
1649 if (!*this_opt)
1650 continue;
1651 if (!strcmp(this_opt, "inverse")) {
1652 virgefb_inverse = 1;
1653 fb_invert_cmaps();
1654 } else if (!strncmp(this_opt, "font:", 5))
1655 strcpy(fb_info.fontname, this_opt+5);
1656#ifdef FBCON_HAS_CFB8
1657 else if (!strcmp (this_opt, "virge8")){
1658 virgefb_default = virgefb_predefined[VIRGE8_DEFMODE].var;
1659 }
1660#endif
1661#ifdef FBCON_HAS_CFB16
1662 else if (!strcmp (this_opt, "virge16")){
1663 virgefb_default = virgefb_predefined[VIRGE16_DEFMODE].var;
1664 }
1665#endif
1666#ifdef FBCON_HAS_CFB32
1667 else if (!strcmp (this_opt, "virge32")){
1668 virgefb_default = virgefb_predefined[VIRGE32_DEFMODE].var;
1669 }
1670#endif
1671 else
1672 virgefb_get_video_mode(this_opt);
1673 }
1674
1675 printk(KERN_INFO "mode : xres=%d, yres=%d, bpp=%d\n", virgefb_default.xres,
1676 virgefb_default.yres, virgefb_default.bits_per_pixel);
1677 DPRINTK("EXIT\n");
1678 return 0;
1679}
1680
1681
1682/*
1683 * Get a Video Mode
1684 */
1685
1686static int __init virgefb_get_video_mode(const char *name)
1687{
1688 int i;
1689
1690 DPRINTK("ENTER\n");
1691 for (i = 0; i < NUM_TOTAL_MODES; i++) {
1692 if (!strcmp(name, virgefb_predefined[i].name)) {
1693 virgefb_default = virgefb_predefined[i].var;
1694 DPRINTK("EXIT\n");
1695 return(i);
1696 }
1697 }
1698 /* ++Andre: set virgefb default mode */
1699
1700/* prefer 16 bit depth, 8 if no 16, if no 8 or 16 use 32 */
1701
1702#ifdef FBCON_HAS_CFB32
1703 virgefb_default = virgefb_predefined[VIRGE32_DEFMODE].var;
1704#endif
1705#ifdef FBCON_HAS_CFB8
1706 virgefb_default = virgefb_predefined[VIRGE8_DEFMODE].var;
1707#endif
1708#ifdef FBCON_HAS_CFB16
1709 virgefb_default = virgefb_predefined[VIRGE16_DEFMODE].var;
1710#endif
1711 DPRINTK("EXIT\n");
1712 return 0;
1713}
1714
1715/*
1716 * Initialization
1717 */
1718
1719int __init virgefb_init(void)
1720{
1721 struct virgefb_par par;
1722 unsigned long board_addr, board_size;
1723 struct zorro_dev *z = NULL;
1724
1725 DPRINTK("ENTER\n");
1726
1727 z = zorro_find_device(ZORRO_PROD_PHASE5_CYBERVISION64_3D, NULL);
1728 if (!z)
1729 return -ENODEV;
1730
1731 board_addr = z->resource.start;
1732 if (board_addr < 0x01000000) {
1733
1734 /* board running in Z2 space. This includes the video memory
1735 as well as the S3 register set */
1736
1737 on_zorro2 = 1;
1738 board_size = 0x00400000;
1739
1740 if (!request_mem_region(board_addr, board_size, "S3 ViRGE"))
1741 return -ENOMEM;
1742
1743 v_ram_phys = board_addr;
1744 v_ram = ZTWO_VADDR(v_ram_phys);
1745 mmio_regs_phys = (unsigned long)(board_addr + 0x003c0000);
1746 vgaio_regs = (unsigned char *) ZTWO_VADDR(board_addr + 0x003c0000);
1747 mmio_regs = (unsigned char *)ZTWO_VADDR(mmio_regs_phys);
1748 vcode_switch_base = (unsigned long) ZTWO_VADDR(board_addr + 0x003a0000);
1749 printk(KERN_INFO "CV3D detected running in Z2 mode.\n");
1750
1751 } else {
1752
1753 /* board running in Z3 space. Separate video memory (3 apertures)
1754 and S3 register set */
1755
1756 on_zorro2 = 0;
1757 board_size = 0x01000000;
1758
1759 if (!request_mem_region(board_addr, board_size, "S3 ViRGE"))
1760 return -ENOMEM;
1761
1762 v_ram_phys = board_addr + 0x04000000;
1763 v_ram = (unsigned long)ioremap(v_ram_phys, 0x01000000);
1764 mmio_regs_phys = board_addr + 0x05000000;
1765 vgaio_regs = (unsigned char *)ioremap(board_addr +0x0c000000, 0x00100000); /* includes PCI regs */
1766 mmio_regs = ioremap(mmio_regs_phys, 0x00010000);
1767 vcode_switch_base = (unsigned long)ioremap(board_addr + 0x08000000, 0x1000);
1768 printk(KERN_INFO "CV3D detected running in Z3 mode\n");
1769 }
1770
1771#if defined (VIRGEFBDEBUG)
1772 DPRINTK("board_addr : 0x%8.8lx\n",board_addr);
1773 DPRINTK("board_size : 0x%8.8lx\n",board_size);
1774 DPRINTK("mmio_regs_phy : 0x%8.8lx\n",mmio_regs_phys);
1775 DPRINTK("v_ram_phys : 0x%8.8lx\n",v_ram_phys);
1776 DPRINTK("vgaio_regs : 0x%8.8lx\n",(unsigned long)vgaio_regs);
1777 DPRINTK("mmio_regs : 0x%8.8lx\n",(unsigned long)mmio_regs);
1778 DPRINTK("v_ram : 0x%8.8lx\n",v_ram);
1779 DPRINTK("vcode sw base : 0x%8.8lx\n",vcode_switch_base);
1780#endif
1781 fbhw = &virgefb_hw_switch;
1782 strcpy(fb_info.modename, virgefb_name);
1783 fb_info.changevar = NULL;
1784 fb_info.fbops = &virgefb_ops;
1785 fb_info.disp = &disp;
1786 fb_info.currcon = -1;
1787 fb_info.switch_con = &virgefb_switch;
1788 fb_info.updatevar = &virgefb_updatevar;
1789 fb_info.flags = FBINFO_FLAG_DEFAULT;
1790 fbhw->init();
1791 fbhw->decode_var(&virgefb_default, &par);
1792 fbhw->encode_var(&virgefb_default, &par);
1793 virgefb_do_fb_set_var(&virgefb_default, 1);
1794 virgefb_get_var(&fb_display[0].var, -1, &fb_info);
1795 virgefb_set_disp(-1, &fb_info);
1796 do_install_cmap(0, &fb_info);
1797
1798 if (register_framebuffer(&fb_info) < 0) {
1799 #warning release resources
1800 printk(KERN_ERR "virgefb.c: register_framebuffer failed\n");
1801 DPRINTK("EXIT\n");
1802 goto out_unmap;
1803 }
1804
1805 printk(KERN_INFO "fb%d: %s frame buffer device, using %ldK of video memory\n",
1806 fb_info.node, fb_info.modename, v_ram_size>>10);
1807
1808 /* TODO: This driver cannot be unloaded yet */
1809
1810 DPRINTK("EXIT\n");
1811 return 0;
1812
1813out_unmap:
1814 if (board_addr >= 0x01000000) {
1815 if (v_ram)
1816 iounmap((void*)v_ram);
1817 if (vgaio_regs)
1818 iounmap(vgaio_regs);
1819 if (mmio_regs)
1820 iounmap(mmio_regs);
1821 if (vcode_switch_base)
1822 iounmap((void*)vcode_switch_base);
1823 v_ram = vcode_switch_base = 0;
1824 vgaio_regs = mmio_regs = NULL;
1825 }
1826 return -EINVAL;
1827}
1828
1829
1830static int virgefb_switch(int con, struct fb_info *info)
1831{
1832 DPRINTK("ENTER\n");
1833 /* Do we have to save the colormap? */
1834 if (fb_display[info->currcon].cmap.len)
1835 fb_get_cmap(&fb_display[info->currcon].cmap, 1,
1836 fbhw->getcolreg, info);
1837 virgefb_do_fb_set_var(&fb_display[con].var, 1);
1838 info->currcon = con;
1839 /* Install new colormap */
1840 do_install_cmap(con, info);
1841 DPRINTK("EXIT\n");
1842 return 0;
1843}
1844
1845
1846/*
1847 * Update the `var' structure (called by fbcon.c)
1848 *
1849 * This call looks only at yoffset and the FB_VMODE_YWRAP flag in `var'.
1850 * Since it's called by a kernel driver, no range checking is done.
1851 */
1852
1853static int virgefb_updatevar(int con, struct fb_info *info)
1854{
1855 DPRINTK("ENTER\n");
1856 return 0;
1857 DPRINTK("EXIT\n");
1858}
1859
1860/*
1861 * Blank the display.
1862 */
1863
1864static int virgefb_blank(int blank, struct fb_info *info)
1865{
1866 DPRINTK("ENTER\n");
1867 fbhw->blank(blank);
1868 DPRINTK("EXIT\n");
1869 return 0;
1870}
1871
1872
1873/*
1874 * Text console acceleration
1875 */
1876
1877#ifdef FBCON_HAS_CFB8
1878static void fbcon_virge8_bmove(struct display *p, int sy, int sx, int dy,
1879 int dx, int height, int width)
1880{
1881 sx *= 8; dx *= 8; width *= 8;
1882 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
1883 (u_short)(dy*fontheight(p)), (u_short)width,
1884 (u_short)(height*fontheight(p)), (u_short)p->next_line, 8);
1885}
1886
1887static void fbcon_virge8_clear(struct vc_data *conp, struct display *p, int sy,
1888 int sx, int height, int width)
1889{
1890 unsigned char bg;
1891
1892 sx *= 8; width *= 8;
1893 bg = attr_bgcol_ec(p,conp);
1894 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
1895 (u_short)width, (u_short)(height*fontheight(p)),
1896 (u_short)bg, (u_short)p->next_line, 8);
1897}
1898
1899static void fbcon_virge8_putc(struct vc_data *conp, struct display *p, int c, int yy,
1900 int xx)
1901{
1902 if (blit_maybe_busy)
1903 virgefb_wait_for_idle();
1904 fbcon_cfb8_putc(conp, p, c, yy, xx);
1905}
1906
1907static void fbcon_virge8_putcs(struct vc_data *conp, struct display *p,
1908 const unsigned short *s, int count, int yy, int xx)
1909{
1910 if (blit_maybe_busy)
1911 virgefb_wait_for_idle();
1912 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
1913}
1914
1915static void fbcon_virge8_revc(struct display *p, int xx, int yy)
1916{
1917 if (blit_maybe_busy)
1918 virgefb_wait_for_idle();
1919 fbcon_cfb8_revc(p, xx, yy);
1920}
1921
1922static void fbcon_virge8_clear_margins(struct vc_data *conp, struct display *p,
1923 int bottom_only)
1924{
1925 if (blit_maybe_busy)
1926 virgefb_wait_for_idle();
1927 fbcon_cfb8_clear_margins(conp, p, bottom_only);
1928}
1929
1930static struct display_switch fbcon_virge8 = {
1931 .setup = fbcon_cfb8_setup,
1932 .bmove = fbcon_virge8_bmove,
1933 .clear = fbcon_virge8_clear,
1934 .putc = fbcon_virge8_putc,
1935 .putcs = fbcon_virge8_putcs,
1936 .revc = fbcon_virge8_revc,
1937 .clear_margins = fbcon_virge8_clear_margins,
1938 .fontwidthmask = FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1939};
1940#endif
1941
1942#ifdef FBCON_HAS_CFB16
1943static void fbcon_virge16_bmove(struct display *p, int sy, int sx, int dy,
1944 int dx, int height, int width)
1945{
1946 sx *= 8; dx *= 8; width *= 8;
1947 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
1948 (u_short)(dy*fontheight(p)), (u_short)width,
1949 (u_short)(height*fontheight(p)), (u_short)p->next_line, 16);
1950}
1951
1952static void fbcon_virge16_clear(struct vc_data *conp, struct display *p, int sy,
1953 int sx, int height, int width)
1954{
1955 unsigned char bg;
1956
1957 sx *= 8; width *= 8;
1958 bg = attr_bgcol_ec(p,conp);
1959 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
1960 (u_short)width, (u_short)(height*fontheight(p)),
1961 (u_short)bg, (u_short)p->next_line, 16);
1962}
1963
1964static void fbcon_virge16_putc(struct vc_data *conp, struct display *p, int c, int yy,
1965 int xx)
1966{
1967 if (blit_maybe_busy)
1968 virgefb_wait_for_idle();
1969 fbcon_cfb16_putc(conp, p, c, yy, xx);
1970}
1971
1972static void fbcon_virge16_putcs(struct vc_data *conp, struct display *p,
1973 const unsigned short *s, int count, int yy, int xx)
1974{
1975 if (blit_maybe_busy)
1976 virgefb_wait_for_idle();
1977 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
1978}
1979
1980static void fbcon_virge16_revc(struct display *p, int xx, int yy)
1981{
1982 if (blit_maybe_busy)
1983 virgefb_wait_for_idle();
1984 fbcon_cfb16_revc(p, xx, yy);
1985}
1986
1987static void fbcon_virge16_clear_margins(struct vc_data *conp, struct display *p,
1988 int bottom_only)
1989{
1990 if (blit_maybe_busy)
1991 virgefb_wait_for_idle();
1992 fbcon_cfb16_clear_margins(conp, p, bottom_only);
1993}
1994
1995static struct display_switch fbcon_virge16 = {
1996 .setup = fbcon_cfb16_setup,
1997 .bmove = fbcon_virge16_bmove,
1998 .clear = fbcon_virge16_clear,
1999 .putc = fbcon_virge16_putc,
2000 .putcs = fbcon_virge16_putcs,
2001 .revc = fbcon_virge16_revc,
2002 .clear_margins = fbcon_virge16_clear_margins,
2003 .fontwidthmask = FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2004};
2005#endif
2006
2007#ifdef FBCON_HAS_CFB32
2008static void fbcon_virge32_bmove(struct display *p, int sy, int sx, int dy,
2009 int dx, int height, int width)
2010{
2011 sx *= 16; dx *= 16; width *= 16; /* doubled these values to do 32 bit blit */
2012 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
2013 (u_short)(dy*fontheight(p)), (u_short)width,
2014 (u_short)(height*fontheight(p)), (u_short)p->next_line, 16);
2015}
2016
2017static void fbcon_virge32_clear(struct vc_data *conp, struct display *p, int sy,
2018 int sx, int height, int width)
2019{
2020 unsigned char bg;
2021
2022 sx *= 16; width *= 16; /* doubled these values to do 32 bit blit */
2023 bg = attr_bgcol_ec(p,conp);
2024 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
2025 (u_short)width, (u_short)(height*fontheight(p)),
2026 (u_short)bg, (u_short)p->next_line, 16);
2027}
2028
2029static void fbcon_virge32_putc(struct vc_data *conp, struct display *p, int c, int yy,
2030 int xx)
2031{
2032 if (blit_maybe_busy)
2033 virgefb_wait_for_idle();
2034 fbcon_cfb32_putc(conp, p, c, yy, xx);
2035}
2036
2037static void fbcon_virge32_putcs(struct vc_data *conp, struct display *p,
2038 const unsigned short *s, int count, int yy, int xx)
2039{
2040 if (blit_maybe_busy)
2041 virgefb_wait_for_idle();
2042 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2043}
2044
2045static void fbcon_virge32_revc(struct display *p, int xx, int yy)
2046{
2047 if (blit_maybe_busy)
2048 virgefb_wait_for_idle();
2049 fbcon_cfb32_revc(p, xx, yy);
2050}
2051
2052static void fbcon_virge32_clear_margins(struct vc_data *conp, struct display *p,
2053 int bottom_only)
2054{
2055 if (blit_maybe_busy)
2056 virgefb_wait_for_idle();
2057 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2058}
2059
2060static struct display_switch fbcon_virge32 = {
2061 .setup = fbcon_cfb32_setup,
2062 .bmove = fbcon_virge32_bmove,
2063 .clear = fbcon_virge32_clear,
2064 .putc = fbcon_virge32_putc,
2065 .putcs = fbcon_virge32_putcs,
2066 .revc = fbcon_virge32_revc,
2067 .clear_margins = fbcon_virge32_clear_margins,
2068 .fontwidthmask = FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2069};
2070#endif
2071
2072#ifdef MODULE
2073MODULE_LICENSE("GPL");
2074
2075int init_module(void)
2076{
2077 return virgefb_init();
2078}
2079#endif /* MODULE */
2080
2081static int cv3d_has_4mb(void)
2082{
2083 /* cyberfb version didn't work, neither does this (not reliably)
2084 forced to return 4MB */
2085#if 0
2086 volatile unsigned long *t0, *t2;
2087#endif
2088 DPRINTK("ENTER\n");
2089#if 0
2090 /* write patterns in memory and test if they can be read */
2091 t0 = (volatile unsigned long *)v_ram;
2092 t2 = (volatile unsigned long *)(v_ram + 0x00200000);
2093 *t0 = 0x87654321;
2094 *t2 = 0x12345678;
2095
2096 if (*t0 != 0x87654321) {
2097 /* read of first location failed */
2098 DPRINTK("EXIT - 0MB !\n");
2099 return 0;
2100 }
2101
2102 if (*t2 == 0x87654321) {
2103 /* should read 0x12345678 if 4MB */
2104 DPRINTK("EXIT - 2MB(a) \n");
2105 return 0;
2106 }
2107
2108 if (*t2 != 0x12345678) {
2109 /* upper 2MB read back match failed */
2110 DPRINTK("EXIT - 2MB(b)\n");
2111 return 0;
2112 }
2113
2114 /* may have 4MB */
2115
2116 *t2 = 0xAAAAAAAA;
2117
2118 if(*t2 != 0xAAAAAAAA) {
2119 /* upper 2MB read back match failed */
2120 DPRINTK("EXIT - 2MB(c)\n");
2121 return 0;
2122 }
2123
2124 *t2 = 0x55555555;
2125
2126 if(*t2 != 0x55555555) {
2127 /* upper 2MB read back match failed */
2128 DPRINTK("EXIT - 2MB(d)\n");
2129 return 0;
2130 }
2131
2132#endif
2133 DPRINTK("EXIT - 4MB\n");
2134 return 1;
2135}
2136
2137
2138/*
2139 * Computes M, N, and R pll params for freq arg.
2140 * Returns 16 bits - hi 0MMMMMM lo 0RRNNNNN
2141 */
2142
2143#define REFCLOCK 14318000
2144
2145static unsigned short virgefb_compute_clock(unsigned long freq)
2146{
2147
2148 unsigned char m, n, r, rpwr;
2149 unsigned long diff, ftry, save = ~0UL;
2150 unsigned short mnr;
2151
2152 DPRINTK("ENTER\n");
2153
2154 for (r = 0, rpwr = 1 ; r < 4 ; r++, rpwr *= 2) {
2155 if ((135000000 <= (rpwr * freq)) && ((rpwr * freq) <= 270000000)) {
2156 for (n = 1 ; n < 32 ; n++) {
2157 m = ((freq * (n + 2) * rpwr)/REFCLOCK) - 2;
2158 if (m == 0 || m >127)
2159 break;
2160 ftry = ((REFCLOCK / (n + 2)) * (m + 2)) / rpwr;
2161 if (ftry > freq)
2162 diff = ftry - freq;
2163 else
2164 diff = freq - ftry;
2165 if (diff < save) {
2166 save = diff;
2167 mnr = (m << 8) | (r<<5) | (n & 0x7f);
2168 }
2169 }
2170 }
2171 }
2172 if (save == ~0UL)
2173 printk("Can't compute clock PLL values for %ld Hz clock\n", freq);
2174 DPRINTK("EXIT\n");
2175 return(mnr);
2176}
2177
2178static void virgefb_load_video_mode(struct fb_var_screeninfo *video_mode)
2179{
2180 unsigned char lace, dblscan, tmp;
2181 unsigned short mnr;
2182 unsigned short HT, HDE, HBS, HBW, HSS, HSW;
2183 unsigned short VT, VDE, VBS, VBW, VSS, VSW;
2184 unsigned short SCO;
2185 int cr11;
2186 int cr67;
2187 int hmul;
2188 int xres, xres_virtual, hfront, hsync, hback;
2189 int yres, vfront, vsync, vback;
2190 int bpp;
2191 int i;
2192 long freq;
2193
2194 DPRINTK("ENTER : %dx%d-%d\n",video_mode->xres, video_mode->yres,
2195 video_mode->bits_per_pixel);
2196
2197 bpp = video_mode->bits_per_pixel;
2198 xres = video_mode->xres;
2199 xres_virtual = video_mode->xres_virtual;
2200 hfront = video_mode->right_margin;
2201 hsync = video_mode->hsync_len;
2202 hback = video_mode->left_margin;
2203
2204 lace = 0;
2205 dblscan = 0;
2206
2207 if (video_mode->vmode & FB_VMODE_DOUBLE) {
2208 yres = video_mode->yres * 2;
2209 vfront = video_mode->lower_margin * 2;
2210 vsync = video_mode->vsync_len * 2;
2211 vback = video_mode->upper_margin * 2;
2212 dblscan = 1;
2213 } else if (video_mode->vmode & FB_VMODE_INTERLACED) {
2214 yres = (video_mode->yres + 1) / 2;
2215 vfront = (video_mode->lower_margin + 1) / 2;
2216 vsync = (video_mode->vsync_len + 1) / 2;
2217 vback = (video_mode->upper_margin + 1) / 2;
2218 lace = 1;
2219 } else {
2220 yres = video_mode->yres;
2221 vfront = video_mode->lower_margin;
2222 vsync = video_mode->vsync_len;
2223 vback = video_mode->upper_margin;
2224 }
2225
2226 switch (bpp) {
2227 case 8:
2228 video_mode->red.offset = 0;
2229 video_mode->green.offset = 0;
2230 video_mode->blue.offset = 0;
2231 video_mode->transp.offset = 0;
2232 video_mode->red.length = 8;
2233 video_mode->green.length = 8;
2234 video_mode->blue.length = 8;
2235 video_mode->transp.length = 0;
2236 hmul = 1;
2237 cr67 = 0x00;
2238 SCO = xres_virtual / 8;
2239 break;
2240 case 16:
2241 video_mode->red.offset = 11;
2242 video_mode->green.offset = 5;
2243 video_mode->blue.offset = 0;
2244 video_mode->transp.offset = 0;
2245 video_mode->red.length = 5;
2246 video_mode->green.length = 6;
2247 video_mode->blue.length = 5;
2248 video_mode->transp.length = 0;
2249 hmul = 2;
2250 cr67 = 0x50;
2251 SCO = xres_virtual / 4;
2252 break;
2253 case 32:
2254 video_mode->red.offset = 16;
2255 video_mode->green.offset = 8;
2256 video_mode->blue.offset = 0;
2257 video_mode->transp.offset = 24;
2258 video_mode->red.length = 8;
2259 video_mode->green.length = 8;
2260 video_mode->blue.length = 8;
2261 video_mode->transp.length = 8;
2262 hmul = 1;
2263 cr67 = 0xd0;
2264 SCO = xres_virtual / 2;
2265 break;
2266 }
2267
2268 HT = (((xres + hfront + hsync + hback) / 8) * hmul) - 5;
2269 HDE = ((xres / 8) * hmul) - 1;
2270 HBS = (xres / 8) * hmul;
2271 HSS = ((xres + hfront) / 8) * hmul;
2272 HSW = (hsync / 8) * hmul;
2273 HBW = (((hfront + hsync + hback) / 8) * hmul) - 2;
2274
2275 VT = yres + vfront + vsync + vback - 2;
2276 VDE = yres - 1;
2277 VBS = yres - 1;
2278 VSS = yres + vfront;
2279 VSW = vsync;
2280 VBW = vfront + vsync + vback - 2;
2281
2282#ifdef VIRGEFBDEBUG
2283 DPRINTK("HDE : 0x%4.4x, %4.4d\n", HDE, HDE);
2284 DPRINTK("HBS : 0x%4.4x, %4.4d\n", HBS, HBS);
2285 DPRINTK("HSS : 0x%4.4x, %4.4d\n", HSS, HSS);
2286 DPRINTK("HSW : 0x%4.4x, %4.4d\n", HSW, HSW);
2287 DPRINTK("HBW : 0x%4.4x, %4.4d\n", HBW, HBW);
2288 DPRINTK("HSS + HSW : 0x%4.4x, %4.4d\n", HSS+HSW, HSS+HSW);
2289 DPRINTK("HBS + HBW : 0x%4.4x, %4.4d\n", HBS+HBW, HBS+HBW);
2290 DPRINTK("HT : 0x%4.4x, %4.4d\n", HT, HT);
2291 DPRINTK("VDE : 0x%4.4x, %4.4d\n", VDE, VDE);
2292 DPRINTK("VBS : 0x%4.4x, %4.4d\n", VBS, VBS);
2293 DPRINTK("VSS : 0x%4.4x, %4.4d\n", VSS, VSS);
2294 DPRINTK("VSW : 0x%4.4x, %4.4d\n", VSW, VSW);
2295 DPRINTK("VBW : 0x%4.4x, %4.4d\n", VBW, VBW);
2296 DPRINTK("VT : 0x%4.4x, %4.4d\n", VT, VT);
2297#endif
2298
2299/* turn gfx off, don't mess up the display */
2300
2301 gfx_on_off(1);
2302
2303/* H and V sync polarity */
2304
2305 tmp = rb_mmio(GREG_MISC_OUTPUT_R) & 0x2f; /* colour, ram enable, clk sr12/s13 sel */
2306 if (!(video_mode->sync & FB_SYNC_HOR_HIGH_ACT))
2307 tmp |= 0x40; /* neg H sync polarity */
2308 if (!(video_mode->sync & FB_SYNC_VERT_HIGH_ACT))
2309 tmp |= 0x80; /* neg V sync polarity */
2310 tmp |= 0x0c; /* clk from sr12/sr13 */
2311 wb_mmio(GREG_MISC_OUTPUT_W, tmp);
2312
2313/* clocks */
2314
2315 wseq(SEQ_ID_BUS_REQ_CNTL, 0xc0); /* 2 clk mem wr and /RAS1 */
2316 wseq(SEQ_ID_CLKSYN_CNTL_2, 0x80); /* b7 is 2 mem clk wr */
2317 mnr = virgefb_compute_clock(MEMCLOCK);
2318 DPRINTK("mem clock %d, m %d, n %d, r %d.\n", MEMCLOCK, ((mnr>>8)&0x7f), (mnr&0x1f), ((mnr >> 5)&0x03));
2319 wseq(SEQ_ID_MCLK_LO, (mnr & 0x7f));
2320 wseq(SEQ_ID_MCLK_HI, ((mnr & 0x7f00) >> 8));
2321 freq = (1000000000 / video_mode->pixclock) * 1000; /* pixclock is in ps ... convert to Hz */
2322 mnr = virgefb_compute_clock(freq);
2323 DPRINTK("dot clock %ld, m %d, n %d, r %d.\n", freq, ((mnr>>8)&0x7f), (mnr&0x1f), ((mnr>>5)&0x03));
2324 wseq(SEQ_ID_DCLK_LO, (mnr & 0x7f));
2325 wseq(SEQ_ID_DCLK_HI, ((mnr & 0x7f00) >> 8));
2326 wseq(SEQ_ID_CLKSYN_CNTL_2, 0xa0);
2327 wseq(SEQ_ID_CLKSYN_CNTL_2, 0x80);
2328 udelay(100);
2329
2330/* load display parameters into board */
2331
2332 /* not sure about sync and blanking extensions bits in cr5d and cr5 */
2333
2334 wcrt(CRT_ID_EXT_HOR_OVF, /* 0x5d */
2335 ((HT & 0x100) ? 0x01 : 0x00) |
2336 ((HDE & 0x100) ? 0x02 : 0x00) |
2337 ((HBS & 0x100) ? 0x04 : 0x00) |
2338 /* (((HBS + HBW) & 0x40) ? 0x08 : 0x00) | */
2339 ((HSS & 0x100) ? 0x10 : 0x00) |
2340 /* (((HSS + HSW) & 0x20) ? 0x20 : 0x00) | */
2341 ((HSW >= 0x20) ? 0x20 : 0x00) |
2342 (((HT-5) & 0x100) ? 0x40 : 0x00));
2343
2344 wcrt(CRT_ID_EXT_VER_OVF, /* 0x5e */
2345 ((VT & 0x400) ? 0x01 : 0x00) |
2346 ((VDE & 0x400) ? 0x02 : 0x00) |
2347 ((VBS & 0x400) ? 0x04 : 0x00) |
2348 ((VSS & 0x400) ? 0x10 : 0x00) |
2349 0x40); /* line compare */
2350
2351 wcrt(CRT_ID_START_VER_RETR, VSS);
2352 cr11 = rcrt(CRT_ID_END_VER_RETR) | 0x20; /* vert interrupt flag */
2353 wcrt(CRT_ID_END_VER_RETR, ((cr11 & 0x20) | ((VSS + VSW) & 0x0f))); /* keeps vert irq enable state, also has unlock bit cr0 to 7 */
2354 wcrt(CRT_ID_VER_DISP_ENA_END, VDE);
2355 wcrt(CRT_ID_START_VER_BLANK, VBS);
2356 wcrt(CRT_ID_END_VER_BLANK, VBS + VBW); /* might be +/- 1 out */
2357 wcrt(CRT_ID_HOR_TOTAL, HT);
2358 wcrt(CRT_ID_DISPLAY_FIFO, HT - 5);
2359 wcrt(CRT_ID_BACKWAD_COMP_3, 0x10); /* enable display fifo */
2360 wcrt(CRT_ID_HOR_DISP_ENA_END, HDE);
2361 wcrt(CRT_ID_START_HOR_BLANK , HBS);
2362 wcrt(CRT_ID_END_HOR_BLANK, (HBS + HBW) & 0x1f);
2363 wcrt(CRT_ID_START_HOR_RETR, HSS);
2364 wcrt(CRT_ID_END_HOR_RETR, /* cr5 */
2365 ((HSS + HSW) & 0x1f) |
2366 (((HBS + HBW) & 0x20) ? 0x80 : 0x00));
2367 wcrt(CRT_ID_VER_TOTAL, VT);
2368 wcrt(CRT_ID_OVERFLOW,
2369 ((VT & 0x100) ? 0x01 : 0x00) |
2370 ((VDE & 0x100) ? 0x02 : 0x00) |
2371 ((VSS & 0x100) ? 0x04 : 0x00) |
2372 ((VBS & 0x100) ? 0x08 : 0x00) |
2373 0x10 |
2374 ((VT & 0x200) ? 0x20 : 0x00) |
2375 ((VDE & 0x200) ? 0x40 : 0x00) |
2376 ((VSS & 0x200) ? 0x80 : 0x00));
2377 wcrt(CRT_ID_MAX_SCAN_LINE,
2378 (dblscan ? 0x80 : 0x00) |
2379 0x40 |
2380 ((VBS & 0x200) ? 0x20 : 0x00));
2381 wcrt(CRT_ID_LINE_COMPARE, 0xff);
2382 wcrt(CRT_ID_LACE_RETR_START, HT / 2); /* (HT-5)/2 ? */
2383 wcrt(CRT_ID_LACE_CONTROL, (lace ? 0x20 : 0x00));
2384
2385 wcrt(CRT_ID_SCREEN_OFFSET, SCO);
2386 wcrt(CRT_ID_EXT_SYS_CNTL_2, (SCO >> 4) & 0x30 );
2387
2388 /* wait for vert sync before cr67 update */
2389
2390 for (i=0; i < 10000; i++) {
2391 udelay(10);
2392 mb();
2393 if (rb_mmio(GREG_INPUT_STATUS1_R) & 0x08)
2394 break;
2395 }
2396
2397 wl_mmio(0x8200, 0x0000c000); /* fifo control (0x00110400 ?) */
2398 wcrt(CRT_ID_EXT_MISC_CNTL_2, cr67);
2399
2400/* enable video */
2401
2402 tmp = rb_mmio(ACT_ADDRESS_RESET);
2403 wb_mmio(ACT_ADDRESS_W, ((bpp == 8) ? 0x20 : 0x00)); /* set b5, ENB PLT in attr idx reg) */
2404 tmp = rb_mmio(ACT_ADDRESS_RESET);
2405
2406/* turn gfx on again */
2407
2408 gfx_on_off(0);
2409
2410/* pass-through */
2411
2412 SetVSwitch(1); /* cv3d */
2413
2414 DUMP;
2415 DPRINTK("EXIT\n");
2416}
2417
2418static inline void gfx_on_off(int toggle)
2419{
2420 unsigned char tmp;
2421
2422 DPRINTK("ENTER gfx %s\n", (toggle ? "off" : "on"));
2423
2424 toggle = (toggle & 0x01) << 5;
2425 tmp = rseq(SEQ_ID_CLOCKING_MODE) & (~(0x01 << 5));
2426 wseq(SEQ_ID_CLOCKING_MODE, tmp | toggle);
2427
2428 DPRINTK("EXIT\n");
2429}
2430
2431#if defined (VIRGEFBDUMP)
2432
2433/*
2434 * Dump board registers
2435 */
2436
2437static void cv64_dump(void)
2438{
2439 int i;
2440 u8 c, b;
2441 u16 w;
2442 u32 l;
2443
2444 /* crt, seq, gfx and atr regs */
2445
2446 SelectMMIO;
2447
2448 printk("\n");
2449 for (i = 0; i <= 0x6f; i++) {
2450 wb_mmio(CRT_ADDRESS, i);
2451 printk("crt idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(CRT_ADDRESS_R));
2452 }
2453 for (i = 0; i <= 0x1c; i++) {
2454 wb_mmio(SEQ_ADDRESS, i);
2455 printk("seq idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(SEQ_ADDRESS_R));
2456 }
2457 for (i = 0; i <= 8; i++) {
2458 wb_mmio(GCT_ADDRESS, i);
2459 printk("gfx idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(GCT_ADDRESS_R));
2460 }
2461 for (i = 0; i <= 0x14; i++) {
2462 c = rb_mmio(ACT_ADDRESS_RESET);
2463 wb_mmio(ACT_ADDRESS_W, i);
2464 printk("atr idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(ACT_ADDRESS_R));
2465 }
2466
2467 /* re-enable video access to palette */
2468
2469 c = rb_mmio(ACT_ADDRESS_RESET);
2470 udelay(10);
2471 wb_mmio(ACT_ADDRESS_W, 0x20);
2472 c = rb_mmio(ACT_ADDRESS_RESET);
2473 udelay(10);
2474
2475 /* general regs */
2476
2477 printk("0x3cc(w 0x3c2) : 0x%2.2x\n", rb_mmio(0x3cc)); /* GREG_MISC_OUTPUT READ */
2478 printk("0x3c2(-------) : 0x%2.2x\n", rb_mmio(0x3c2)); /* GREG_INPUT_STATUS 0 READ */
2479 printk("0x3c3(w 0x3c3) : 0x%2.2x\n", rb_vgaio(0x3c3)); /* GREG_VIDEO_SUBS_ENABLE */
2480 printk("0x3ca(w 0x3da) : 0x%2.2x\n", rb_vgaio(0x3ca)); /* GREG_FEATURE_CONTROL read */
2481 printk("0x3da(-------) : 0x%2.2x\n", rb_mmio(0x3da)); /* GREG_INPUT_STATUS 1 READ */
2482
2483 /* engine regs */
2484
2485 for (i = 0x8180; i <= 0x8200; i = i + 4)
2486 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2487
2488 i = 0x8504;
2489 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2490 i = 0x850c;
2491 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2492 for (i = 0xa4d4; i <= 0xa50c; i = i + 4)
2493 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2494
2495 /* PCI regs */
2496
2497 SelectCFG;
2498
2499 for (c = 0; c < 0x08; c = c + 2) {
2500 w = (*((u16 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 2)));
2501 printk("pci 0x%2.2x : 0x%4.4x\n", c, w);
2502 }
2503 c = 8;
2504 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2505 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2506 c = 0x0d;
2507 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2508 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2509 c = 0x10;
2510 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2511 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2512 c = 0x30;
2513 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2514 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2515 c = 0x3c;
2516 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2517 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2518 c = 0x3d;
2519 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2520 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2521 c = 0x3e;
2522 w = (*((u16 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 2)));
2523 printk("pci 0x%2.2x : 0x%4.4x\n", c, w);
2524 SelectMMIO;
2525}
2526#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 01:20:04 -0500