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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-05-22 19:30:48 -0400
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-08-05 08:46:51 -0400
commitf18e3e0ce0dacca497e3f1547095b3f9b111b0f7 (patch)
treeed3a34329b2f16e428a3c6f82d35527f7e0e0f8e /drivers/video/via
parentd60defb7b2c05b5c4b187171c09b714b0a00efe9 (diff)
viafb: kill viafb_load_crtc_timing
This patch replaces calls to viafb_load_crtc_timing with the code. This should make it easier to fix the oddity that in the modetable the blank and sync end entries contain the length and we need to add the start values to get those to be written to the hardware. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers/video/via')
-rw-r--r--drivers/video/via/hw.c30
-rw-r--r--drivers/video/via/lcd.c41
-rw-r--r--drivers/video/via/lcd.h2
3 files changed, 27 insertions, 46 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 372ce4f071c2..52d41f011d85 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1467,20 +1467,6 @@ void viafb_set_vclock(u32 clk, int set_iga)
1467 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ 1467 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1468} 1468}
1469 1469
1470void viafb_load_crtc_timing(struct display_timing device_timing,
1471 int set_iga)
1472{
1473 device_timing.hor_blank_end += device_timing.hor_blank_start;
1474 device_timing.hor_sync_end += device_timing.hor_sync_start;
1475 device_timing.ver_blank_end += device_timing.ver_blank_start;
1476 device_timing.ver_sync_end += device_timing.ver_sync_start;
1477
1478 if (set_iga == IGA1)
1479 via_set_primary_timing(&device_timing);
1480 else if (set_iga == IGA2)
1481 via_set_secondary_timing(&device_timing);
1482}
1483
1484void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 1470void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1485 struct VideoModeTable *video_mode, int bpp_byte, int set_iga) 1471 struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1486{ 1472{
@@ -1515,6 +1501,10 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1515 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16; 1501 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1516 } 1502 }
1517 1503
1504 crt_reg.hor_blank_end += crt_reg.hor_blank_start;
1505 crt_reg.hor_sync_end += crt_reg.hor_sync_start;
1506 crt_reg.ver_blank_end += crt_reg.ver_blank_start;
1507 crt_reg.ver_sync_end += crt_reg.ver_sync_start;
1518 h_addr = crt_reg.hor_addr; 1508 h_addr = crt_reg.hor_addr;
1519 v_addr = crt_reg.ver_addr; 1509 v_addr = crt_reg.ver_addr;
1520 if (set_iga == IGA1) { 1510 if (set_iga == IGA1) {
@@ -1522,14 +1512,10 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1522 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); 1512 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1523 } 1513 }
1524 1514
1525 switch (set_iga) { 1515 if (set_iga == IGA1)
1526 case IGA1: 1516 via_set_primary_timing(&crt_reg);
1527 viafb_load_crtc_timing(crt_reg, IGA1); 1517 else if (set_iga == IGA2)
1528 break; 1518 via_set_secondary_timing(&crt_reg);
1529 case IGA2:
1530 viafb_load_crtc_timing(crt_reg, IGA2);
1531 break;
1532 }
1533 1519
1534 viafb_lock_crt(); 1520 viafb_lock_crt();
1535 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); 1521 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index 6e06981d638b..0a38e4de9979 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -559,7 +559,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
559 int panel_hres = plvds_setting_info->lcd_panel_hres; 559 int panel_hres = plvds_setting_info->lcd_panel_hres;
560 int panel_vres = plvds_setting_info->lcd_panel_vres; 560 int panel_vres = plvds_setting_info->lcd_panel_vres;
561 u32 clock; 561 u32 clock;
562 struct display_timing mode_crt_reg, panel_crt_reg; 562 struct display_timing mode_crt_reg, panel_crt_reg, timing;
563 struct crt_mode_table *panel_crt_table = NULL; 563 struct crt_mode_table *panel_crt_table = NULL;
564 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, 564 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
565 panel_vres); 565 panel_vres);
@@ -576,31 +576,28 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
576 clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total 576 clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
577 * panel_crt_table->refresh_rate; 577 * panel_crt_table->refresh_rate;
578 plvds_setting_info->vclk = clock; 578 plvds_setting_info->vclk = clock;
579 if (set_iga == IGA1) { 579
580 /* IGA1 doesn't have LCD scaling, so set it as centering. */ 580 if (set_iga == IGA2 && (set_hres < panel_hres || set_vres < panel_vres)
581 viafb_load_crtc_timing(lcd_centering_timging 581 && plvds_setting_info->display_method == LCD_EXPANDSION) {
582 (mode_crt_reg, panel_crt_reg), IGA1); 582 timing = panel_crt_reg;
583 load_lcd_scaling(set_hres, set_vres, panel_hres, panel_vres);
583 } else { 584 } else {
584 /* Expansion */ 585 timing = lcd_centering_timging(mode_crt_reg, panel_crt_reg);
585 if (plvds_setting_info->display_method == LCD_EXPANDSION 586 if (set_iga == IGA2)
586 && (set_hres < panel_hres || set_vres < panel_vres)) { 587 /* disable scaling */
587 /* expansion timing IGA2 loaded panel set timing*/ 588 via_write_reg_mask(VIACR, 0x79, 0x00,
588 viafb_load_crtc_timing(panel_crt_reg, IGA2);
589 DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
590 load_lcd_scaling(set_hres, set_vres, panel_hres,
591 panel_vres);
592 DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
593 } else { /* Centering */
594 /* centering timing IGA2 always loaded panel
595 and mode releative timing */
596 viafb_load_crtc_timing(lcd_centering_timging
597 (mode_crt_reg, panel_crt_reg), IGA2);
598 viafb_write_reg_mask(CR79, VIACR, 0x00,
599 BIT0 + BIT1 + BIT2); 589 BIT0 + BIT1 + BIT2);
600 /* LCD scaling disabled */
601 }
602 } 590 }
603 591
592 timing.hor_blank_end += timing.hor_blank_start;
593 timing.hor_sync_end += timing.hor_sync_start;
594 timing.ver_blank_end += timing.ver_blank_start;
595 timing.ver_sync_end += timing.ver_sync_start;
596 if (set_iga == IGA1)
597 via_set_primary_timing(&timing);
598 else if (set_iga == IGA2)
599 via_set_secondary_timing(&timing);
600
604 /* Fetch count for IGA2 only */ 601 /* Fetch count for IGA2 only */
605 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga); 602 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
606 603
diff --git a/drivers/video/via/lcd.h b/drivers/video/via/lcd.h
index 75f60a655b0e..3b9e5397aa69 100644
--- a/drivers/video/via/lcd.h
+++ b/drivers/video/via/lcd.h
@@ -85,7 +85,5 @@ void viafb_init_lvds_output_interface(struct lvds_chip_information
85 struct lvds_setting_information 85 struct lvds_setting_information
86 *plvds_setting_info); 86 *plvds_setting_info);
87bool viafb_lcd_get_mobile_state(bool *mobile); 87bool viafb_lcd_get_mobile_state(bool *mobile);
88void viafb_load_crtc_timing(struct display_timing device_timing,
89 int set_iga);
90 88
91#endif /* __LCD_H__ */ 89#endif /* __LCD_H__ */