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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-03-23 17:04:01 -0400
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-03-23 17:11:46 -0400
commit6c1093af5833d4c69634711d9453287ab9e0cb77 (patch)
treeef838146402b42ecdf9b2e2e5579b900bdce6387 /drivers/video/via
parent0f77d4a052aec7392dbfd3d8942a519d013d66d9 (diff)
viafb: add clock source selection and PLL power management support
This patch adds some support for clock source selection as well as PLL power management. The code is unused at the moment but was successfully tested as far as possible. The implementation is according to the documentation for VX700, VX800, VX855, VX900. Probably the source selection works like this starting with K800 and the power managemennt at least since VX700. (guessed based on the initialization in viamode.c) Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers/video/via')
-rw-r--r--drivers/video/via/hw.c88
1 files changed, 88 insertions, 0 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index bd28e13f83d4..b38d3b40de95 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1409,6 +1409,42 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1409 1409
1410} 1410}
1411 1411
1412static void set_primary_pll_state(u8 state)
1413{
1414 u8 value;
1415
1416 switch (state) {
1417 case VIA_STATE_ON:
1418 value = 0x20;
1419 break;
1420 case VIA_STATE_OFF:
1421 value = 0x00;
1422 break;
1423 default:
1424 return;
1425 }
1426
1427 via_write_reg_mask(VIASR, 0x2D, value, 0x30);
1428}
1429
1430static void set_secondary_pll_state(u8 state)
1431{
1432 u8 value;
1433
1434 switch (state) {
1435 case VIA_STATE_ON:
1436 value = 0x08;
1437 break;
1438 case VIA_STATE_OFF:
1439 value = 0x00;
1440 break;
1441 default:
1442 return;
1443 }
1444
1445 via_write_reg_mask(VIASR, 0x2D, value, 0x08);
1446}
1447
1412static u32 cle266_encode_pll(struct pll_config pll) 1448static u32 cle266_encode_pll(struct pll_config pll)
1413{ 1449{
1414 return (pll.multiplier << 8) 1450 return (pll.multiplier << 8)
@@ -1494,6 +1530,58 @@ static void vx855_set_secondary_pll(struct pll_config config)
1494 k800_set_secondary_pll_encoded(vx855_encode_pll(config)); 1530 k800_set_secondary_pll_encoded(vx855_encode_pll(config));
1495} 1531}
1496 1532
1533enum via_clksrc {
1534 VIA_CLKSRC_X1 = 0,
1535 VIA_CLKSRC_TVX1,
1536 VIA_CLKSRC_TVPLL,
1537 VIA_CLKSRC_DVP1TVCLKR,
1538 VIA_CLKSRC_CAP0,
1539 VIA_CLKSRC_CAP1,
1540};
1541
1542static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
1543{
1544 u8 data = 0;
1545
1546 switch (source) {
1547 case VIA_CLKSRC_X1:
1548 data = 0x00;
1549 break;
1550 case VIA_CLKSRC_TVX1:
1551 data = 0x02;
1552 break;
1553 case VIA_CLKSRC_TVPLL:
1554 data = 0x04; /* 0x06 should be the same */
1555 break;
1556 case VIA_CLKSRC_DVP1TVCLKR:
1557 data = 0x0A;
1558 break;
1559 case VIA_CLKSRC_CAP0:
1560 data = 0xC;
1561 break;
1562 case VIA_CLKSRC_CAP1:
1563 data = 0x0E;
1564 break;
1565 }
1566
1567 if (!use_pll)
1568 data |= 1;
1569
1570 return data;
1571}
1572
1573static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
1574{
1575 u8 data = set_clock_source_common(source, use_pll) << 4;
1576 via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
1577}
1578
1579static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
1580{
1581 u8 data = set_clock_source_common(source, use_pll);
1582 via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
1583}
1584
1497static inline u32 get_pll_internal_frequency(u32 ref_freq, 1585static inline u32 get_pll_internal_frequency(u32 ref_freq,
1498 struct pll_config pll) 1586 struct pll_config pll)
1499{ 1587{