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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-03-12 16:54:56 -0500
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-03-12 16:54:56 -0500
commit2563afa9ec6970f3545906382cc986ee012f60ec (patch)
tree861097eb35da2dfda966b70f300eeaf8311fae37 /drivers/video/via
parentbf5ea02d9058a97a0bc2da9ca04ae4b34989407a (diff)
parente4fcaeff4fcb56779f22f2f11e50ed2a69e650a3 (diff)
Merge branch 'viafb-pll' into viafb-next
Diffstat (limited to 'drivers/video/via')
-rw-r--r--drivers/video/via/dvi.c4
-rw-r--r--drivers/video/via/hw.c740
-rw-r--r--drivers/video/via/hw.h2
-rw-r--r--drivers/video/via/lcd.c8
-rw-r--r--drivers/video/via/share.h141
-rw-r--r--drivers/video/via/viamode.c322
-rw-r--r--drivers/video/via/viamode.h9
7 files changed, 479 insertions, 747 deletions
diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c
index 84e21b39dd0b..41ca198b5098 100644
--- a/drivers/video/via/dvi.c
+++ b/drivers/video/via/dvi.c
@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
195 struct crt_mode_table *pDviTiming; 195 struct crt_mode_table *pDviTiming;
196 unsigned long desirePixelClock, maxPixelClock; 196 unsigned long desirePixelClock, maxPixelClock;
197 pDviTiming = mode->crtc; 197 pDviTiming = mode->crtc;
198 desirePixelClock = pDviTiming->clk / 1000000; 198 desirePixelClock = pDviTiming->refresh_rate
199 * pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
200 / 1000000;
199 maxPixelClock = (unsigned long)viaparinfo-> 201 maxPixelClock = (unsigned long)viaparinfo->
200 tmds_setting_info->max_pixel_clock; 202 tmds_setting_info->max_pixel_clock;
201 203
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 6cb3b5626f0d..5728fd76bc11 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -22,342 +22,272 @@
22#include <linux/via-core.h> 22#include <linux/via-core.h>
23#include "global.h" 23#include "global.h"
24 24
25static struct pll_map pll_value[] = { 25static struct pll_config cle266_pll_config[] = {
26 {25175000, 26 {19, 4, 0},
27 {99, 7, 3}, 27 {26, 5, 0},
28 {85, 3, 4}, /* ignoring bit difference: 0x00008000 */ 28 {28, 5, 0},
29 {141, 5, 4}, 29 {31, 5, 0},
30 {141, 5, 4} }, 30 {33, 5, 0},
31 {29581000, 31 {55, 5, 0},
32 {33, 4, 2}, 32 {102, 5, 0},
33 {66, 2, 4}, /* ignoring bit difference: 0x00808000 */ 33 {53, 6, 0},
34 {166, 5, 4}, /* ignoring bit difference: 0x00008000 */ 34 {92, 6, 0},
35 {165, 5, 4} }, 35 {98, 6, 0},
36 {26880000, 36 {112, 6, 0},
37 {15, 4, 1}, 37 {41, 7, 0},
38 {30, 2, 3}, /* ignoring bit difference: 0x00808000 */ 38 {60, 7, 0},
39 {150, 5, 4}, 39 {99, 7, 0},
40 {150, 5, 4} }, 40 {100, 7, 0},
41 {31500000, 41 {83, 8, 0},
42 {53, 3, 3}, /* ignoring bit difference: 0x00008000 */ 42 {86, 8, 0},
43 {141, 4, 4}, /* ignoring bit difference: 0x00008000 */ 43 {108, 8, 0},
44 {176, 5, 4}, 44 {87, 9, 0},
45 {176, 5, 4} }, 45 {118, 9, 0},
46 {31728000, 46 {95, 12, 0},
47 {31, 7, 1}, 47 {115, 12, 0},
48 {177, 5, 4}, /* ignoring bit difference: 0x00008000 */ 48 {108, 13, 0},
49 {177, 5, 4}, 49 {83, 17, 0},
50 {142, 4, 4} }, 50 {67, 20, 0},
51 {32688000, 51 {86, 20, 0},
52 {73, 4, 3}, 52 {98, 20, 0},
53 {146, 4, 4}, /* ignoring bit difference: 0x00008000 */ 53 {121, 24, 0},
54 {183, 5, 4}, 54 {99, 29, 0},
55 {146, 4, 4} }, 55 {33, 3, 1},
56 {36000000, 56 {15, 4, 1},
57 {101, 5, 3}, /* ignoring bit difference: 0x00008000 */ 57 {23, 4, 1},
58 {161, 4, 4}, /* ignoring bit difference: 0x00008000 */ 58 {37, 5, 1},
59 {202, 5, 4}, 59 {83, 5, 1},
60 {161, 4, 4} }, 60 {85, 5, 1},
61 {40000000, 61 {94, 5, 1},
62 {89, 4, 3}, 62 {103, 5, 1},
63 {89, 4, 3}, /* ignoring bit difference: 0x00008000 */ 63 {109, 5, 1},
64 {112, 5, 3}, 64 {113, 5, 1},
65 {112, 5, 3} }, 65 {121, 5, 1},
66 {41291000, 66 {82, 6, 1},
67 {23, 4, 1}, 67 {31, 7, 1},
68 {69, 3, 3}, /* ignoring bit difference: 0x00008000 */ 68 {55, 7, 1},
69 {115, 5, 3}, 69 {84, 7, 1},
70 {115, 5, 3} }, 70 {83, 8, 1},
71 {43163000, 71 {76, 9, 1},
72 {121, 5, 3}, 72 {127, 9, 1},
73 {121, 5, 3}, /* ignoring bit difference: 0x00008000 */ 73 {33, 4, 2},
74 {121, 5, 3}, 74 {75, 4, 2},
75 {121, 5, 3} }, 75 {119, 4, 2},
76 {45250000, 76 {121, 4, 2},
77 {127, 5, 3}, 77 {91, 5, 2},
78 {127, 5, 3}, /* ignoring bit difference: 0x00808000 */ 78 {118, 5, 2},
79 {127, 5, 3}, 79 {83, 6, 2},
80 {127, 5, 3} }, 80 {109, 6, 2},
81 {46000000, 81 {90, 7, 2},
82 {90, 7, 2}, 82 {93, 2, 3},
83 {103, 4, 3}, /* ignoring bit difference: 0x00008000 */ 83 {53, 3, 3},
84 {129, 5, 3}, 84 {73, 4, 3},
85 {103, 4, 3} }, 85 {89, 4, 3},
86 {46996000, 86 {105, 4, 3},
87 {105, 4, 3}, /* ignoring bit difference: 0x00008000 */ 87 {117, 4, 3},
88 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */ 88 {101, 5, 3},
89 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */ 89 {121, 5, 3},
90 {105, 4, 3} }, 90 {127, 5, 3},
91 {48000000, 91 {99, 7, 3}
92 {67, 20, 0}, 92};
93 {134, 5, 3}, /* ignoring bit difference: 0x00808000 */ 93
94 {134, 5, 3}, 94static struct pll_config k800_pll_config[] = {
95 {134, 5, 3} }, 95 {22, 2, 0},
96 {48875000, 96 {28, 3, 0},
97 {99, 29, 0}, 97 {81, 3, 1},
98 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */ 98 {85, 3, 1},
99 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */ 99 {98, 3, 1},
100 {137, 5, 3} }, 100 {112, 3, 1},
101 {49500000, 101 {86, 4, 1},
102 {83, 6, 2}, 102 {166, 4, 1},
103 {83, 3, 3}, /* ignoring bit difference: 0x00008000 */ 103 {109, 5, 1},
104 {138, 5, 3}, 104 {113, 5, 1},
105 {83, 3, 3} }, 105 {121, 5, 1},
106 {52406000, 106 {131, 5, 1},
107 {117, 4, 3}, 107 {143, 5, 1},
108 {117, 4, 3}, /* ignoring bit difference: 0x00008000 */ 108 {153, 5, 1},
109 {117, 4, 3}, 109 {66, 3, 2},
110 {88, 3, 3} }, 110 {68, 3, 2},
111 {52977000, 111 {95, 3, 2},
112 {37, 5, 1}, 112 {106, 3, 2},
113 {148, 5, 3}, /* ignoring bit difference: 0x00808000 */ 113 {116, 3, 2},
114 {148, 5, 3}, 114 {93, 4, 2},
115 {148, 5, 3} }, 115 {119, 4, 2},
116 {56250000, 116 {121, 4, 2},
117 {55, 7, 1}, /* ignoring bit difference: 0x00008000 */ 117 {133, 4, 2},
118 {126, 4, 3}, /* ignoring bit difference: 0x00008000 */ 118 {137, 4, 2},
119 {157, 5, 3}, 119 {117, 5, 2},
120 {157, 5, 3} }, 120 {118, 5, 2},
121 {57275000, 121 {120, 5, 2},
122 {0, 0, 0}, 122 {124, 5, 2},
123 {2, 2, 0}, 123 {132, 5, 2},
124 {2, 2, 0}, 124 {137, 5, 2},
125 {157, 5, 3} }, /* ignoring bit difference: 0x00808000 */ 125 {141, 5, 2},
126 {60466000, 126 {166, 5, 2},
127 {76, 9, 1}, 127 {170, 5, 2},
128 {169, 5, 3}, /* ignoring bit difference: 0x00808000 */ 128 {191, 5, 2},
129 {169, 5, 3}, /* FIXED: old = {72, 2, 3} */ 129 {206, 5, 2},
130 {169, 5, 3} }, 130 {208, 5, 2},
131 {61500000, 131 {30, 2, 3},
132 {86, 20, 0}, 132 {69, 3, 3},
133 {172, 5, 3}, /* ignoring bit difference: 0x00808000 */ 133 {82, 3, 3},
134 {172, 5, 3}, 134 {83, 3, 3},
135 {172, 5, 3} }, 135 {109, 3, 3},
136 {65000000, 136 {114, 3, 3},
137 {109, 6, 2}, /* ignoring bit difference: 0x00008000 */ 137 {125, 3, 3},
138 {109, 3, 3}, /* ignoring bit difference: 0x00008000 */ 138 {89, 4, 3},
139 {109, 3, 3}, 139 {103, 4, 3},
140 {109, 3, 3} }, 140 {117, 4, 3},
141 {65178000, 141 {126, 4, 3},
142 {91, 5, 2}, 142 {150, 4, 3},
143 {182, 5, 3}, /* ignoring bit difference: 0x00808000 */ 143 {161, 4, 3},
144 {109, 3, 3}, 144 {121, 5, 3},
145 {182, 5, 3} }, 145 {127, 5, 3},
146 {66750000, 146 {131, 5, 3},
147 {75, 4, 2}, 147 {134, 5, 3},
148 {150, 4, 3}, /* ignoring bit difference: 0x00808000 */ 148 {148, 5, 3},
149 {150, 4, 3}, 149 {169, 5, 3},
150 {112, 3, 3} }, 150 {172, 5, 3},
151 {68179000, 151 {182, 5, 3},
152 {19, 4, 0}, 152 {195, 5, 3},
153 {114, 3, 3}, /* ignoring bit difference: 0x00008000 */ 153 {196, 5, 3},
154 {190, 5, 3}, 154 {208, 5, 3},
155 {191, 5, 3} }, 155 {66, 2, 4},
156 {69924000, 156 {85, 3, 4},
157 {83, 17, 0}, 157 {141, 4, 4},
158 {195, 5, 3}, /* ignoring bit difference: 0x00808000 */ 158 {146, 4, 4},
159 {195, 5, 3}, 159 {161, 4, 4},
160 {195, 5, 3} }, 160 {177, 5, 4}
161 {70159000, 161};
162 {98, 20, 0}, 162
163 {196, 5, 3}, /* ignoring bit difference: 0x00808000 */ 163static struct pll_config cx700_pll_config[] = {
164 {196, 5, 3}, 164 {98, 3, 1},
165 {195, 5, 3} }, 165 {86, 4, 1},
166 {72000000, 166 {109, 5, 1},
167 {121, 24, 0}, 167 {110, 5, 1},
168 {161, 4, 3}, /* ignoring bit difference: 0x00808000 */ 168 {113, 5, 1},
169 {161, 4, 3}, 169 {121, 5, 1},
170 {161, 4, 3} }, 170 {131, 5, 1},
171 {78750000, 171 {135, 5, 1},
172 {33, 3, 1}, 172 {142, 5, 1},
173 {66, 3, 2}, /* ignoring bit difference: 0x00008000 */ 173 {143, 5, 1},
174 {110, 5, 2}, 174 {153, 5, 1},
175 {110, 5, 2} }, 175 {187, 5, 1},
176 {80136000, 176 {208, 5, 1},
177 {28, 5, 0}, 177 {68, 2, 2},
178 {68, 3, 2}, /* ignoring bit difference: 0x00008000 */ 178 {95, 3, 2},
179 {112, 5, 2}, 179 {116, 3, 2},
180 {112, 5, 2} }, 180 {93, 4, 2},
181 {83375000, 181 {119, 4, 2},
182 {93, 2, 3}, 182 {133, 4, 2},
183 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */ 183 {137, 4, 2},
184 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */ 184 {151, 4, 2},
185 {117, 5, 2} }, 185 {166, 4, 2},
186 {83950000, 186 {110, 5, 2},
187 {41, 7, 0}, 187 {112, 5, 2},
188 {117, 5, 2}, /* ignoring bit difference: 0x00008000 */ 188 {117, 5, 2},
189 {117, 5, 2}, 189 {118, 5, 2},
190 {117, 5, 2} }, 190 {120, 5, 2},
191 {84750000, 191 {132, 5, 2},
192 {118, 5, 2}, 192 {137, 5, 2},
193 {118, 5, 2}, /* ignoring bit difference: 0x00808000 */ 193 {141, 5, 2},
194 {118, 5, 2}, 194 {151, 5, 2},
195 {118, 5, 2} }, 195 {166, 5, 2},
196 {85860000, 196 {175, 5, 2},
197 {84, 7, 1}, 197 {191, 5, 2},
198 {120, 5, 2}, /* ignoring bit difference: 0x00808000 */ 198 {206, 5, 2},
199 {120, 5, 2}, 199 {174, 7, 2},
200 {118, 5, 2} }, 200 {82, 3, 3},
201 {88750000, 201 {109, 3, 3},
202 {31, 5, 0}, 202 {117, 4, 3},
203 {124, 5, 2}, /* ignoring bit difference: 0x00808000 */ 203 {150, 4, 3},
204 {174, 7, 2}, /* ignoring bit difference: 0x00808000 */ 204 {161, 4, 3},
205 {124, 5, 2} }, 205 {112, 5, 3},
206 {94500000, 206 {115, 5, 3},
207 {33, 5, 0}, 207 {121, 5, 3},
208 {132, 5, 2}, /* ignoring bit difference: 0x00008000 */ 208 {127, 5, 3},
209 {132, 5, 2}, 209 {129, 5, 3},
210 {132, 5, 2} }, 210 {131, 5, 3},
211 {97750000, 211 {134, 5, 3},
212 {82, 6, 1}, 212 {138, 5, 3},
213 {137, 5, 2}, /* ignoring bit difference: 0x00808000 */ 213 {148, 5, 3},
214 {137, 5, 2}, 214 {157, 5, 3},
215 {137, 5, 2} }, 215 {169, 5, 3},
216 {101000000, 216 {172, 5, 3},
217 {127, 9, 1}, 217 {190, 5, 3},
218 {141, 5, 2}, /* ignoring bit difference: 0x00808000 */ 218 {195, 5, 3},
219 {141, 5, 2}, 219 {196, 5, 3},
220 {141, 5, 2} }, 220 {208, 5, 3},
221 {106500000, 221 {141, 5, 4},
222 {119, 4, 2}, 222 {150, 5, 4},
223 {119, 4, 2}, /* ignoring bit difference: 0x00808000 */ 223 {166, 5, 4},
224 {119, 4, 2}, 224 {176, 5, 4},
225 {149, 5, 2} }, 225 {177, 5, 4},
226 {108000000, 226 {183, 5, 4},
227 {121, 4, 2}, 227 {202, 5, 4}
228 {121, 4, 2}, /* ignoring bit difference: 0x00808000 */ 228};
229 {151, 5, 2}, 229
230 {151, 5, 2} }, 230static struct pll_config vx855_pll_config[] = {
231 {113309000, 231 {86, 4, 1},
232 {95, 12, 0}, 232 {108, 5, 1},
233 {95, 3, 2}, /* ignoring bit difference: 0x00808000 */ 233 {110, 5, 1},
234 {95, 3, 2}, 234 {113, 5, 1},
235 {159, 5, 2} }, 235 {121, 5, 1},
236 {118840000, 236 {131, 5, 1},
237 {83, 5, 1}, 237 {135, 5, 1},
238 {166, 5, 2}, /* ignoring bit difference: 0x00808000 */ 238 {142, 5, 1},
239 {166, 5, 2}, 239 {143, 5, 1},
240 {166, 5, 2} }, 240 {153, 5, 1},
241 {119000000, 241 {164, 5, 1},
242 {108, 13, 0}, 242 {187, 5, 1},
243 {133, 4, 2}, /* ignoring bit difference: 0x00808000 */ 243 {208, 5, 1},
244 {133, 4, 2}, 244 {110, 5, 2},
245 {167, 5, 2} }, 245 {112, 5, 2},
246 {121750000, 246 {117, 5, 2},
247 {85, 5, 1}, 247 {118, 5, 2},
248 {170, 5, 2}, /* ignoring bit difference: 0x00808000 */ 248 {124, 5, 2},
249 {68, 2, 2}, 249 {132, 5, 2},
250 {0, 0, 0} }, 250 {137, 5, 2},
251 {125104000, 251 {141, 5, 2},
252 {53, 6, 0}, /* ignoring bit difference: 0x00008000 */ 252 {149, 5, 2},
253 {106, 3, 2}, /* ignoring bit difference: 0x00008000 */ 253 {151, 5, 2},
254 {175, 5, 2}, 254 {159, 5, 2},
255 {0, 0, 0} }, 255 {166, 5, 2},
256 {135000000, 256 {167, 5, 2},
257 {94, 5, 1}, 257 {172, 5, 2},
258 {28, 3, 0}, /* ignoring bit difference: 0x00804000 */ 258 {189, 5, 2},
259 {151, 4, 2}, 259 {191, 5, 2},
260 {189, 5, 2} }, 260 {194, 5, 2},
261 {136700000, 261 {206, 5, 2},
262 {115, 12, 0}, 262 {208, 5, 2},
263 {191, 5, 2}, /* ignoring bit difference: 0x00808000 */ 263 {83, 3, 3},
264 {191, 5, 2}, 264 {88, 3, 3},
265 {191, 5, 2} }, 265 {109, 3, 3},
266 {138400000, 266 {112, 3, 3},
267 {87, 9, 0}, 267 {103, 4, 3},
268 {116, 3, 2}, /* ignoring bit difference: 0x00808000 */ 268 {105, 4, 3},
269 {116, 3, 2}, 269 {161, 4, 3},
270 {194, 5, 2} }, 270 {112, 5, 3},
271 {146760000, 271 {115, 5, 3},
272 {103, 5, 1}, 272 {121, 5, 3},
273 {206, 5, 2}, /* ignoring bit difference: 0x00808000 */ 273 {127, 5, 3},
274 {206, 5, 2}, 274 {134, 5, 3},
275 {206, 5, 2} }, 275 {137, 5, 3},
276 {153920000, 276 {148, 5, 3},
277 {86, 8, 0}, 277 {157, 5, 3},
278 {86, 4, 1}, /* ignoring bit difference: 0x00808000 */ 278 {169, 5, 3},
279 {86, 4, 1}, 279 {172, 5, 3},
280 {86, 4, 1} }, /* FIXED: old = {84, 2, 1} */ 280 {182, 5, 3},
281 {156000000, 281 {191, 5, 3},
282 {109, 5, 1}, 282 {195, 5, 3},
283 {109, 5, 1}, /* ignoring bit difference: 0x00808000 */ 283 {209, 5, 3},
284 {109, 5, 1}, 284 {142, 4, 4},
285 {108, 5, 1} }, 285 {146, 4, 4},
286 {157500000, 286 {161, 4, 4},
287 {55, 5, 0}, /* ignoring bit difference: 0x00008000 */ 287 {141, 5, 4},
288 {22, 2, 0}, /* ignoring bit difference: 0x00802000 */ 288 {150, 5, 4},
289 {110, 5, 1}, 289 {165, 5, 4},
290 {110, 5, 1} }, 290 {176, 5, 4}
291 {162000000,
292 {113, 5, 1},
293 {113, 5, 1}, /* ignoring bit difference: 0x00808000 */
294 {113, 5, 1},
295 {113, 5, 1} },
296 {187000000,
297 {118, 9, 0},
298 {131, 5, 1}, /* ignoring bit difference: 0x00808000 */
299 {131, 5, 1},
300 {131, 5, 1} },
301 {193295000,
302 {108, 8, 0},
303 {81, 3, 1}, /* ignoring bit difference: 0x00808000 */
304 {135, 5, 1},
305 {135, 5, 1} },
306 {202500000,
307 {99, 7, 0},
308 {85, 3, 1}, /* ignoring bit difference: 0x00808000 */
309 {142, 5, 1},
310 {142, 5, 1} },
311 {204000000,
312 {100, 7, 0},
313 {143, 5, 1}, /* ignoring bit difference: 0x00808000 */
314 {143, 5, 1},
315 {143, 5, 1} },
316 {218500000,
317 {92, 6, 0},
318 {153, 5, 1}, /* ignoring bit difference: 0x00808000 */
319 {153, 5, 1},
320 {153, 5, 1} },
321 {234000000,
322 {98, 6, 0},
323 {98, 3, 1}, /* ignoring bit difference: 0x00008000 */
324 {98, 3, 1},
325 {164, 5, 1} },
326 {267250000,
327 {112, 6, 0},
328 {112, 3, 1}, /* ignoring bit difference: 0x00808000 */
329 {187, 5, 1},
330 {187, 5, 1} },
331 {297500000,
332 {102, 5, 0}, /* ignoring bit difference: 0x00008000 */
333 {166, 4, 1}, /* ignoring bit difference: 0x00008000 */
334 {208, 5, 1},
335 {208, 5, 1} },
336 {74481000,
337 {26, 5, 0},
338 {125, 3, 3}, /* ignoring bit difference: 0x00808000 */
339 {208, 5, 3},
340 {209, 5, 3} },
341 {172798000,
342 {121, 5, 1},
343 {121, 5, 1}, /* ignoring bit difference: 0x00808000 */
344 {121, 5, 1},
345 {121, 5, 1} },
346 {122614000,
347 {60, 7, 0},
348 {137, 4, 2}, /* ignoring bit difference: 0x00808000 */
349 {137, 4, 2},
350 {172, 5, 2} },
351 {74270000,
352 {83, 8, 1},
353 {208, 5, 3},
354 {208, 5, 3},
355 {0, 0, 0} },
356 {148500000,
357 {83, 8, 0},
358 {208, 5, 2},
359 {166, 4, 2},
360 {208, 5, 2} }
361}; 291};
362 292
363/* according to VIA Technologies these values are based on experiment */ 293/* according to VIA Technologies these values are based on experiment */
@@ -1692,43 +1622,63 @@ static u32 vx855_encode_pll(struct pll_config pll)
1692 | pll.multiplier; 1622 | pll.multiplier;
1693} 1623}
1694 1624
1695u32 viafb_get_clk_value(int clk) 1625static inline u32 get_pll_internal_frequency(u32 ref_freq,
1626 struct pll_config pll)
1696{ 1627{
1697 u32 value = 0; 1628 return ref_freq / pll.divisor * pll.multiplier;
1698 int i = 0; 1629}
1699 1630
1700 while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk) 1631static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)
1701 i++; 1632{
1633 return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;
1634}
1702 1635
1703 if (i == NUM_TOTAL_PLL_TABLE) { 1636static struct pll_config get_pll_config(struct pll_config *config, int size,
1704 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!"); 1637 int clk)
1705 } else { 1638{
1706 switch (viaparinfo->chip_info->gfx_chip_name) { 1639 struct pll_config best = config[0];
1707 case UNICHROME_CLE266: 1640 const u32 f0 = 14318180; /* X1 frequency */
1708 case UNICHROME_K400: 1641 int i;
1709 value = cle266_encode_pll(pll_value[i].cle266_pll);
1710 break;
1711 1642
1712 case UNICHROME_K800: 1643 for (i = 1; i < size; i++) {
1713 case UNICHROME_PM800: 1644 if (abs(get_pll_output_frequency(f0, config[i]) - clk)
1714 case UNICHROME_CN700: 1645 < abs(get_pll_output_frequency(f0, best) - clk))
1715 value = k800_encode_pll(pll_value[i].k800_pll); 1646 best = config[i];
1716 break; 1647 }
1717 1648
1718 case UNICHROME_CX700: 1649 return best;
1719 case UNICHROME_CN750: 1650}
1720 case UNICHROME_K8M890:
1721 case UNICHROME_P4M890:
1722 case UNICHROME_P4M900:
1723 case UNICHROME_VX800:
1724 value = k800_encode_pll(pll_value[i].cx700_pll);
1725 break;
1726 1651
1727 case UNICHROME_VX855: 1652u32 viafb_get_clk_value(int clk)
1728 case UNICHROME_VX900: 1653{
1729 value = vx855_encode_pll(pll_value[i].vx855_pll); 1654 u32 value = 0;
1730 break; 1655
1731 } 1656 switch (viaparinfo->chip_info->gfx_chip_name) {
1657 case UNICHROME_CLE266:
1658 case UNICHROME_K400:
1659 value = cle266_encode_pll(get_pll_config(cle266_pll_config,
1660 ARRAY_SIZE(cle266_pll_config), clk));
1661 break;
1662 case UNICHROME_K800:
1663 case UNICHROME_PM800:
1664 case UNICHROME_CN700:
1665 value = k800_encode_pll(get_pll_config(k800_pll_config,
1666 ARRAY_SIZE(k800_pll_config), clk));
1667 break;
1668 case UNICHROME_CX700:
1669 case UNICHROME_CN750:
1670 case UNICHROME_K8M890:
1671 case UNICHROME_P4M890:
1672 case UNICHROME_P4M900:
1673 case UNICHROME_VX800:
1674 value = k800_encode_pll(get_pll_config(cx700_pll_config,
1675 ARRAY_SIZE(cx700_pll_config), clk));
1676 break;
1677 case UNICHROME_VX855:
1678 case UNICHROME_VX900:
1679 value = vx855_encode_pll(get_pll_config(vx855_pll_config,
1680 ARRAY_SIZE(vx855_pll_config), clk));
1681 break;
1732 } 1682 }
1733 1683
1734 return value; 1684 return value;
@@ -2052,7 +2002,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2052 int i; 2002 int i;
2053 int index = 0; 2003 int index = 0;
2054 int h_addr, v_addr; 2004 int h_addr, v_addr;
2055 u32 pll_D_N; 2005 u32 pll_D_N, clock;
2056 2006
2057 for (i = 0; i < video_mode->mode_array; i++) { 2007 for (i = 0; i < video_mode->mode_array; i++) {
2058 index = i; 2008 index = i;
@@ -2105,7 +2055,9 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2105 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) 2055 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
2106 viafb_load_FIFO_reg(set_iga, h_addr, v_addr); 2056 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
2107 2057
2108 pll_D_N = viafb_get_clk_value(crt_table[index].clk); 2058 clock = crt_reg.hor_total * crt_reg.ver_total
2059 * crt_table[index].refresh_rate;
2060 pll_D_N = viafb_get_clk_value(clock);
2109 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N); 2061 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2110 viafb_set_vclock(pll_D_N, set_iga); 2062 viafb_set_vclock(pll_D_N, set_iga);
2111 2063
@@ -2616,35 +2568,43 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2616int viafb_get_pixclock(int hres, int vres, int vmode_refresh) 2568int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2617{ 2569{
2618 int i; 2570 int i;
2571 struct crt_mode_table *best;
2572 struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2619 2573
2620 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { 2574 if (!vmode)
2621 if ((hres == res_map_refresh_tbl[i].hres) 2575 return RES_640X480_60HZ_PIXCLOCK;
2622 && (vres == res_map_refresh_tbl[i].vres) 2576
2623 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh)) 2577 best = &vmode->crtc[0];
2624 return res_map_refresh_tbl[i].pixclock; 2578 for (i = 1; i < vmode->mode_array; i++) {
2579 if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)
2580 < abs(best->refresh_rate - vmode_refresh))
2581 best = &vmode->crtc[i];
2625 } 2582 }
2626 return RES_640X480_60HZ_PIXCLOCK;
2627 2583
2584 return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)
2585 * 1000 / best->refresh_rate;
2628} 2586}
2629 2587
2630int viafb_get_refresh(int hres, int vres, u32 long_refresh) 2588int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2631{ 2589{
2632#define REFRESH_TOLERANCE 3 2590 int i;
2633 int i, nearest = -1, diff = REFRESH_TOLERANCE; 2591 struct crt_mode_table *best;
2634 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { 2592 struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2635 if ((hres == res_map_refresh_tbl[i].hres) 2593
2636 && (vres == res_map_refresh_tbl[i].vres) 2594 if (!vmode)
2637 && (diff > (abs(long_refresh - 2595 return 60;
2638 res_map_refresh_tbl[i].vmode_refresh)))) { 2596
2639 diff = abs(long_refresh - res_map_refresh_tbl[i]. 2597 best = &vmode->crtc[0];
2640 vmode_refresh); 2598 for (i = 1; i < vmode->mode_array; i++) {
2641 nearest = i; 2599 if (abs(vmode->crtc[i].refresh_rate - long_refresh)
2642 } 2600 < abs(best->refresh_rate - long_refresh))
2601 best = &vmode->crtc[i];
2643 } 2602 }
2644#undef REFRESH_TOLERANCE 2603
2645 if (nearest > 0) 2604 if (abs(best->refresh_rate - long_refresh) > 3)
2646 return res_map_refresh_tbl[nearest].vmode_refresh; 2605 return 60;
2647 return 60; 2606
2607 return best->refresh_rate;
2648} 2608}
2649 2609
2650static void device_off(void) 2610static void device_off(void)
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 668d534542ef..7295263299f7 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
893/* VT3410 chipset*/ 893/* VT3410 chipset*/
894#define VX900_FUNCTION3 0x3410 894#define VX900_FUNCTION3 0x3410
895 895
896#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
897
898struct IODATA { 896struct IODATA {
899 u8 Index; 897 u8 Index;
900 u8 Mask; 898 u8 Mask;
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index d75e3f8e9061..64bc7e763103 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -562,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
562 int set_vres = plvds_setting_info->v_active; 562 int set_vres = plvds_setting_info->v_active;
563 int panel_hres = plvds_setting_info->lcd_panel_hres; 563 int panel_hres = plvds_setting_info->lcd_panel_hres;
564 int panel_vres = plvds_setting_info->lcd_panel_vres; 564 int panel_vres = plvds_setting_info->lcd_panel_vres;
565 u32 pll_D_N; 565 u32 pll_D_N, clock;
566 struct display_timing mode_crt_reg, panel_crt_reg; 566 struct display_timing mode_crt_reg, panel_crt_reg;
567 struct crt_mode_table *panel_crt_table = NULL; 567 struct crt_mode_table *panel_crt_table = NULL;
568 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, 568 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
@@ -577,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
577 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n"); 577 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
578 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) 578 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
579 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info); 579 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
580 plvds_setting_info->vclk = panel_crt_table->clk; 580 clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
581 * panel_crt_table->refresh_rate;
582 plvds_setting_info->vclk = clock;
581 if (set_iga == IGA1) { 583 if (set_iga == IGA1) {
582 /* IGA1 doesn't have LCD scaling, so set it as centering. */ 584 /* IGA1 doesn't have LCD scaling, so set it as centering. */
583 viafb_load_crtc_timing(lcd_centering_timging 585 viafb_load_crtc_timing(lcd_centering_timging
@@ -612,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
612 614
613 fill_lcd_format(); 615 fill_lcd_format();
614 616
615 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk); 617 pll_D_N = viafb_get_clk_value(clock);
616 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N); 618 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
617 viafb_set_vclock(pll_D_N, set_iga); 619 viafb_set_vclock(pll_D_N, set_iga);
618 lcd_patch_skew(plvds_setting_info, plvds_chip_info); 620 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
index 2cbe1031b421..4b7831f0d012 100644
--- a/drivers/video/via/share.h
+++ b/drivers/video/via/share.h
@@ -627,77 +627,6 @@
627#define M2048x1536_R60_HSP NEGATIVE 627#define M2048x1536_R60_HSP NEGATIVE
628#define M2048x1536_R60_VSP POSITIVE 628#define M2048x1536_R60_VSP POSITIVE
629 629
630/* define PLL index: */
631#define CLK_25_175M 25175000
632#define CLK_26_880M 26880000
633#define CLK_29_581M 29581000
634#define CLK_31_500M 31500000
635#define CLK_31_728M 31728000
636#define CLK_32_668M 32688000
637#define CLK_36_000M 36000000
638#define CLK_40_000M 40000000
639#define CLK_41_291M 41291000
640#define CLK_43_163M 43163000
641#define CLK_45_250M 45250000 /* 45.46MHz */
642#define CLK_46_000M 46000000
643#define CLK_46_996M 46996000
644#define CLK_48_000M 48000000
645#define CLK_48_875M 48875000
646#define CLK_49_500M 49500000
647#define CLK_52_406M 52406000
648#define CLK_52_977M 52977000
649#define CLK_56_250M 56250000
650#define CLK_57_275M 57275000
651#define CLK_60_466M 60466000
652#define CLK_61_500M 61500000
653#define CLK_65_000M 65000000
654#define CLK_65_178M 65178000
655#define CLK_66_750M 66750000 /* 67.116MHz */
656#define CLK_68_179M 68179000
657#define CLK_69_924M 69924000
658#define CLK_70_159M 70159000
659#define CLK_72_000M 72000000
660#define CLK_74_270M 74270000
661#define CLK_78_750M 78750000
662#define CLK_80_136M 80136000
663#define CLK_83_375M 83375000
664#define CLK_83_950M 83950000
665#define CLK_84_750M 84750000 /* 84.537Mhz */
666#define CLK_85_860M 85860000
667#define CLK_88_750M 88750000
668#define CLK_94_500M 94500000
669#define CLK_97_750M 97750000
670#define CLK_101_000M 101000000
671#define CLK_106_500M 106500000
672#define CLK_108_000M 108000000
673#define CLK_113_309M 113309000
674#define CLK_118_840M 118840000
675#define CLK_119_000M 119000000
676#define CLK_121_750M 121750000 /* 121.704MHz */
677#define CLK_125_104M 125104000
678#define CLK_135_000M 135000000
679#define CLK_136_700M 136700000
680#define CLK_138_400M 138400000
681#define CLK_146_760M 146760000
682#define CLK_148_500M 148500000
683
684#define CLK_153_920M 153920000
685#define CLK_156_000M 156000000
686#define CLK_157_500M 157500000
687#define CLK_162_000M 162000000
688#define CLK_187_000M 187000000
689#define CLK_193_295M 193295000
690#define CLK_202_500M 202500000
691#define CLK_204_000M 204000000
692#define CLK_218_500M 218500000
693#define CLK_234_000M 234000000
694#define CLK_267_250M 267250000
695#define CLK_297_500M 297500000
696#define CLK_74_481M 74481000
697#define CLK_172_798M 172798000
698#define CLK_122_614M 122614000
699
700
701/* Definition CRTC Timing Index */ 630/* Definition CRTC Timing Index */
702#define H_TOTAL_INDEX 0 631#define H_TOTAL_INDEX 0
703#define H_ADDR_INDEX 1 632#define H_ADDR_INDEX 1
@@ -722,76 +651,7 @@
722 651
723/* Definition Video Mode Pixel Clock (picoseconds) 652/* Definition Video Mode Pixel Clock (picoseconds)
724*/ 653*/
725#define RES_480X640_60HZ_PIXCLOCK 39722
726#define RES_640X480_60HZ_PIXCLOCK 39722 654#define RES_640X480_60HZ_PIXCLOCK 39722
727#define RES_640X480_75HZ_PIXCLOCK 31747
728#define RES_640X480_85HZ_PIXCLOCK 27777
729#define RES_640X480_100HZ_PIXCLOCK 23168
730#define RES_640X480_120HZ_PIXCLOCK 19081
731#define RES_720X480_60HZ_PIXCLOCK 37020
732#define RES_720X576_60HZ_PIXCLOCK 30611
733#define RES_800X600_60HZ_PIXCLOCK 25000
734#define RES_800X600_75HZ_PIXCLOCK 20203
735#define RES_800X600_85HZ_PIXCLOCK 17777
736#define RES_800X600_100HZ_PIXCLOCK 14667
737#define RES_800X600_120HZ_PIXCLOCK 11912
738#define RES_800X480_60HZ_PIXCLOCK 33805
739#define RES_848X480_60HZ_PIXCLOCK 31756
740#define RES_856X480_60HZ_PIXCLOCK 31518
741#define RES_1024X512_60HZ_PIXCLOCK 24218
742#define RES_1024X600_60HZ_PIXCLOCK 20460
743#define RES_1024X768_60HZ_PIXCLOCK 15385
744#define RES_1024X768_75HZ_PIXCLOCK 12699
745#define RES_1024X768_85HZ_PIXCLOCK 10582
746#define RES_1024X768_100HZ_PIXCLOCK 8825
747#define RES_1152X864_75HZ_PIXCLOCK 9259
748#define RES_1280X768_60HZ_PIXCLOCK 12480
749#define RES_1280X800_60HZ_PIXCLOCK 11994
750#define RES_1280X960_60HZ_PIXCLOCK 9259
751#define RES_1280X1024_60HZ_PIXCLOCK 9260
752#define RES_1280X1024_75HZ_PIXCLOCK 7408
753#define RES_1280X768_85HZ_PIXCLOCK 6349
754#define RES_1440X1050_60HZ_PIXCLOCK 7993
755#define RES_1600X1200_60HZ_PIXCLOCK 6172
756#define RES_1600X1200_75HZ_PIXCLOCK 4938
757#define RES_1280X720_60HZ_PIXCLOCK 13426
758#define RES_1200X900_60HZ_PIXCLOCK 17459
759#define RES_1920X1080_60HZ_PIXCLOCK 5787
760#define RES_1400X1050_60HZ_PIXCLOCK 8214
761#define RES_1400X1050_75HZ_PIXCLOCK 6410
762#define RES_1368X768_60HZ_PIXCLOCK 11647
763#define RES_960X600_60HZ_PIXCLOCK 22099
764#define RES_1000X600_60HZ_PIXCLOCK 20834
765#define RES_1024X576_60HZ_PIXCLOCK 21278
766#define RES_1088X612_60HZ_PIXCLOCK 18877
767#define RES_1152X720_60HZ_PIXCLOCK 14981
768#define RES_1200X720_60HZ_PIXCLOCK 14253
769#define RES_1280X600_60HZ_PIXCLOCK 16260
770#define RES_1280X720_50HZ_PIXCLOCK 16538
771#define RES_1280X768_50HZ_PIXCLOCK 15342
772#define RES_1366X768_50HZ_PIXCLOCK 14301
773#define RES_1366X768_60HZ_PIXCLOCK 11646
774#define RES_1360X768_60HZ_PIXCLOCK 11799
775#define RES_1440X900_60HZ_PIXCLOCK 9390
776#define RES_1440X900_75HZ_PIXCLOCK 7315
777#define RES_1600X900_60HZ_PIXCLOCK 8415
778#define RES_1600X1024_60HZ_PIXCLOCK 7315
779#define RES_1680X1050_60HZ_PIXCLOCK 6814
780#define RES_1680X1050_75HZ_PIXCLOCK 5348
781#define RES_1792X1344_60HZ_PIXCLOCK 4902
782#define RES_1856X1392_60HZ_PIXCLOCK 4577
783#define RES_1920X1200_60HZ_PIXCLOCK 5173
784#define RES_1920X1440_60HZ_PIXCLOCK 4274
785#define RES_1920X1440_75HZ_PIXCLOCK 3367
786#define RES_2048X1536_60HZ_PIXCLOCK 3742
787
788#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
789#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
790#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
791#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
792#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
793#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
794#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
795 655
796/* LCD display method 656/* LCD display method
797*/ 657*/
@@ -822,7 +682,6 @@ struct display_timing {
822 682
823struct crt_mode_table { 683struct crt_mode_table {
824 int refresh_rate; 684 int refresh_rate;
825 unsigned long clk;
826 int h_sync_polarity; 685 int h_sync_polarity;
827 int v_sync_polarity; 686 int v_sync_polarity;
828 struct display_timing crtc; 687 struct display_timing crtc;
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
index 81274890fc29..8c5bc41ff6a4 100644
--- a/drivers/video/via/viamode.c
+++ b/drivers/video/via/viamode.c
@@ -21,72 +21,6 @@
21 21
22#include <linux/via-core.h> 22#include <linux/via-core.h>
23#include "global.h" 23#include "global.h"
24struct res_map_refresh res_map_refresh_tbl[] = {
25/*hres, vres, vclock, vmode_refresh*/
26 {480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
27 {640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
28 {640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
29 {640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
30 {640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
31 {640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
32 {720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
33 {720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
34 {800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
35 {800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
36 {800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
37 {800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
38 {800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
39 {800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
40 {848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
41 {856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
42 {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
43 {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
44 {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
45 {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
46 {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
47 {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
48/* {1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},*/
49 {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
50 {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
51 {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
52 {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
53 {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
54 {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
55 {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
56 {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
57 {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
58 {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
59 {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
60 {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
61 {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
62 {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
63 {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
64 {960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
65 {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
66 {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
67 {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
68 {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
69 {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
70 {1200, 900, RES_1200X900_60HZ_PIXCLOCK, 60},
71 {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
72 {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
73 {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
74 {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
75 {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
76 {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
77 {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
78 {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
79 {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
80 {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
81 {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
82 {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
83 {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
84 {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
85 {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
86 {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
87 {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
88 {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
89};
90 24
91struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, 25struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
92{VIASR, SR15, 0x02, 0x02}, 26{VIASR, SR15, 0x02, 0x02},
@@ -359,327 +293,320 @@ struct VPITTable VPIT = {
359 293
360/* 480x640 */ 294/* 480x640 */
361static struct crt_mode_table CRTM480x640[] = { 295static struct crt_mode_table CRTM480x640[] = {
362 /* r_rate, vclk, hsp, vsp */ 296 /* r_rate, hsp, vsp */
363 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 297 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
364 {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP, 298 {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP,
365 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/ 299 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/
366}; 300};
367 301
368/* 640x480*/ 302/* 640x480*/
369static struct crt_mode_table CRTM640x480[] = { 303static struct crt_mode_table CRTM640x480[] = {
370 /*r_rate,vclk,hsp,vsp */ 304 /*r_rate,hsp,vsp */
371 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 305 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
372 {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP, 306 {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP,
373 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} }, 307 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
374 {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP, 308 {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP,
375 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} }, 309 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
376 {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP, 310 {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP,
377 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} }, 311 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
378 {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP, 312 {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP,
379 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/ 313 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
380 {REFRESH_120, CLK_52_406M, M640X480_R120_HSP, 314 {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP,
381 M640X480_R120_VSP, 315 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/
382 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481,
383 3} } /*GTF*/
384}; 316};
385 317
386/*720x480 (GTF)*/ 318/*720x480 (GTF)*/
387static struct crt_mode_table CRTM720x480[] = { 319static struct crt_mode_table CRTM720x480[] = {
388 /*r_rate,vclk,hsp,vsp */ 320 /*r_rate,hsp,vsp */
389 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 321 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
390 {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP, 322 {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP,
391 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} } 323 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
392 324
393}; 325};
394 326
395/*720x576 (GTF)*/ 327/*720x576 (GTF)*/
396static struct crt_mode_table CRTM720x576[] = { 328static struct crt_mode_table CRTM720x576[] = {
397 /*r_rate,vclk,hsp,vsp */ 329 /*r_rate,hsp,vsp */
398 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 330 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
399 {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP, 331 {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP,
400 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} } 332 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
401}; 333};
402 334
403/* 800x480 (CVT) */ 335/* 800x480 (CVT) */
404static struct crt_mode_table CRTM800x480[] = { 336static struct crt_mode_table CRTM800x480[] = {
405 /* r_rate, vclk, hsp, vsp */ 337 /* r_rate, hsp, vsp */
406 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 338 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
407 {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP, 339 {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP,
408 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} } 340 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
409}; 341};
410 342
411/* 800x600*/ 343/* 800x600*/
412static struct crt_mode_table CRTM800x600[] = { 344static struct crt_mode_table CRTM800x600[] = {
413 /*r_rate,vclk,hsp,vsp */ 345 /*r_rate,hsp,vsp */
414 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 346 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
415 {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP, 347 {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP,
416 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} }, 348 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
417 {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP, 349 {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP,
418 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} }, 350 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
419 {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP, 351 {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP,
420 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} }, 352 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
421 {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP, 353 {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP,
422 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} }, 354 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
423 {REFRESH_120, CLK_83_950M, M800X600_R120_HSP, 355 {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP,
424 M800X600_R120_VSP, 356 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} }
425 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601,
426 3} }
427}; 357};
428 358
429/* 848x480 (CVT) */ 359/* 848x480 (CVT) */
430static struct crt_mode_table CRTM848x480[] = { 360static struct crt_mode_table CRTM848x480[] = {
431 /* r_rate, vclk, hsp, vsp */ 361 /* r_rate, hsp, vsp */
432 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 362 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
433 {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP, 363 {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP,
434 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} } 364 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
435}; 365};
436 366
437/*856x480 (GTF) convert to 852x480*/ 367/*856x480 (GTF) convert to 852x480*/
438static struct crt_mode_table CRTM852x480[] = { 368static struct crt_mode_table CRTM852x480[] = {
439 /*r_rate,vclk,hsp,vsp */ 369 /*r_rate,hsp,vsp */
440 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 370 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
441 {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP, 371 {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
442 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} } 372 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
443}; 373};
444 374
445/*1024x512 (GTF)*/ 375/*1024x512 (GTF)*/
446static struct crt_mode_table CRTM1024x512[] = { 376static struct crt_mode_table CRTM1024x512[] = {
447 /*r_rate,vclk,hsp,vsp */ 377 /*r_rate,hsp,vsp */
448 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 378 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
449 {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP, 379 {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
450 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} } 380 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
451 381
452}; 382};
453 383
454/* 1024x600*/ 384/* 1024x600*/
455static struct crt_mode_table CRTM1024x600[] = { 385static struct crt_mode_table CRTM1024x600[] = {
456 /*r_rate,vclk,hsp,vsp */ 386 /*r_rate,hsp,vsp */
457 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 387 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
458 {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP, 388 {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
459 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} }, 389 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
460}; 390};
461 391
462/* 1024x768*/ 392/* 1024x768*/
463static struct crt_mode_table CRTM1024x768[] = { 393static struct crt_mode_table CRTM1024x768[] = {
464 /*r_rate,vclk,hsp,vsp */ 394 /*r_rate,hsp,vsp */
465 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 395 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
466 {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP, 396 {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
467 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} }, 397 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
468 {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP, 398 {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
469 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} }, 399 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
470 {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP, 400 {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
471 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} }, 401 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
472 {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP, 402 {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
473 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} } 403 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
474}; 404};
475 405
476/* 1152x864*/ 406/* 1152x864*/
477static struct crt_mode_table CRTM1152x864[] = { 407static struct crt_mode_table CRTM1152x864[] = {
478 /*r_rate,vclk,hsp,vsp */ 408 /*r_rate,hsp,vsp */
479 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 409 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
480 {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP, 410 {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
481 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} } 411 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
482 412
483}; 413};
484 414
485/* 1280x720 (HDMI 720P)*/ 415/* 1280x720 (HDMI 720P)*/
486static struct crt_mode_table CRTM1280x720[] = { 416static struct crt_mode_table CRTM1280x720[] = {
487 /*r_rate,vclk,hsp,vsp */ 417 /*r_rate,hsp,vsp */
488 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 418 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
489 {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP, 419 {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
490 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} }, 420 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
491 {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP, 421 {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
492 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} } 422 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
493}; 423};
494 424
495/*1280x768 (GTF)*/ 425/*1280x768 (GTF)*/
496static struct crt_mode_table CRTM1280x768[] = { 426static struct crt_mode_table CRTM1280x768[] = {
497 /*r_rate,vclk,hsp,vsp */ 427 /*r_rate,hsp,vsp */
498 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 428 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
499 {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP, 429 {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
500 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} }, 430 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
501 {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP, 431 {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
502 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} } 432 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
503}; 433};
504 434
505/* 1280x800 (CVT) */ 435/* 1280x800 (CVT) */
506static struct crt_mode_table CRTM1280x800[] = { 436static struct crt_mode_table CRTM1280x800[] = {
507 /* r_rate, vclk, hsp, vsp */ 437 /* r_rate, hsp, vsp */
508 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 438 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
509 {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP, 439 {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
510 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} } 440 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
511}; 441};
512 442
513/*1280x960*/ 443/*1280x960*/
514static struct crt_mode_table CRTM1280x960[] = { 444static struct crt_mode_table CRTM1280x960[] = {
515 /*r_rate,vclk,hsp,vsp */ 445 /*r_rate,hsp,vsp */
516 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 446 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
517 {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP, 447 {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
518 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} } 448 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
519}; 449};
520 450
521/* 1280x1024*/ 451/* 1280x1024*/
522static struct crt_mode_table CRTM1280x1024[] = { 452static struct crt_mode_table CRTM1280x1024[] = {
523 /*r_rate,vclk,,hsp,vsp */ 453 /*r_rate,hsp,vsp */
524 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 454 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
525 {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP, 455 {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
526 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025, 456 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
527 3} }, 457 3} },
528 {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP, 458 {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
529 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025, 459 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
530 3} }, 460 3} },
531 {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP, 461 {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
532 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} } 462 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
533}; 463};
534 464
535/* 1368x768 (GTF) */ 465/* 1368x768 (GTF) */
536static struct crt_mode_table CRTM1368x768[] = { 466static struct crt_mode_table CRTM1368x768[] = {
537 /* r_rate, vclk, hsp, vsp */ 467 /* r_rate, hsp, vsp */
538 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 468 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
539 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, 469 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
540 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} } 470 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
541}; 471};
542 472
543/*1440x1050 (GTF)*/ 473/*1440x1050 (GTF)*/
544static struct crt_mode_table CRTM1440x1050[] = { 474static struct crt_mode_table CRTM1440x1050[] = {
545 /*r_rate,vclk,hsp,vsp */ 475 /*r_rate,hsp,vsp */
546 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 476 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
547 {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP, 477 {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
548 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} } 478 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
549}; 479};
550 480
551/* 1600x1200*/ 481/* 1600x1200*/
552static struct crt_mode_table CRTM1600x1200[] = { 482static struct crt_mode_table CRTM1600x1200[] = {
553 /*r_rate,vclk,hsp,vsp */ 483 /*r_rate,hsp,vsp */
554 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 484 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
555 {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP, 485 {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
556 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 486 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
557 3} }, 487 3} },
558 {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP, 488 {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
559 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} } 489 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
560 490
561}; 491};
562 492
563/* 1680x1050 (CVT) */ 493/* 1680x1050 (CVT) */
564static struct crt_mode_table CRTM1680x1050[] = { 494static struct crt_mode_table CRTM1680x1050[] = {
565 /* r_rate, vclk, hsp, vsp */ 495 /* r_rate, hsp, vsp */
566 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 496 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
567 {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP, 497 {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
568 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053, 498 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
569 6} }, 499 6} },
570 {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP, 500 {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
571 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} } 501 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
572}; 502};
573 503
574/* 1680x1050 (CVT Reduce Blanking) */ 504/* 1680x1050 (CVT Reduce Blanking) */
575static struct crt_mode_table CRTM1680x1050_RB[] = { 505static struct crt_mode_table CRTM1680x1050_RB[] = {
576 /* r_rate, vclk, hsp, vsp */ 506 /* r_rate, hsp, vsp */
577 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 507 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
578 {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP, 508 {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
579 M1680x1050_RB_R60_VSP,
580 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} } 509 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
581}; 510};
582 511
583/* 1920x1080 (CVT)*/ 512/* 1920x1080 (CVT)*/
584static struct crt_mode_table CRTM1920x1080[] = { 513static struct crt_mode_table CRTM1920x1080[] = {
585 /*r_rate,vclk,hsp,vsp */ 514 /*r_rate,hsp,vsp */
586 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 515 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
587 {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP, 516 {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
588 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} } 517 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
589}; 518};
590 519
591/* 1920x1080 (CVT with Reduce Blanking) */ 520/* 1920x1080 (CVT with Reduce Blanking) */
592static struct crt_mode_table CRTM1920x1080_RB[] = { 521static struct crt_mode_table CRTM1920x1080_RB[] = {
593 /* r_rate, vclk, hsp, vsp */ 522 /* r_rate, hsp, vsp */
594 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 523 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
595 {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP, 524 {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
596 M1920X1080_RB_R60_VSP,
597 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} } 525 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
598}; 526};
599 527
600/* 1920x1440*/ 528/* 1920x1440*/
601static struct crt_mode_table CRTM1920x1440[] = { 529static struct crt_mode_table CRTM1920x1440[] = {
602 /*r_rate,vclk,hsp,vsp */ 530 /*r_rate,hsp,vsp */
603 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 531 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
604 {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP, 532 {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
605 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441, 533 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
606 3} }, 534 3} },
607 {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP, 535 {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
608 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} } 536 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
609}; 537};
610 538
611/* 1400x1050 (CVT) */ 539/* 1400x1050 (CVT) */
612static struct crt_mode_table CRTM1400x1050[] = { 540static struct crt_mode_table CRTM1400x1050[] = {
613 /* r_rate, vclk, hsp, vsp */ 541 /* r_rate, hsp, vsp */
614 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 542 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
615 {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP, 543 {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
616 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053, 544 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
617 4} }, 545 4} },
618 {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP, 546 {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
619 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} } 547 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
620}; 548};
621 549
622/* 1400x1050 (CVT Reduce Blanking) */ 550/* 1400x1050 (CVT Reduce Blanking) */
623static struct crt_mode_table CRTM1400x1050_RB[] = { 551static struct crt_mode_table CRTM1400x1050_RB[] = {
624 /* r_rate, vclk, hsp, vsp */ 552 /* r_rate, hsp, vsp */
625 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 553 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
626 {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP, 554 {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
627 M1400X1050_RB_R60_VSP,
628 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} } 555 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
629}; 556};
630 557
631/* 960x600 (CVT) */ 558/* 960x600 (CVT) */
632static struct crt_mode_table CRTM960x600[] = { 559static struct crt_mode_table CRTM960x600[] = {
633 /* r_rate, vclk, hsp, vsp */ 560 /* r_rate, hsp, vsp */
634 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 561 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
635 {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP, 562 {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
636 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} } 563 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
637}; 564};
638 565
639/* 1000x600 (GTF) */ 566/* 1000x600 (GTF) */
640static struct crt_mode_table CRTM1000x600[] = { 567static struct crt_mode_table CRTM1000x600[] = {
641 /* r_rate, vclk, hsp, vsp */ 568 /* r_rate, hsp, vsp */
642 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 569 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
643 {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP, 570 {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
644 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} } 571 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
645}; 572};
646 573
647/* 1024x576 (GTF) */ 574/* 1024x576 (GTF) */
648static struct crt_mode_table CRTM1024x576[] = { 575static struct crt_mode_table CRTM1024x576[] = {
649 /* r_rate, vclk, hsp, vsp */ 576 /* r_rate, hsp, vsp */
650 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 577 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
651 {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP, 578 {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
652 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} } 579 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
653}; 580};
654 581
655/* 1088x612 (CVT) */ 582/* 1088x612 (CVT) */
656static struct crt_mode_table CRTM1088x612[] = { 583static struct crt_mode_table CRTM1088x612[] = {
657 /* r_rate, vclk, hsp, vsp */ 584 /* r_rate, hsp, vsp */
658 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 585 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
659 {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP, 586 {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
660 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} } 587 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
661}; 588};
662 589
663/* 1152x720 (CVT) */ 590/* 1152x720 (CVT) */
664static struct crt_mode_table CRTM1152x720[] = { 591static struct crt_mode_table CRTM1152x720[] = {
665 /* r_rate, vclk, hsp, vsp */ 592 /* r_rate, hsp, vsp */
666 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 593 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
667 {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP, 594 {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
668 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} } 595 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
669}; 596};
670 597
671/* 1200x720 (GTF) */ 598/* 1200x720 (GTF) */
672static struct crt_mode_table CRTM1200x720[] = { 599static struct crt_mode_table CRTM1200x720[] = {
673 /* r_rate, vclk, hsp, vsp */ 600 /* r_rate, hsp, vsp */
674 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 601 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
675 {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP, 602 {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
676 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} } 603 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
677}; 604};
678 605
679/* 1200x900 (DCON) */ 606/* 1200x900 (DCON) */
680static struct crt_mode_table DCON1200x900[] = { 607static struct crt_mode_table DCON1200x900[] = {
681 /* r_rate, vclk, hsp, vsp */ 608 /* r_rate, hsp, vsp */
682 {REFRESH_60, CLK_57_275M, M1200X900_R60_HSP, M1200X900_R60_VSP, 609 {REFRESH_60, M1200X900_R60_HSP, M1200X900_R60_VSP,
683 /* The correct htotal is 1240, but this doesn't raster on VX855. */ 610 /* The correct htotal is 1240, but this doesn't raster on VX855. */
684 /* Via suggested changing to a multiple of 16, hence 1264. */ 611 /* Via suggested changing to a multiple of 16, hence 1264. */
685 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 612 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
@@ -688,121 +615,117 @@ static struct crt_mode_table DCON1200x900[] = {
688 615
689/* 1280x600 (GTF) */ 616/* 1280x600 (GTF) */
690static struct crt_mode_table CRTM1280x600[] = { 617static struct crt_mode_table CRTM1280x600[] = {
691 /* r_rate, vclk, hsp, vsp */ 618 /* r_rate, hsp, vsp */
692 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 619 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
693 {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP, 620 {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
694 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} } 621 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
695}; 622};
696 623
697/* 1360x768 (CVT) */ 624/* 1360x768 (CVT) */
698static struct crt_mode_table CRTM1360x768[] = { 625static struct crt_mode_table CRTM1360x768[] = {
699 /* r_rate, vclk, hsp, vsp */ 626 /* r_rate, hsp, vsp */
700 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 627 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
701 {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP, 628 {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
702 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} } 629 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
703}; 630};
704 631
705/* 1360x768 (CVT Reduce Blanking) */ 632/* 1360x768 (CVT Reduce Blanking) */
706static struct crt_mode_table CRTM1360x768_RB[] = { 633static struct crt_mode_table CRTM1360x768_RB[] = {
707 /* r_rate, vclk, hsp, vsp */ 634 /* r_rate, hsp, vsp */
708 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 635 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
709 {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP, 636 {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
710 M1360X768_RB_R60_VSP,
711 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} } 637 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
712}; 638};
713 639
714/* 1366x768 (GTF) */ 640/* 1366x768 (GTF) */
715static struct crt_mode_table CRTM1366x768[] = { 641static struct crt_mode_table CRTM1366x768[] = {
716 /* r_rate, vclk, hsp, vsp */ 642 /* r_rate, hsp, vsp */
717 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 643 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
718 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, 644 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
719 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }, 645 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
720 {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP, 646 {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
721 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} } 647 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
722}; 648};
723 649
724/* 1440x900 (CVT) */ 650/* 1440x900 (CVT) */
725static struct crt_mode_table CRTM1440x900[] = { 651static struct crt_mode_table CRTM1440x900[] = {
726 /* r_rate, vclk, hsp, vsp */ 652 /* r_rate, hsp, vsp */
727 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 653 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
728 {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP, 654 {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
729 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} }, 655 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
730 {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP, 656 {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
731 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} } 657 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
732}; 658};
733 659
734/* 1440x900 (CVT Reduce Blanking) */ 660/* 1440x900 (CVT Reduce Blanking) */
735static struct crt_mode_table CRTM1440x900_RB[] = { 661static struct crt_mode_table CRTM1440x900_RB[] = {
736 /* r_rate, vclk, hsp, vsp */ 662 /* r_rate, hsp, vsp */
737 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 663 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
738 {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP, 664 {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
739 M1440X900_RB_R60_VSP,
740 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} } 665 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
741}; 666};
742 667
743/* 1600x900 (CVT) */ 668/* 1600x900 (CVT) */
744static struct crt_mode_table CRTM1600x900[] = { 669static struct crt_mode_table CRTM1600x900[] = {
745 /* r_rate, vclk, hsp, vsp */ 670 /* r_rate, hsp, vsp */
746 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 671 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
747 {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP, 672 {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
748 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} } 673 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
749}; 674};
750 675
751/* 1600x900 (CVT Reduce Blanking) */ 676/* 1600x900 (CVT Reduce Blanking) */
752static struct crt_mode_table CRTM1600x900_RB[] = { 677static struct crt_mode_table CRTM1600x900_RB[] = {
753 /* r_rate, vclk, hsp, vsp */ 678 /* r_rate, hsp, vsp */
754 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 679 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
755 {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP, 680 {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
756 M1600X900_RB_R60_VSP,
757 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} } 681 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
758}; 682};
759 683
760/* 1600x1024 (GTF) */ 684/* 1600x1024 (GTF) */
761static struct crt_mode_table CRTM1600x1024[] = { 685static struct crt_mode_table CRTM1600x1024[] = {
762 /* r_rate, vclk, hsp, vsp */ 686 /* r_rate, hsp, vsp */
763 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 687 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
764 {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP, 688 {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
765 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} } 689 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
766}; 690};
767 691
768/* 1792x1344 (DMT) */ 692/* 1792x1344 (DMT) */
769static struct crt_mode_table CRTM1792x1344[] = { 693static struct crt_mode_table CRTM1792x1344[] = {
770 /* r_rate, vclk, hsp, vsp */ 694 /* r_rate, hsp, vsp */
771 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 695 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
772 {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP, 696 {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
773 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} } 697 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
774}; 698};
775 699
776/* 1856x1392 (DMT) */ 700/* 1856x1392 (DMT) */
777static struct crt_mode_table CRTM1856x1392[] = { 701static struct crt_mode_table CRTM1856x1392[] = {
778 /* r_rate, vclk, hsp, vsp */ 702 /* r_rate, hsp, vsp */
779 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 703 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
780 {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP, 704 {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
781 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} } 705 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
782}; 706};
783 707
784/* 1920x1200 (CVT) */ 708/* 1920x1200 (CVT) */
785static struct crt_mode_table CRTM1920x1200[] = { 709static struct crt_mode_table CRTM1920x1200[] = {
786 /* r_rate, vclk, hsp, vsp */ 710 /* r_rate, hsp, vsp */
787 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 711 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
788 {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP, 712 {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
789 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} } 713 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
790}; 714};
791 715
792/* 1920x1200 (CVT with Reduce Blanking) */ 716/* 1920x1200 (CVT with Reduce Blanking) */
793static struct crt_mode_table CRTM1920x1200_RB[] = { 717static struct crt_mode_table CRTM1920x1200_RB[] = {
794 /* r_rate, vclk, hsp, vsp */ 718 /* r_rate, hsp, vsp */
795 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 719 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
796 {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP, 720 {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
797 M1920X1200_RB_R60_VSP,
798 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} } 721 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
799}; 722};
800 723
801/* 2048x1536 (CVT) */ 724/* 2048x1536 (CVT) */
802static struct crt_mode_table CRTM2048x1536[] = { 725static struct crt_mode_table CRTM2048x1536[] = {
803 /* r_rate, vclk, hsp, vsp */ 726 /* r_rate, hsp, vsp */
804 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 727 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
805 {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP, 728 {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
806 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} } 729 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
807}; 730};
808 731
@@ -955,14 +878,12 @@ static struct VideoModeTable viafb_rb_modes[] = {
955}; 878};
956 879
957struct crt_mode_table CEAM1280x720[] = { 880struct crt_mode_table CEAM1280x720[] = {
958 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP, 881 {REFRESH_60, M1280X720_CEA_R60_HSP, M1280X720_CEA_R60_VSP,
959 M1280X720_CEA_R60_VSP,
960 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 882 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
961 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} } 883 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
962}; 884};
963struct crt_mode_table CEAM1920x1080[] = { 885struct crt_mode_table CEAM1920x1080[] = {
964 {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP, 886 {REFRESH_60, M1920X1080_CEA_R60_HSP, M1920X1080_CEA_R60_VSP,
965 M1920X1080_CEA_R60_VSP,
966 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 887 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
967 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} } 888 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
968}; 889};
@@ -972,7 +893,6 @@ struct VideoModeTable CEA_HDMI_Modes[] = {
972 {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)} 893 {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
973}; 894};
974 895
975int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl);
976int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes); 896int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
977int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs); 897int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
978int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs); 898int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
index 5b1ced86514b..8a67ea1b5ef0 100644
--- a/drivers/video/via/viamode.h
+++ b/drivers/video/via/viamode.h
@@ -41,14 +41,6 @@ struct patch_table {
41 struct io_reg *io_reg_table; 41 struct io_reg *io_reg_table;
42}; 42};
43 43
44struct res_map_refresh {
45 int hres;
46 int vres;
47 int pixclock;
48 int vmode_refresh;
49};
50
51extern int NUM_TOTAL_RES_MAP_REFRESH;
52extern int NUM_TOTAL_CEA_MODES; 44extern int NUM_TOTAL_CEA_MODES;
53extern int NUM_TOTAL_CN400_ModeXregs; 45extern int NUM_TOTAL_CN400_ModeXregs;
54extern int NUM_TOTAL_CN700_ModeXregs; 46extern int NUM_TOTAL_CN700_ModeXregs;
@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[];
66extern struct crt_mode_table CEAM1920x1080[]; 58extern struct crt_mode_table CEAM1920x1080[];
67extern struct VideoModeTable CEA_HDMI_Modes[]; 59extern struct VideoModeTable CEA_HDMI_Modes[];
68 60
69extern struct res_map_refresh res_map_refresh_tbl[];
70extern struct io_reg CN400_ModeXregs[]; 61extern struct io_reg CN400_ModeXregs[];
71extern struct io_reg CN700_ModeXregs[]; 62extern struct io_reg CN700_ModeXregs[];
72extern struct io_reg KM400_ModeXregs[]; 63extern struct io_reg KM400_ModeXregs[];
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 12:25:01 -0400