diff options
author | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2010-03-10 18:21:36 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-12 18:52:33 -0500 |
commit | 4bbac05f8c0ab40dcc52ed6dff44e1b0d80fa6e3 (patch) | |
tree | 2829ac5401f88c99e4f796d7445f9311cd34670c /drivers/video/via | |
parent | daacccd1657bdecae8f7c98a8e2b84367a8d4e87 (diff) |
viafb: remove dead code due to IGA1_IGA2
Some code depended on IGA1_IGA2 which was never set (at least with the
symbolic name). Remove this dead code although it might one day be useful
to get a hint on how some things might work. However as this is dead it
is likely full of bugs and would prevent a clean structure (as it has some
very strange things).
Dead code -> no regressions, at least if VIA doesn't do anything very ugly.
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Scott Fang <ScottFang@viatech.com.cn>
Cc: Joseph Chan <JosephChan@via.com.tw>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/via')
-rw-r--r-- | drivers/video/via/hw.c | 22 | ||||
-rw-r--r-- | drivers/video/via/lcd.c | 562 | ||||
-rw-r--r-- | drivers/video/via/share.h | 1 |
3 files changed, 11 insertions, 574 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c index ecbb01f05112..ed8d78a35b29 100644 --- a/drivers/video/via/hw.c +++ b/drivers/video/via/hw.c | |||
@@ -757,11 +757,8 @@ static void set_crt_output_path(int set_iga) | |||
757 | viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6); | 757 | viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6); |
758 | break; | 758 | break; |
759 | case IGA2: | 759 | case IGA2: |
760 | case IGA1_IGA2: | ||
761 | viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); | 760 | viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); |
762 | viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6); | 761 | viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6); |
763 | if (set_iga == IGA1_IGA2) | ||
764 | viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3); | ||
765 | break; | 762 | break; |
766 | } | 763 | } |
767 | } | 764 | } |
@@ -951,13 +948,6 @@ static void set_lcd_output_path(int set_iga, int output_interface) | |||
951 | 948 | ||
952 | enable_second_display_channel(); | 949 | enable_second_display_channel(); |
953 | break; | 950 | break; |
954 | |||
955 | case IGA1_IGA2: | ||
956 | viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3); | ||
957 | viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); | ||
958 | |||
959 | disable_second_display_channel(); | ||
960 | break; | ||
961 | } | 951 | } |
962 | 952 | ||
963 | switch (output_interface) { | 953 | switch (output_interface) { |
@@ -1125,15 +1115,13 @@ void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga) | |||
1125 | struct io_register *reg = NULL; | 1115 | struct io_register *reg = NULL; |
1126 | 1116 | ||
1127 | switch (set_iga) { | 1117 | switch (set_iga) { |
1128 | case IGA1_IGA2: | ||
1129 | case IGA1: | 1118 | case IGA1: |
1130 | reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); | 1119 | reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); |
1131 | viafb_load_reg_num = fetch_count_reg. | 1120 | viafb_load_reg_num = fetch_count_reg. |
1132 | iga1_fetch_count_reg.reg_num; | 1121 | iga1_fetch_count_reg.reg_num; |
1133 | reg = fetch_count_reg.iga1_fetch_count_reg.reg; | 1122 | reg = fetch_count_reg.iga1_fetch_count_reg.reg; |
1134 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | 1123 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
1135 | if (set_iga == IGA1) | 1124 | break; |
1136 | break; | ||
1137 | case IGA2: | 1125 | case IGA2: |
1138 | reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); | 1126 | reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); |
1139 | viafb_load_reg_num = fetch_count_reg. | 1127 | viafb_load_reg_num = fetch_count_reg. |
@@ -1503,7 +1491,7 @@ void viafb_set_vclock(u32 CLK, int set_iga) | |||
1503 | /* H.W. Reset : ON */ | 1491 | /* H.W. Reset : ON */ |
1504 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); | 1492 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); |
1505 | 1493 | ||
1506 | if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) { | 1494 | if (set_iga == IGA1) { |
1507 | /* Change D,N FOR VCLK */ | 1495 | /* Change D,N FOR VCLK */ |
1508 | switch (viaparinfo->chip_info->gfx_chip_name) { | 1496 | switch (viaparinfo->chip_info->gfx_chip_name) { |
1509 | case UNICHROME_CLE266: | 1497 | case UNICHROME_CLE266: |
@@ -1532,7 +1520,7 @@ void viafb_set_vclock(u32 CLK, int set_iga) | |||
1532 | } | 1520 | } |
1533 | } | 1521 | } |
1534 | 1522 | ||
1535 | if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) { | 1523 | if (set_iga == IGA2) { |
1536 | /* Change D,N FOR LCK */ | 1524 | /* Change D,N FOR LCK */ |
1537 | switch (viaparinfo->chip_info->gfx_chip_name) { | 1525 | switch (viaparinfo->chip_info->gfx_chip_name) { |
1538 | case UNICHROME_CLE266: | 1526 | case UNICHROME_CLE266: |
@@ -1561,12 +1549,12 @@ void viafb_set_vclock(u32 CLK, int set_iga) | |||
1561 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); | 1549 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); |
1562 | 1550 | ||
1563 | /* Reset PLL */ | 1551 | /* Reset PLL */ |
1564 | if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) { | 1552 | if (set_iga == IGA1) { |
1565 | viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); | 1553 | viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); |
1566 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); | 1554 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); |
1567 | } | 1555 | } |
1568 | 1556 | ||
1569 | if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) { | 1557 | if (set_iga == IGA2) { |
1570 | viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); | 1558 | viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); |
1571 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); | 1559 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); |
1572 | } | 1560 | } |
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c index 49651e0a914c..1d1176c3dc44 100644 --- a/drivers/video/via/lcd.c +++ b/drivers/video/via/lcd.c | |||
@@ -24,26 +24,6 @@ | |||
24 | 24 | ||
25 | #define viafb_compact_res(x, y) (((x)<<16)|(y)) | 25 | #define viafb_compact_res(x, y) (((x)<<16)|(y)) |
26 | 26 | ||
27 | static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = { | ||
28 | /* IGA2 Shadow Horizontal Total */ | ||
29 | {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D, 0, 7}, {CR71, 3, 3} } }, | ||
30 | /* IGA2 Shadow Horizontal Blank End */ | ||
31 | {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E, 0, 7} } }, | ||
32 | /* IGA2 Shadow Vertical Total */ | ||
33 | {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F, 0, 7}, {CR71, 0, 2} } }, | ||
34 | /* IGA2 Shadow Vertical Addressable Video */ | ||
35 | {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70, 0, 7}, {CR71, 4, 6} } }, | ||
36 | /* IGA2 Shadow Vertical Blank Start */ | ||
37 | {IGA2_SHADOW_VER_BLANK_START_REG_NUM, | ||
38 | {{CR72, 0, 7}, {CR74, 4, 6} } }, | ||
39 | /* IGA2 Shadow Vertical Blank End */ | ||
40 | {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73, 0, 7}, {CR74, 0, 2} } }, | ||
41 | /* IGA2 Shadow Vertical Sync Start */ | ||
42 | {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75, 0, 7}, {CR76, 4, 6} } }, | ||
43 | /* IGA2 Shadow Vertical Sync End */ | ||
44 | {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76, 0, 3} } } | ||
45 | }; | ||
46 | |||
47 | static struct _lcd_scaling_factor lcd_scaling_factor = { | 27 | static struct _lcd_scaling_factor lcd_scaling_factor = { |
48 | /* LCD Horizontal Scaling Factor Register */ | 28 | /* LCD Horizontal Scaling Factor Register */ |
49 | {LCD_HOR_SCALING_FACTOR_REG_NUM, | 29 | {LCD_HOR_SCALING_FACTOR_REG_NUM, |
@@ -65,12 +45,6 @@ static void fp_id_to_vindex(int panel_id); | |||
65 | static int lvds_register_read(int index); | 45 | static int lvds_register_read(int index); |
66 | static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, | 46 | static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, |
67 | int panel_vres); | 47 | int panel_vres); |
68 | static void load_lcd_k400_patch_tbl(int set_hres, int set_vres, | ||
69 | int panel_id); | ||
70 | static void load_lcd_p880_patch_tbl(int set_hres, int set_vres, | ||
71 | int panel_id); | ||
72 | static void load_lcd_patch_regs(int set_hres, int set_vres, | ||
73 | int panel_id, int set_iga); | ||
74 | static void via_pitch_alignment_patch_lcd( | 48 | static void via_pitch_alignment_patch_lcd( |
75 | struct lvds_setting_information *plvds_setting_info, | 49 | struct lvds_setting_information *plvds_setting_info, |
76 | struct lvds_chip_information | 50 | struct lvds_chip_information |
@@ -100,8 +74,6 @@ static void check_diport_of_integrated_lvds( | |||
100 | static struct display_timing lcd_centering_timging(struct display_timing | 74 | static struct display_timing lcd_centering_timging(struct display_timing |
101 | mode_crt_reg, | 75 | mode_crt_reg, |
102 | struct display_timing panel_crt_reg); | 76 | struct display_timing panel_crt_reg); |
103 | static void load_crtc_shadow_timing(struct display_timing mode_timing, | ||
104 | struct display_timing panel_timing); | ||
105 | static void viafb_load_scaling_factor_for_p4m900(int set_hres, | 77 | static void viafb_load_scaling_factor_for_p4m900(int set_hres, |
106 | int set_vres, int panel_hres, int panel_vres); | 78 | int set_vres, int panel_hres, int panel_vres); |
107 | 79 | ||
@@ -543,277 +515,6 @@ static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, | |||
543 | } | 515 | } |
544 | } | 516 | } |
545 | 517 | ||
546 | static void load_lcd_k400_patch_tbl(int set_hres, int set_vres, | ||
547 | int panel_id) | ||
548 | { | ||
549 | u32 compact_mode = viafb_compact_res(set_hres, set_vres); | ||
550 | int reg_num = 0; | ||
551 | struct io_reg *lcd_patch_reg = NULL; | ||
552 | |||
553 | switch (panel_id) { | ||
554 | /* LCD 800x600 */ | ||
555 | case LCD_PANEL_ID1_800X600: | ||
556 | switch (compact_mode) { | ||
557 | case viafb_compact_res(640, 400): | ||
558 | case viafb_compact_res(640, 480): | ||
559 | reg_num = NUM_TOTAL_K400_LCD_RES_6X4_8X6; | ||
560 | lcd_patch_reg = K400_LCD_RES_6X4_8X6; | ||
561 | break; | ||
562 | case viafb_compact_res(720, 480): | ||
563 | case viafb_compact_res(720, 576): | ||
564 | reg_num = NUM_TOTAL_K400_LCD_RES_7X4_8X6; | ||
565 | lcd_patch_reg = K400_LCD_RES_7X4_8X6; | ||
566 | break; | ||
567 | } | ||
568 | break; | ||
569 | |||
570 | /* LCD 1024x768 */ | ||
571 | case LCD_PANEL_ID2_1024X768: | ||
572 | switch (compact_mode) { | ||
573 | case viafb_compact_res(640, 400): | ||
574 | case viafb_compact_res(640, 480): | ||
575 | reg_num = NUM_TOTAL_K400_LCD_RES_6X4_10X7; | ||
576 | lcd_patch_reg = K400_LCD_RES_6X4_10X7; | ||
577 | break; | ||
578 | case viafb_compact_res(720, 480): | ||
579 | case viafb_compact_res(720, 576): | ||
580 | reg_num = NUM_TOTAL_K400_LCD_RES_7X4_10X7; | ||
581 | lcd_patch_reg = K400_LCD_RES_7X4_10X7; | ||
582 | break; | ||
583 | case viafb_compact_res(800, 600): | ||
584 | reg_num = NUM_TOTAL_K400_LCD_RES_8X6_10X7; | ||
585 | lcd_patch_reg = K400_LCD_RES_8X6_10X7; | ||
586 | break; | ||
587 | } | ||
588 | break; | ||
589 | |||
590 | /* LCD 1280x1024 */ | ||
591 | case LCD_PANEL_ID4_1280X1024: | ||
592 | switch (compact_mode) { | ||
593 | case viafb_compact_res(640, 400): | ||
594 | case viafb_compact_res(640, 480): | ||
595 | reg_num = NUM_TOTAL_K400_LCD_RES_6X4_12X10; | ||
596 | lcd_patch_reg = K400_LCD_RES_6X4_12X10; | ||
597 | break; | ||
598 | case viafb_compact_res(720, 480): | ||
599 | case viafb_compact_res(720, 576): | ||
600 | reg_num = NUM_TOTAL_K400_LCD_RES_7X4_12X10; | ||
601 | lcd_patch_reg = K400_LCD_RES_7X4_12X10; | ||
602 | break; | ||
603 | case viafb_compact_res(800, 600): | ||
604 | reg_num = NUM_TOTAL_K400_LCD_RES_8X6_12X10; | ||
605 | lcd_patch_reg = K400_LCD_RES_8X6_12X10; | ||
606 | break; | ||
607 | case viafb_compact_res(1024, 768): | ||
608 | reg_num = NUM_TOTAL_K400_LCD_RES_10X7_12X10; | ||
609 | lcd_patch_reg = K400_LCD_RES_10X7_12X10; | ||
610 | break; | ||
611 | |||
612 | } | ||
613 | break; | ||
614 | |||
615 | /* LCD 1400x1050 */ | ||
616 | case LCD_PANEL_ID5_1400X1050: | ||
617 | switch (compact_mode) { | ||
618 | case viafb_compact_res(640, 480): | ||
619 | reg_num = NUM_TOTAL_K400_LCD_RES_6X4_14X10; | ||
620 | lcd_patch_reg = K400_LCD_RES_6X4_14X10; | ||
621 | break; | ||
622 | case viafb_compact_res(800, 600): | ||
623 | reg_num = NUM_TOTAL_K400_LCD_RES_8X6_14X10; | ||
624 | lcd_patch_reg = K400_LCD_RES_8X6_14X10; | ||
625 | break; | ||
626 | case viafb_compact_res(1024, 768): | ||
627 | reg_num = NUM_TOTAL_K400_LCD_RES_10X7_14X10; | ||
628 | lcd_patch_reg = K400_LCD_RES_10X7_14X10; | ||
629 | break; | ||
630 | case viafb_compact_res(1280, 768): | ||
631 | case viafb_compact_res(1280, 800): | ||
632 | case viafb_compact_res(1280, 960): | ||
633 | case viafb_compact_res(1280, 1024): | ||
634 | reg_num = NUM_TOTAL_K400_LCD_RES_12X10_14X10; | ||
635 | lcd_patch_reg = K400_LCD_RES_12X10_14X10; | ||
636 | break; | ||
637 | } | ||
638 | break; | ||
639 | |||
640 | /* LCD 1600x1200 */ | ||
641 | case LCD_PANEL_ID6_1600X1200: | ||
642 | switch (compact_mode) { | ||
643 | case viafb_compact_res(640, 400): | ||
644 | case viafb_compact_res(640, 480): | ||
645 | reg_num = NUM_TOTAL_K400_LCD_RES_6X4_16X12; | ||
646 | lcd_patch_reg = K400_LCD_RES_6X4_16X12; | ||
647 | break; | ||
648 | case viafb_compact_res(720, 480): | ||
649 | case viafb_compact_res(720, 576): | ||
650 | reg_num = NUM_TOTAL_K400_LCD_RES_7X4_16X12; | ||
651 | lcd_patch_reg = K400_LCD_RES_7X4_16X12; | ||
652 | break; | ||
653 | case viafb_compact_res(800, 600): | ||
654 | reg_num = NUM_TOTAL_K400_LCD_RES_8X6_16X12; | ||
655 | lcd_patch_reg = K400_LCD_RES_8X6_16X12; | ||
656 | break; | ||
657 | case viafb_compact_res(1024, 768): | ||
658 | reg_num = NUM_TOTAL_K400_LCD_RES_10X7_16X12; | ||
659 | lcd_patch_reg = K400_LCD_RES_10X7_16X12; | ||
660 | break; | ||
661 | case viafb_compact_res(1280, 768): | ||
662 | case viafb_compact_res(1280, 800): | ||
663 | case viafb_compact_res(1280, 960): | ||
664 | case viafb_compact_res(1280, 1024): | ||
665 | reg_num = NUM_TOTAL_K400_LCD_RES_12X10_16X12; | ||
666 | lcd_patch_reg = K400_LCD_RES_12X10_16X12; | ||
667 | break; | ||
668 | } | ||
669 | break; | ||
670 | |||
671 | /* LCD 1366x768 */ | ||
672 | case LCD_PANEL_ID7_1366X768: | ||
673 | switch (compact_mode) { | ||
674 | case viafb_compact_res(640, 480): | ||
675 | reg_num = NUM_TOTAL_K400_LCD_RES_6X4_1366X7; | ||
676 | lcd_patch_reg = K400_LCD_RES_6X4_1366X7; | ||
677 | break; | ||
678 | case viafb_compact_res(720, 480): | ||
679 | case viafb_compact_res(720, 576): | ||
680 | reg_num = NUM_TOTAL_K400_LCD_RES_7X4_1366X7; | ||
681 | lcd_patch_reg = K400_LCD_RES_7X4_1366X7; | ||
682 | break; | ||
683 | case viafb_compact_res(800, 600): | ||
684 | reg_num = NUM_TOTAL_K400_LCD_RES_8X6_1366X7; | ||
685 | lcd_patch_reg = K400_LCD_RES_8X6_1366X7; | ||
686 | break; | ||
687 | case viafb_compact_res(1024, 768): | ||
688 | reg_num = NUM_TOTAL_K400_LCD_RES_10X7_1366X7; | ||
689 | lcd_patch_reg = K400_LCD_RES_10X7_1366X7; | ||
690 | break; | ||
691 | case viafb_compact_res(1280, 768): | ||
692 | case viafb_compact_res(1280, 800): | ||
693 | case viafb_compact_res(1280, 960): | ||
694 | case viafb_compact_res(1280, 1024): | ||
695 | reg_num = NUM_TOTAL_K400_LCD_RES_12X10_1366X7; | ||
696 | lcd_patch_reg = K400_LCD_RES_12X10_1366X7; | ||
697 | break; | ||
698 | } | ||
699 | break; | ||
700 | |||
701 | /* LCD 1360x768 */ | ||
702 | case LCD_PANEL_IDB_1360X768: | ||
703 | break; | ||
704 | } | ||
705 | if (reg_num != 0) { | ||
706 | /* H.W. Reset : ON */ | ||
707 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); | ||
708 | |||
709 | viafb_write_regx(lcd_patch_reg, reg_num); | ||
710 | |||
711 | /* H.W. Reset : OFF */ | ||
712 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); | ||
713 | |||
714 | /* Reset PLL */ | ||
715 | viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); | ||
716 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); | ||
717 | |||
718 | /* Fire! */ | ||
719 | outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc); | ||
720 | } | ||
721 | } | ||
722 | |||
723 | static void load_lcd_p880_patch_tbl(int set_hres, int set_vres, | ||
724 | int panel_id) | ||
725 | { | ||
726 | u32 compact_mode = viafb_compact_res(set_hres, set_vres); | ||
727 | int reg_num = 0; | ||
728 | struct io_reg *lcd_patch_reg = NULL; | ||
729 | |||
730 | switch (panel_id) { | ||
731 | case LCD_PANEL_ID5_1400X1050: | ||
732 | switch (compact_mode) { | ||
733 | case viafb_compact_res(640, 480): | ||
734 | reg_num = NUM_TOTAL_P880_LCD_RES_6X4_14X10; | ||
735 | lcd_patch_reg = P880_LCD_RES_6X4_14X10; | ||
736 | break; | ||
737 | case viafb_compact_res(800, 600): | ||
738 | reg_num = NUM_TOTAL_P880_LCD_RES_8X6_14X10; | ||
739 | lcd_patch_reg = P880_LCD_RES_8X6_14X10; | ||
740 | break; | ||
741 | } | ||
742 | break; | ||
743 | case LCD_PANEL_ID6_1600X1200: | ||
744 | switch (compact_mode) { | ||
745 | case viafb_compact_res(640, 400): | ||
746 | case viafb_compact_res(640, 480): | ||
747 | reg_num = NUM_TOTAL_P880_LCD_RES_6X4_16X12; | ||
748 | lcd_patch_reg = P880_LCD_RES_6X4_16X12; | ||
749 | break; | ||
750 | case viafb_compact_res(720, 480): | ||
751 | case viafb_compact_res(720, 576): | ||
752 | reg_num = NUM_TOTAL_P880_LCD_RES_7X4_16X12; | ||
753 | lcd_patch_reg = P880_LCD_RES_7X4_16X12; | ||
754 | break; | ||
755 | case viafb_compact_res(800, 600): | ||
756 | reg_num = NUM_TOTAL_P880_LCD_RES_8X6_16X12; | ||
757 | lcd_patch_reg = P880_LCD_RES_8X6_16X12; | ||
758 | break; | ||
759 | case viafb_compact_res(1024, 768): | ||
760 | reg_num = NUM_TOTAL_P880_LCD_RES_10X7_16X12; | ||
761 | lcd_patch_reg = P880_LCD_RES_10X7_16X12; | ||
762 | break; | ||
763 | case viafb_compact_res(1280, 768): | ||
764 | case viafb_compact_res(1280, 960): | ||
765 | case viafb_compact_res(1280, 1024): | ||
766 | reg_num = NUM_TOTAL_P880_LCD_RES_12X10_16X12; | ||
767 | lcd_patch_reg = P880_LCD_RES_12X10_16X12; | ||
768 | break; | ||
769 | } | ||
770 | break; | ||
771 | |||
772 | } | ||
773 | if (reg_num != 0) { | ||
774 | /* H.W. Reset : ON */ | ||
775 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); | ||
776 | |||
777 | viafb_write_regx(lcd_patch_reg, reg_num); | ||
778 | |||
779 | /* H.W. Reset : OFF */ | ||
780 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); | ||
781 | |||
782 | /* Reset PLL */ | ||
783 | viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); | ||
784 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); | ||
785 | |||
786 | /* Fire! */ | ||
787 | outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc); | ||
788 | } | ||
789 | } | ||
790 | |||
791 | static void load_lcd_patch_regs(int set_hres, int set_vres, | ||
792 | int panel_id, int set_iga) | ||
793 | { | ||
794 | viafb_unlock_crt(); | ||
795 | |||
796 | /* Patch for simultaneous & Expansion */ | ||
797 | if ((set_iga == IGA1_IGA2) && | ||
798 | (viaparinfo->lvds_setting_info->display_method == | ||
799 | LCD_EXPANDSION)) { | ||
800 | switch (viaparinfo->chip_info->gfx_chip_name) { | ||
801 | case UNICHROME_CLE266: | ||
802 | case UNICHROME_K400: | ||
803 | load_lcd_k400_patch_tbl(set_hres, set_vres, panel_id); | ||
804 | break; | ||
805 | case UNICHROME_K800: | ||
806 | break; | ||
807 | case UNICHROME_PM800: | ||
808 | case UNICHROME_CN700: | ||
809 | case UNICHROME_CX700: | ||
810 | load_lcd_p880_patch_tbl(set_hres, set_vres, panel_id); | ||
811 | } | ||
812 | } | ||
813 | |||
814 | viafb_lock_crt(); | ||
815 | } | ||
816 | |||
817 | static void via_pitch_alignment_patch_lcd( | 518 | static void via_pitch_alignment_patch_lcd( |
818 | struct lvds_setting_information *plvds_setting_info, | 519 | struct lvds_setting_information *plvds_setting_info, |
819 | struct lvds_chip_information | 520 | struct lvds_chip_information |
@@ -919,7 +620,6 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, | |||
919 | int panel_hres = plvds_setting_info->lcd_panel_hres; | 620 | int panel_hres = plvds_setting_info->lcd_panel_hres; |
920 | int panel_vres = plvds_setting_info->lcd_panel_vres; | 621 | int panel_vres = plvds_setting_info->lcd_panel_vres; |
921 | u32 pll_D_N; | 622 | u32 pll_D_N; |
922 | int offset; | ||
923 | struct display_timing mode_crt_reg, panel_crt_reg; | 623 | struct display_timing mode_crt_reg, panel_crt_reg; |
924 | struct crt_mode_table *panel_crt_table = NULL; | 624 | struct crt_mode_table *panel_crt_table = NULL; |
925 | struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, | 625 | struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, |
@@ -961,52 +661,12 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, | |||
961 | } | 661 | } |
962 | } | 662 | } |
963 | 663 | ||
964 | if (set_iga == IGA1_IGA2) { | 664 | /* Fetch count for IGA2 only */ |
965 | load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg); | 665 | viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga); |
966 | /* Fill shadow registers */ | ||
967 | 666 | ||
968 | switch (plvds_setting_info->lcd_panel_id) { | 667 | if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) |
969 | case LCD_PANEL_ID0_640X480: | 668 | && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) |
970 | offset = 80; | 669 | viafb_load_FIFO_reg(set_iga, set_hres, set_vres); |
971 | break; | ||
972 | case LCD_PANEL_ID1_800X600: | ||
973 | case LCD_PANEL_IDA_800X480: | ||
974 | offset = 110; | ||
975 | break; | ||
976 | case LCD_PANEL_ID2_1024X768: | ||
977 | offset = 150; | ||
978 | break; | ||
979 | case LCD_PANEL_ID3_1280X768: | ||
980 | case LCD_PANEL_ID4_1280X1024: | ||
981 | case LCD_PANEL_ID5_1400X1050: | ||
982 | case LCD_PANEL_ID9_1280X800: | ||
983 | offset = 190; | ||
984 | break; | ||
985 | case LCD_PANEL_ID6_1600X1200: | ||
986 | offset = 250; | ||
987 | break; | ||
988 | case LCD_PANEL_ID7_1366X768: | ||
989 | case LCD_PANEL_IDB_1360X768: | ||
990 | offset = 212; | ||
991 | break; | ||
992 | default: | ||
993 | offset = 140; | ||
994 | break; | ||
995 | } | ||
996 | |||
997 | /* Offset for simultaneous */ | ||
998 | viafb_set_secondary_pitch(offset << 3); | ||
999 | DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n"); | ||
1000 | viafb_load_fetch_count_reg(set_hres, 4, IGA2); | ||
1001 | /* Fetch count for simultaneous */ | ||
1002 | } else { /* SAMM */ | ||
1003 | /* Fetch count for IGA2 only */ | ||
1004 | viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga); | ||
1005 | |||
1006 | if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) | ||
1007 | && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) | ||
1008 | viafb_load_FIFO_reg(set_iga, set_hres, set_vres); | ||
1009 | } | ||
1010 | 670 | ||
1011 | fill_lcd_format(); | 671 | fill_lcd_format(); |
1012 | 672 | ||
@@ -1023,11 +683,6 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, | |||
1023 | || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)) | 683 | || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)) |
1024 | viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); | 684 | viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); |
1025 | 685 | ||
1026 | load_lcd_patch_regs(set_hres, set_vres, | ||
1027 | plvds_setting_info->lcd_panel_id, set_iga); | ||
1028 | |||
1029 | DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n"); | ||
1030 | |||
1031 | /* Patch for non 32bit alignment mode */ | 686 | /* Patch for non 32bit alignment mode */ |
1032 | via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info); | 687 | via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info); |
1033 | } | 688 | } |
@@ -1241,8 +896,7 @@ void viafb_lcd_enable(void) | |||
1241 | viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48); | 896 | viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48); |
1242 | } | 897 | } |
1243 | 898 | ||
1244 | if ((viaparinfo->lvds_setting_info->iga_path == IGA1) | 899 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) { |
1245 | || (viaparinfo->lvds_setting_info->iga_path == IGA1_IGA2)) { | ||
1246 | /* CRT path set to IGA2 */ | 900 | /* CRT path set to IGA2 */ |
1247 | viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40); | 901 | viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40); |
1248 | /* IGA2 path disabled */ | 902 | /* IGA2 path disabled */ |
@@ -1434,210 +1088,6 @@ static struct display_timing lcd_centering_timging(struct display_timing | |||
1434 | return crt_reg; | 1088 | return crt_reg; |
1435 | } | 1089 | } |
1436 | 1090 | ||
1437 | static void load_crtc_shadow_timing(struct display_timing mode_timing, | ||
1438 | struct display_timing panel_timing) | ||
1439 | { | ||
1440 | struct io_register *reg = NULL; | ||
1441 | int i; | ||
1442 | int viafb_load_reg_Num = 0; | ||
1443 | int reg_value = 0; | ||
1444 | |||
1445 | if (viaparinfo->lvds_setting_info->display_method == LCD_EXPANDSION) { | ||
1446 | /* Expansion */ | ||
1447 | for (i = 12; i < 20; i++) { | ||
1448 | switch (i) { | ||
1449 | case H_TOTAL_SHADOW_INDEX: | ||
1450 | reg_value = | ||
1451 | IGA2_HOR_TOTAL_SHADOW_FORMULA | ||
1452 | (panel_timing.hor_total); | ||
1453 | viafb_load_reg_Num = | ||
1454 | iga2_shadow_crtc_reg.hor_total_shadow. | ||
1455 | reg_num; | ||
1456 | reg = iga2_shadow_crtc_reg.hor_total_shadow.reg; | ||
1457 | break; | ||
1458 | case H_BLANK_END_SHADOW_INDEX: | ||
1459 | reg_value = | ||
1460 | IGA2_HOR_BLANK_END_SHADOW_FORMULA | ||
1461 | (panel_timing.hor_blank_start, | ||
1462 | panel_timing.hor_blank_end); | ||
1463 | viafb_load_reg_Num = | ||
1464 | iga2_shadow_crtc_reg. | ||
1465 | hor_blank_end_shadow.reg_num; | ||
1466 | reg = | ||
1467 | iga2_shadow_crtc_reg. | ||
1468 | hor_blank_end_shadow.reg; | ||
1469 | break; | ||
1470 | case V_TOTAL_SHADOW_INDEX: | ||
1471 | reg_value = | ||
1472 | IGA2_VER_TOTAL_SHADOW_FORMULA | ||
1473 | (panel_timing.ver_total); | ||
1474 | viafb_load_reg_Num = | ||
1475 | iga2_shadow_crtc_reg.ver_total_shadow. | ||
1476 | reg_num; | ||
1477 | reg = iga2_shadow_crtc_reg.ver_total_shadow.reg; | ||
1478 | break; | ||
1479 | case V_ADDR_SHADOW_INDEX: | ||
1480 | reg_value = | ||
1481 | IGA2_VER_ADDR_SHADOW_FORMULA | ||
1482 | (panel_timing.ver_addr); | ||
1483 | viafb_load_reg_Num = | ||
1484 | iga2_shadow_crtc_reg.ver_addr_shadow. | ||
1485 | reg_num; | ||
1486 | reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg; | ||
1487 | break; | ||
1488 | case V_BLANK_SATRT_SHADOW_INDEX: | ||
1489 | reg_value = | ||
1490 | IGA2_VER_BLANK_START_SHADOW_FORMULA | ||
1491 | (panel_timing.ver_blank_start); | ||
1492 | viafb_load_reg_Num = | ||
1493 | iga2_shadow_crtc_reg. | ||
1494 | ver_blank_start_shadow.reg_num; | ||
1495 | reg = | ||
1496 | iga2_shadow_crtc_reg. | ||
1497 | ver_blank_start_shadow.reg; | ||
1498 | break; | ||
1499 | case V_BLANK_END_SHADOW_INDEX: | ||
1500 | reg_value = | ||
1501 | IGA2_VER_BLANK_END_SHADOW_FORMULA | ||
1502 | (panel_timing.ver_blank_start, | ||
1503 | panel_timing.ver_blank_end); | ||
1504 | viafb_load_reg_Num = | ||
1505 | iga2_shadow_crtc_reg. | ||
1506 | ver_blank_end_shadow.reg_num; | ||
1507 | reg = | ||
1508 | iga2_shadow_crtc_reg. | ||
1509 | ver_blank_end_shadow.reg; | ||
1510 | break; | ||
1511 | case V_SYNC_SATRT_SHADOW_INDEX: | ||
1512 | reg_value = | ||
1513 | IGA2_VER_SYNC_START_SHADOW_FORMULA | ||
1514 | (panel_timing.ver_sync_start); | ||
1515 | viafb_load_reg_Num = | ||
1516 | iga2_shadow_crtc_reg. | ||
1517 | ver_sync_start_shadow.reg_num; | ||
1518 | reg = | ||
1519 | iga2_shadow_crtc_reg. | ||
1520 | ver_sync_start_shadow.reg; | ||
1521 | break; | ||
1522 | case V_SYNC_END_SHADOW_INDEX: | ||
1523 | reg_value = | ||
1524 | IGA2_VER_SYNC_END_SHADOW_FORMULA | ||
1525 | (panel_timing.ver_sync_start, | ||
1526 | panel_timing.ver_sync_end); | ||
1527 | viafb_load_reg_Num = | ||
1528 | iga2_shadow_crtc_reg. | ||
1529 | ver_sync_end_shadow.reg_num; | ||
1530 | reg = | ||
1531 | iga2_shadow_crtc_reg. | ||
1532 | ver_sync_end_shadow.reg; | ||
1533 | break; | ||
1534 | } | ||
1535 | viafb_load_reg(reg_value, | ||
1536 | viafb_load_reg_Num, reg, VIACR); | ||
1537 | } | ||
1538 | } else { /* Centering */ | ||
1539 | for (i = 12; i < 20; i++) { | ||
1540 | switch (i) { | ||
1541 | case H_TOTAL_SHADOW_INDEX: | ||
1542 | reg_value = | ||
1543 | IGA2_HOR_TOTAL_SHADOW_FORMULA | ||
1544 | (panel_timing.hor_total); | ||
1545 | viafb_load_reg_Num = | ||
1546 | iga2_shadow_crtc_reg.hor_total_shadow. | ||
1547 | reg_num; | ||
1548 | reg = iga2_shadow_crtc_reg.hor_total_shadow.reg; | ||
1549 | break; | ||
1550 | case H_BLANK_END_SHADOW_INDEX: | ||
1551 | reg_value = | ||
1552 | IGA2_HOR_BLANK_END_SHADOW_FORMULA | ||
1553 | (panel_timing.hor_blank_start, | ||
1554 | panel_timing.hor_blank_end); | ||
1555 | viafb_load_reg_Num = | ||
1556 | iga2_shadow_crtc_reg. | ||
1557 | hor_blank_end_shadow.reg_num; | ||
1558 | reg = | ||
1559 | iga2_shadow_crtc_reg. | ||
1560 | hor_blank_end_shadow.reg; | ||
1561 | break; | ||
1562 | case V_TOTAL_SHADOW_INDEX: | ||
1563 | reg_value = | ||
1564 | IGA2_VER_TOTAL_SHADOW_FORMULA | ||
1565 | (panel_timing.ver_total); | ||
1566 | viafb_load_reg_Num = | ||
1567 | iga2_shadow_crtc_reg.ver_total_shadow. | ||
1568 | reg_num; | ||
1569 | reg = iga2_shadow_crtc_reg.ver_total_shadow.reg; | ||
1570 | break; | ||
1571 | case V_ADDR_SHADOW_INDEX: | ||
1572 | reg_value = | ||
1573 | IGA2_VER_ADDR_SHADOW_FORMULA | ||
1574 | (mode_timing.ver_addr); | ||
1575 | viafb_load_reg_Num = | ||
1576 | iga2_shadow_crtc_reg.ver_addr_shadow. | ||
1577 | reg_num; | ||
1578 | reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg; | ||
1579 | break; | ||
1580 | case V_BLANK_SATRT_SHADOW_INDEX: | ||
1581 | reg_value = | ||
1582 | IGA2_VER_BLANK_START_SHADOW_FORMULA | ||
1583 | (mode_timing.ver_blank_start); | ||
1584 | viafb_load_reg_Num = | ||
1585 | iga2_shadow_crtc_reg. | ||
1586 | ver_blank_start_shadow.reg_num; | ||
1587 | reg = | ||
1588 | iga2_shadow_crtc_reg. | ||
1589 | ver_blank_start_shadow.reg; | ||
1590 | break; | ||
1591 | case V_BLANK_END_SHADOW_INDEX: | ||
1592 | reg_value = | ||
1593 | IGA2_VER_BLANK_END_SHADOW_FORMULA | ||
1594 | (panel_timing.ver_blank_start, | ||
1595 | panel_timing.ver_blank_end); | ||
1596 | viafb_load_reg_Num = | ||
1597 | iga2_shadow_crtc_reg. | ||
1598 | ver_blank_end_shadow.reg_num; | ||
1599 | reg = | ||
1600 | iga2_shadow_crtc_reg. | ||
1601 | ver_blank_end_shadow.reg; | ||
1602 | break; | ||
1603 | case V_SYNC_SATRT_SHADOW_INDEX: | ||
1604 | reg_value = | ||
1605 | IGA2_VER_SYNC_START_SHADOW_FORMULA( | ||
1606 | (panel_timing.ver_sync_start - | ||
1607 | panel_timing.ver_blank_start) + | ||
1608 | (panel_timing.ver_addr - | ||
1609 | mode_timing.ver_addr) / 2 + | ||
1610 | mode_timing.ver_addr); | ||
1611 | viafb_load_reg_Num = | ||
1612 | iga2_shadow_crtc_reg.ver_sync_start_shadow. | ||
1613 | reg_num; | ||
1614 | reg = | ||
1615 | iga2_shadow_crtc_reg.ver_sync_start_shadow. | ||
1616 | reg; | ||
1617 | break; | ||
1618 | case V_SYNC_END_SHADOW_INDEX: | ||
1619 | reg_value = | ||
1620 | IGA2_VER_SYNC_END_SHADOW_FORMULA( | ||
1621 | (panel_timing.ver_sync_start - | ||
1622 | panel_timing.ver_blank_start) + | ||
1623 | (panel_timing.ver_addr - | ||
1624 | mode_timing.ver_addr) / 2 + | ||
1625 | mode_timing.ver_addr, | ||
1626 | panel_timing.ver_sync_end); | ||
1627 | viafb_load_reg_Num = | ||
1628 | iga2_shadow_crtc_reg.ver_sync_end_shadow. | ||
1629 | reg_num; | ||
1630 | reg = | ||
1631 | iga2_shadow_crtc_reg.ver_sync_end_shadow. | ||
1632 | reg; | ||
1633 | break; | ||
1634 | } | ||
1635 | viafb_load_reg(reg_value, | ||
1636 | viafb_load_reg_Num, reg, VIACR); | ||
1637 | } | ||
1638 | } | ||
1639 | } | ||
1640 | |||
1641 | bool viafb_lcd_get_mobile_state(bool *mobile) | 1091 | bool viafb_lcd_get_mobile_state(bool *mobile) |
1642 | { | 1092 | { |
1643 | unsigned char *romptr, *tableptr; | 1093 | unsigned char *romptr, *tableptr; |
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h index fad3d2d8053c..d55aaa7b912c 100644 --- a/drivers/video/via/share.h +++ b/drivers/video/via/share.h | |||
@@ -63,7 +63,6 @@ | |||
63 | /* Display path */ | 63 | /* Display path */ |
64 | #define IGA1 1 | 64 | #define IGA1 1 |
65 | #define IGA2 2 | 65 | #define IGA2 2 |
66 | #define IGA1_IGA2 3 | ||
67 | 66 | ||
68 | /* Define Color Depth */ | 67 | /* Define Color Depth */ |
69 | #define MODE_8BPP 1 | 68 | #define MODE_8BPP 1 |