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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-04-24 09:18:48 -0400
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2011-04-24 09:18:48 -0400
commitf33f6f0ccc5ff7415da3feb18b1ff966ed2d80d1 (patch)
tree5074abce8a7cffd69519194c8b5b627de1099dca /drivers/video/via
parent75ec72f8c53b9f981e68704432a2e425a01f79b7 (diff)
parent2946294f9aa734efc5873ea2f34131d0a8c0f89a (diff)
Merge branch 'viafb-pll' into viafb-next
Conflicts: drivers/video/via/viamode.c Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers/video/via')
-rw-r--r--drivers/video/via/Makefile2
-rw-r--r--drivers/video/via/hw.c529
-rw-r--r--drivers/video/via/hw.h14
-rw-r--r--drivers/video/via/lcd.c7
-rw-r--r--drivers/video/via/via_clock.c349
-rw-r--r--drivers/video/via/via_clock.h76
-rw-r--r--drivers/video/via/viamode.c8
7 files changed, 577 insertions, 408 deletions
diff --git a/drivers/video/via/Makefile b/drivers/video/via/Makefile
index 96f01ee2a412..5108136e8776 100644
--- a/drivers/video/via/Makefile
+++ b/drivers/video/via/Makefile
@@ -6,4 +6,4 @@ obj-$(CONFIG_FB_VIA) += viafb.o
6 6
7viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \ 7viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \
8 via_utility.o vt1636.o global.o tblDPASetting.o viamode.o \ 8 via_utility.o vt1636.o global.o tblDPASetting.o viamode.o \
9 via-core.o via-gpio.o via_modesetting.o 9 via-core.o via-gpio.o via_modesetting.o via_clock.o
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 3308f471b68a..47b13535ed2b 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -22,273 +22,82 @@
22#include <linux/via-core.h> 22#include <linux/via-core.h>
23#include <asm/olpc.h> 23#include <asm/olpc.h>
24#include "global.h" 24#include "global.h"
25 25#include "via_clock.h"
26static struct pll_config cle266_pll_config[] = { 26
27 {19, 4, 0}, 27static struct pll_limit cle266_pll_limits[] = {
28 {26, 5, 0}, 28 {19, 19, 4, 0},
29 {28, 5, 0}, 29 {26, 102, 5, 0},
30 {31, 5, 0}, 30 {53, 112, 6, 0},
31 {33, 5, 0}, 31 {41, 100, 7, 0},
32 {55, 5, 0}, 32 {83, 108, 8, 0},
33 {102, 5, 0}, 33 {87, 118, 9, 0},
34 {53, 6, 0}, 34 {95, 115, 12, 0},
35 {92, 6, 0}, 35 {108, 108, 13, 0},
36 {98, 6, 0}, 36 {83, 83, 17, 0},
37 {112, 6, 0}, 37 {67, 98, 20, 0},
38 {41, 7, 0}, 38 {121, 121, 24, 0},
39 {60, 7, 0}, 39 {99, 99, 29, 0},
40 {99, 7, 0}, 40 {33, 33, 3, 1},
41 {100, 7, 0}, 41 {15, 23, 4, 1},
42 {83, 8, 0}, 42 {37, 121, 5, 1},
43 {86, 8, 0}, 43 {82, 82, 6, 1},
44 {108, 8, 0}, 44 {31, 84, 7, 1},
45 {87, 9, 0}, 45 {83, 83, 8, 1},
46 {118, 9, 0}, 46 {76, 127, 9, 1},
47 {95, 12, 0}, 47 {33, 121, 4, 2},
48 {115, 12, 0}, 48 {91, 118, 5, 2},
49 {108, 13, 0}, 49 {83, 109, 6, 2},
50 {83, 17, 0}, 50 {90, 90, 7, 2},
51 {67, 20, 0}, 51 {93, 93, 2, 3},
52 {86, 20, 0}, 52 {53, 53, 3, 3},
53 {98, 20, 0}, 53 {73, 117, 4, 3},
54 {121, 24, 0}, 54 {101, 127, 5, 3},
55 {99, 29, 0}, 55 {99, 99, 7, 3}
56 {33, 3, 1},
57 {15, 4, 1},
58 {23, 4, 1},
59 {37, 5, 1},
60 {83, 5, 1},
61 {85, 5, 1},
62 {94, 5, 1},
63 {103, 5, 1},
64 {109, 5, 1},
65 {113, 5, 1},
66 {121, 5, 1},
67 {82, 6, 1},
68 {31, 7, 1},
69 {55, 7, 1},
70 {84, 7, 1},
71 {83, 8, 1},
72 {76, 9, 1},
73 {127, 9, 1},
74 {33, 4, 2},
75 {75, 4, 2},
76 {119, 4, 2},
77 {121, 4, 2},
78 {91, 5, 2},
79 {118, 5, 2},
80 {83, 6, 2},
81 {109, 6, 2},
82 {90, 7, 2},
83 {93, 2, 3},
84 {53, 3, 3},
85 {73, 4, 3},
86 {89, 4, 3},
87 {105, 4, 3},
88 {117, 4, 3},
89 {101, 5, 3},
90 {121, 5, 3},
91 {127, 5, 3},
92 {99, 7, 3}
93}; 56};
94 57
95static struct pll_config k800_pll_config[] = { 58static struct pll_limit k800_pll_limits[] = {
96 {22, 2, 0}, 59 {22, 22, 2, 0},
97 {28, 3, 0}, 60 {28, 28, 3, 0},
98 {81, 3, 1}, 61 {81, 112, 3, 1},
99 {85, 3, 1}, 62 {86, 166, 4, 1},
100 {98, 3, 1}, 63 {109, 153, 5, 1},
101 {112, 3, 1}, 64 {66, 116, 3, 2},
102 {86, 4, 1}, 65 {93, 137, 4, 2},
103 {166, 4, 1}, 66 {117, 208, 5, 2},
104 {109, 5, 1}, 67 {30, 30, 2, 3},
105 {113, 5, 1}, 68 {69, 125, 3, 3},
106 {121, 5, 1}, 69 {89, 161, 4, 3},
107 {131, 5, 1}, 70 {121, 208, 5, 3},
108 {143, 5, 1}, 71 {66, 66, 2, 4},
109 {153, 5, 1}, 72 {85, 85, 3, 4},
110 {66, 3, 2}, 73 {141, 161, 4, 4},
111 {68, 3, 2}, 74 {177, 177, 5, 4}
112 {95, 3, 2},
113 {106, 3, 2},
114 {116, 3, 2},
115 {93, 4, 2},
116 {119, 4, 2},
117 {121, 4, 2},
118 {133, 4, 2},
119 {137, 4, 2},
120 {117, 5, 2},
121 {118, 5, 2},
122 {120, 5, 2},
123 {124, 5, 2},
124 {132, 5, 2},
125 {137, 5, 2},
126 {141, 5, 2},
127 {166, 5, 2},
128 {170, 5, 2},
129 {191, 5, 2},
130 {206, 5, 2},
131 {208, 5, 2},
132 {30, 2, 3},
133 {69, 3, 3},
134 {82, 3, 3},
135 {83, 3, 3},
136 {109, 3, 3},
137 {114, 3, 3},
138 {125, 3, 3},
139 {89, 4, 3},
140 {103, 4, 3},
141 {117, 4, 3},
142 {126, 4, 3},
143 {150, 4, 3},
144 {161, 4, 3},
145 {121, 5, 3},
146 {127, 5, 3},
147 {131, 5, 3},
148 {134, 5, 3},
149 {148, 5, 3},
150 {169, 5, 3},
151 {172, 5, 3},
152 {182, 5, 3},
153 {195, 5, 3},
154 {196, 5, 3},
155 {208, 5, 3},
156 {66, 2, 4},
157 {85, 3, 4},
158 {141, 4, 4},
159 {146, 4, 4},
160 {161, 4, 4},
161 {177, 5, 4}
162}; 75};
163 76
164static struct pll_config cx700_pll_config[] = { 77static struct pll_limit cx700_pll_limits[] = {
165 {98, 3, 1}, 78 {98, 98, 3, 1},
166 {86, 4, 1}, 79 {86, 86, 4, 1},
167 {109, 5, 1}, 80 {109, 208, 5, 1},
168 {110, 5, 1}, 81 {68, 68, 2, 2},
169 {113, 5, 1}, 82 {95, 116, 3, 2},
170 {121, 5, 1}, 83 {93, 166, 4, 2},
171 {131, 5, 1}, 84 {110, 206, 5, 2},
172 {135, 5, 1}, 85 {174, 174, 7, 2},
173 {142, 5, 1}, 86 {82, 109, 3, 3},
174 {143, 5, 1}, 87 {117, 161, 4, 3},
175 {153, 5, 1}, 88 {112, 208, 5, 3},
176 {187, 5, 1}, 89 {141, 202, 5, 4}
177 {208, 5, 1},
178 {68, 2, 2},
179 {95, 3, 2},
180 {116, 3, 2},
181 {93, 4, 2},
182 {119, 4, 2},
183 {133, 4, 2},
184 {137, 4, 2},
185 {151, 4, 2},
186 {166, 4, 2},
187 {110, 5, 2},
188 {112, 5, 2},
189 {117, 5, 2},
190 {118, 5, 2},
191 {120, 5, 2},
192 {132, 5, 2},
193 {137, 5, 2},
194 {141, 5, 2},
195 {151, 5, 2},
196 {166, 5, 2},
197 {175, 5, 2},
198 {191, 5, 2},
199 {206, 5, 2},
200 {174, 7, 2},
201 {82, 3, 3},
202 {109, 3, 3},
203 {117, 4, 3},
204 {150, 4, 3},
205 {161, 4, 3},
206 {112, 5, 3},
207 {115, 5, 3},
208 {121, 5, 3},
209 {127, 5, 3},
210 {129, 5, 3},
211 {131, 5, 3},
212 {134, 5, 3},
213 {138, 5, 3},
214 {148, 5, 3},
215 {157, 5, 3},
216 {169, 5, 3},
217 {172, 5, 3},
218 {190, 5, 3},
219 {195, 5, 3},
220 {196, 5, 3},
221 {208, 5, 3},
222 {141, 5, 4},
223 {150, 5, 4},
224 {166, 5, 4},
225 {176, 5, 4},
226 {177, 5, 4},
227 {183, 5, 4},
228 {202, 5, 4}
229}; 90};
230 91
231static struct pll_config vx855_pll_config[] = { 92static struct pll_limit vx855_pll_limits[] = {
232 {86, 4, 1}, 93 {86, 86, 4, 1},
233 {108, 5, 1}, 94 {108, 208, 5, 1},
234 {110, 5, 1}, 95 {110, 208, 5, 2},
235 {113, 5, 1}, 96 {83, 112, 3, 3},
236 {121, 5, 1}, 97 {103, 161, 4, 3},
237 {131, 5, 1}, 98 {112, 209, 5, 3},
238 {135, 5, 1}, 99 {142, 161, 4, 4},
239 {142, 5, 1}, 100 {141, 176, 5, 4}
240 {143, 5, 1},
241 {153, 5, 1},
242 {164, 5, 1},
243 {187, 5, 1},
244 {208, 5, 1},
245 {110, 5, 2},
246 {112, 5, 2},
247 {117, 5, 2},
248 {118, 5, 2},
249 {124, 5, 2},
250 {132, 5, 2},
251 {137, 5, 2},
252 {141, 5, 2},
253 {149, 5, 2},
254 {151, 5, 2},
255 {159, 5, 2},
256 {166, 5, 2},
257 {167, 5, 2},
258 {172, 5, 2},
259 {189, 5, 2},
260 {191, 5, 2},
261 {194, 5, 2},
262 {206, 5, 2},
263 {208, 5, 2},
264 {83, 3, 3},
265 {88, 3, 3},
266 {109, 3, 3},
267 {112, 3, 3},
268 {103, 4, 3},
269 {105, 4, 3},
270 {161, 4, 3},
271 {112, 5, 3},
272 {115, 5, 3},
273 {121, 5, 3},
274 {127, 5, 3},
275 {134, 5, 3},
276 {137, 5, 3},
277 {148, 5, 3},
278 {157, 5, 3},
279 {169, 5, 3},
280 {172, 5, 3},
281 {182, 5, 3},
282 {191, 5, 3},
283 {195, 5, 3},
284 {209, 5, 3},
285 {142, 4, 4},
286 {146, 4, 4},
287 {161, 4, 4},
288 {141, 5, 4},
289 {150, 5, 4},
290 {165, 5, 4},
291 {176, 5, 4}
292}; 101};
293 102
294/* according to VIA Technologies these values are based on experiment */ 103/* according to VIA Technologies these values are based on experiment */
@@ -713,6 +522,9 @@ static struct via_device_mapping device_mapping[] = {
713 {VIA_LVDS2, "LVDS2"} 522 {VIA_LVDS2, "LVDS2"}
714}; 523};
715 524
525/* structure with function pointers to support clock control */
526static struct via_clock clock;
527
716static void load_fix_bit_crtc_reg(void); 528static void load_fix_bit_crtc_reg(void);
717static void __devinit init_gfx_chip_info(int chip_type); 529static void __devinit init_gfx_chip_info(int chip_type);
718static void __devinit init_tmds_chip_info(void); 530static void __devinit init_tmds_chip_info(void);
@@ -1634,69 +1446,54 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1634 1446
1635} 1447}
1636 1448
1637static u32 cle266_encode_pll(struct pll_config pll) 1449static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
1638{
1639 return (pll.multiplier << 8)
1640 | (pll.rshift << 6)
1641 | pll.divisor;
1642}
1643
1644static u32 k800_encode_pll(struct pll_config pll)
1645{
1646 return ((pll.divisor - 2) << 16)
1647 | (pll.rshift << 10)
1648 | (pll.multiplier - 2);
1649}
1650
1651static u32 vx855_encode_pll(struct pll_config pll)
1652{
1653 return (pll.divisor << 16)
1654 | (pll.rshift << 10)
1655 | pll.multiplier;
1656}
1657
1658static inline u32 get_pll_internal_frequency(u32 ref_freq,
1659 struct pll_config pll)
1660{
1661 return ref_freq / pll.divisor * pll.multiplier;
1662}
1663
1664static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)
1665{
1666 return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;
1667}
1668
1669static struct pll_config get_pll_config(struct pll_config *config, int size,
1670 int clk) 1450 int clk)
1671{ 1451{
1672 struct pll_config best = config[0]; 1452 struct via_pll_config cur, up, down, best = {0, 1, 0};
1673 const u32 f0 = 14318180; /* X1 frequency */ 1453 const u32 f0 = 14318180; /* X1 frequency */
1674 int i; 1454 int i, f;
1675 1455
1676 for (i = 1; i < size; i++) { 1456 for (i = 0; i < size; i++) {
1677 if (abs(get_pll_output_frequency(f0, config[i]) - clk) 1457 cur.rshift = limits[i].rshift;
1678 < abs(get_pll_output_frequency(f0, best) - clk)) 1458 cur.divisor = limits[i].divisor;
1679 best = config[i]; 1459 cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
1460 f = abs(get_pll_output_frequency(f0, cur) - clk);
1461 up = down = cur;
1462 up.multiplier++;
1463 down.multiplier--;
1464 if (abs(get_pll_output_frequency(f0, up) - clk) < f)
1465 cur = up;
1466 else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
1467 cur = down;
1468
1469 if (cur.multiplier < limits[i].multiplier_min)
1470 cur.multiplier = limits[i].multiplier_min;
1471 else if (cur.multiplier > limits[i].multiplier_max)
1472 cur.multiplier = limits[i].multiplier_max;
1473
1474 f = abs(get_pll_output_frequency(f0, cur) - clk);
1475 if (f < abs(get_pll_output_frequency(f0, best) - clk))
1476 best = cur;
1680 } 1477 }
1681 1478
1682 return best; 1479 return best;
1683} 1480}
1684 1481
1685u32 viafb_get_clk_value(int clk) 1482static struct via_pll_config get_best_pll_config(int clk)
1686{ 1483{
1687 u32 value = 0; 1484 struct via_pll_config config;
1688 1485
1689 switch (viaparinfo->chip_info->gfx_chip_name) { 1486 switch (viaparinfo->chip_info->gfx_chip_name) {
1690 case UNICHROME_CLE266: 1487 case UNICHROME_CLE266:
1691 case UNICHROME_K400: 1488 case UNICHROME_K400:
1692 value = cle266_encode_pll(get_pll_config(cle266_pll_config, 1489 config = get_pll_config(cle266_pll_limits,
1693 ARRAY_SIZE(cle266_pll_config), clk)); 1490 ARRAY_SIZE(cle266_pll_limits), clk);
1694 break; 1491 break;
1695 case UNICHROME_K800: 1492 case UNICHROME_K800:
1696 case UNICHROME_PM800: 1493 case UNICHROME_PM800:
1697 case UNICHROME_CN700: 1494 case UNICHROME_CN700:
1698 value = k800_encode_pll(get_pll_config(k800_pll_config, 1495 config = get_pll_config(k800_pll_limits,
1699 ARRAY_SIZE(k800_pll_config), clk)); 1496 ARRAY_SIZE(k800_pll_limits), clk);
1700 break; 1497 break;
1701 case UNICHROME_CX700: 1498 case UNICHROME_CX700:
1702 case UNICHROME_CN750: 1499 case UNICHROME_CN750:
@@ -1704,92 +1501,28 @@ u32 viafb_get_clk_value(int clk)
1704 case UNICHROME_P4M890: 1501 case UNICHROME_P4M890:
1705 case UNICHROME_P4M900: 1502 case UNICHROME_P4M900:
1706 case UNICHROME_VX800: 1503 case UNICHROME_VX800:
1707 value = k800_encode_pll(get_pll_config(cx700_pll_config, 1504 config = get_pll_config(cx700_pll_limits,
1708 ARRAY_SIZE(cx700_pll_config), clk)); 1505 ARRAY_SIZE(cx700_pll_limits), clk);
1709 break; 1506 break;
1710 case UNICHROME_VX855: 1507 case UNICHROME_VX855:
1711 case UNICHROME_VX900: 1508 case UNICHROME_VX900:
1712 value = vx855_encode_pll(get_pll_config(vx855_pll_config, 1509 config = get_pll_config(vx855_pll_limits,
1713 ARRAY_SIZE(vx855_pll_config), clk)); 1510 ARRAY_SIZE(vx855_pll_limits), clk);
1714 break; 1511 break;
1715 } 1512 }
1716 1513
1717 return value; 1514 return config;
1718} 1515}
1719 1516
1720/* Set VCLK*/ 1517/* Set VCLK*/
1721void viafb_set_vclock(u32 clk, int set_iga) 1518void viafb_set_vclock(u32 clk, int set_iga)
1722{ 1519{
1723 /* H.W. Reset : ON */ 1520 struct via_pll_config config = get_best_pll_config(clk);
1724 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1725
1726 if (set_iga == IGA1) {
1727 /* Change D,N FOR VCLK */
1728 switch (viaparinfo->chip_info->gfx_chip_name) {
1729 case UNICHROME_CLE266:
1730 case UNICHROME_K400:
1731 via_write_reg(VIASR, SR46, (clk & 0x00FF));
1732 via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1733 break;
1734
1735 case UNICHROME_K800:
1736 case UNICHROME_PM800:
1737 case UNICHROME_CN700:
1738 case UNICHROME_CX700:
1739 case UNICHROME_CN750:
1740 case UNICHROME_K8M890:
1741 case UNICHROME_P4M890:
1742 case UNICHROME_P4M900:
1743 case UNICHROME_VX800:
1744 case UNICHROME_VX855:
1745 case UNICHROME_VX900:
1746 via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1747 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1748 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1749 break;
1750 }
1751 }
1752
1753 if (set_iga == IGA2) {
1754 /* Change D,N FOR LCK */
1755 switch (viaparinfo->chip_info->gfx_chip_name) {
1756 case UNICHROME_CLE266:
1757 case UNICHROME_K400:
1758 via_write_reg(VIASR, SR44, (clk & 0x00FF));
1759 via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1760 break;
1761 1521
1762 case UNICHROME_K800: 1522 if (set_iga == IGA1)
1763 case UNICHROME_PM800: 1523 clock.set_primary_pll(config);
1764 case UNICHROME_CN700: 1524 if (set_iga == IGA2)
1765 case UNICHROME_CX700: 1525 clock.set_secondary_pll(config);
1766 case UNICHROME_CN750:
1767 case UNICHROME_K8M890:
1768 case UNICHROME_P4M890:
1769 case UNICHROME_P4M900:
1770 case UNICHROME_VX800:
1771 case UNICHROME_VX855:
1772 case UNICHROME_VX900:
1773 via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1774 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1775 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1776 break;
1777 }
1778 }
1779
1780 /* H.W. Reset : OFF */
1781 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1782
1783 /* Reset PLL */
1784 if (set_iga == IGA1) {
1785 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1786 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1787 }
1788
1789 if (set_iga == IGA2) {
1790 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1791 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1792 }
1793 1526
1794 /* Fire! */ 1527 /* Fire! */
1795 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ 1528 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
@@ -2035,7 +1768,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2035 int i; 1768 int i;
2036 int index = 0; 1769 int index = 0;
2037 int h_addr, v_addr; 1770 int h_addr, v_addr;
2038 u32 pll_D_N, clock, refresh = viafb_refresh; 1771 u32 clock, refresh = viafb_refresh;
2039 1772
2040 if (viafb_SAMM_ON && set_iga == IGA2) 1773 if (viafb_SAMM_ON && set_iga == IGA2)
2041 refresh = viafb_refresh1; 1774 refresh = viafb_refresh1;
@@ -2089,14 +1822,13 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2089 1822
2090 clock = crt_reg.hor_total * crt_reg.ver_total 1823 clock = crt_reg.hor_total * crt_reg.ver_total
2091 * crt_table[index].refresh_rate; 1824 * crt_table[index].refresh_rate;
2092 pll_D_N = viafb_get_clk_value(clock); 1825 viafb_set_vclock(clock, set_iga);
2093 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
2094 viafb_set_vclock(pll_D_N, set_iga);
2095 1826
2096} 1827}
2097 1828
2098void __devinit viafb_init_chip_info(int chip_type) 1829void __devinit viafb_init_chip_info(int chip_type)
2099{ 1830{
1831 via_clock_init(&clock, chip_type);
2100 init_gfx_chip_info(chip_type); 1832 init_gfx_chip_info(chip_type);
2101 init_tmds_chip_info(); 1833 init_tmds_chip_info();
2102 init_lvds_chip_info(); 1834 init_lvds_chip_info();
@@ -2584,6 +2316,33 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2584 get_sync(viafbinfo1)); 2316 get_sync(viafbinfo1));
2585 } 2317 }
2586 2318
2319 clock.set_engine_pll_state(VIA_STATE_ON);
2320 clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
2321 clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
2322
2323#ifdef CONFIG_FB_VIA_X_COMPATIBILITY
2324 clock.set_primary_pll_state(VIA_STATE_ON);
2325 clock.set_primary_clock_state(VIA_STATE_ON);
2326 clock.set_secondary_pll_state(VIA_STATE_ON);
2327 clock.set_secondary_clock_state(VIA_STATE_ON);
2328#else
2329 if (viaparinfo->shared->iga1_devices) {
2330 clock.set_primary_pll_state(VIA_STATE_ON);
2331 clock.set_primary_clock_state(VIA_STATE_ON);
2332 } else {
2333 clock.set_primary_pll_state(VIA_STATE_OFF);
2334 clock.set_primary_clock_state(VIA_STATE_OFF);
2335 }
2336
2337 if (viaparinfo->shared->iga2_devices) {
2338 clock.set_secondary_pll_state(VIA_STATE_ON);
2339 clock.set_secondary_clock_state(VIA_STATE_ON);
2340 } else {
2341 clock.set_secondary_pll_state(VIA_STATE_OFF);
2342 clock.set_secondary_clock_state(VIA_STATE_OFF);
2343 }
2344#endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/
2345
2587 via_set_state(devices, VIA_STATE_ON); 2346 via_set_state(devices, VIA_STATE_ON);
2588 device_screen_on(); 2347 device_screen_on();
2589 return 1; 2348 return 1;
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 090d167863a4..c7239eb83bae 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -732,20 +732,13 @@ struct _lcd_scaling_factor {
732 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor; 732 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
733}; 733};
734 734
735struct pll_config { 735struct pll_limit {
736 u16 multiplier; 736 u16 multiplier_min;
737 u16 multiplier_max;
737 u8 divisor; 738 u8 divisor;
738 u8 rshift; 739 u8 rshift;
739}; 740};
740 741
741struct pll_map {
742 u32 clk;
743 struct pll_config cle266_pll;
744 struct pll_config k800_pll;
745 struct pll_config cx700_pll;
746 struct pll_config vx855_pll;
747};
748
749struct rgbLUT { 742struct rgbLUT {
750 u8 red; 743 u8 red;
751 u8 green; 744 u8 green;
@@ -935,7 +928,6 @@ void viafb_lock_crt(void);
935void viafb_unlock_crt(void); 928void viafb_unlock_crt(void);
936void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga); 929void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
937void viafb_write_regx(struct io_reg RegTable[], int ItemNum); 930void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
938u32 viafb_get_clk_value(int clk);
939void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active); 931void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
940void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ 932void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
941 *p_gfx_dpa_setting); 933 *p_gfx_dpa_setting);
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index 6984046c6eed..6e06981d638b 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -558,7 +558,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
558 int set_vres = plvds_setting_info->v_active; 558 int set_vres = plvds_setting_info->v_active;
559 int panel_hres = plvds_setting_info->lcd_panel_hres; 559 int panel_hres = plvds_setting_info->lcd_panel_hres;
560 int panel_vres = plvds_setting_info->lcd_panel_vres; 560 int panel_vres = plvds_setting_info->lcd_panel_vres;
561 u32 pll_D_N, clock; 561 u32 clock;
562 struct display_timing mode_crt_reg, panel_crt_reg; 562 struct display_timing mode_crt_reg, panel_crt_reg;
563 struct crt_mode_table *panel_crt_table = NULL; 563 struct crt_mode_table *panel_crt_table = NULL;
564 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, 564 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
@@ -609,10 +609,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
609 viafb_load_FIFO_reg(set_iga, set_hres, set_vres); 609 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
610 610
611 fill_lcd_format(); 611 fill_lcd_format();
612 612 viafb_set_vclock(clock, set_iga);
613 pll_D_N = viafb_get_clk_value(clock);
614 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
615 viafb_set_vclock(pll_D_N, set_iga);
616 lcd_patch_skew(plvds_setting_info, plvds_chip_info); 613 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
617 614
618 /* If K8M800, enable LCD Prefetch Mode. */ 615 /* If K8M800, enable LCD Prefetch Mode. */
diff --git a/drivers/video/via/via_clock.c b/drivers/video/via/via_clock.c
new file mode 100644
index 000000000000..af8f26b643c1
--- /dev/null
+++ b/drivers/video/via/via_clock.c
@@ -0,0 +1,349 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4 * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
13 * the implied warranty of MERCHANTABILITY or FITNESS FOR
14 * A PARTICULAR PURPOSE.See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22/*
23 * clock and PLL management functions
24 */
25
26#include <linux/kernel.h>
27#include <linux/via-core.h>
28#include "via_clock.h"
29#include "global.h"
30#include "debug.h"
31
32const char *via_slap = "Please slap VIA Technologies to motivate them "
33 "releasing full documentation for your platform!\n";
34
35static inline u32 cle266_encode_pll(struct via_pll_config pll)
36{
37 return (pll.multiplier << 8)
38 | (pll.rshift << 6)
39 | pll.divisor;
40}
41
42static inline u32 k800_encode_pll(struct via_pll_config pll)
43{
44 return ((pll.divisor - 2) << 16)
45 | (pll.rshift << 10)
46 | (pll.multiplier - 2);
47}
48
49static inline u32 vx855_encode_pll(struct via_pll_config pll)
50{
51 return (pll.divisor << 16)
52 | (pll.rshift << 10)
53 | pll.multiplier;
54}
55
56static inline void cle266_set_primary_pll_encoded(u32 data)
57{
58 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
59 via_write_reg(VIASR, 0x46, data & 0xFF);
60 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
61 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
62}
63
64static inline void k800_set_primary_pll_encoded(u32 data)
65{
66 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
67 via_write_reg(VIASR, 0x44, data & 0xFF);
68 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
69 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
70 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
71}
72
73static inline void cle266_set_secondary_pll_encoded(u32 data)
74{
75 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
76 via_write_reg(VIASR, 0x44, data & 0xFF);
77 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
78 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
79}
80
81static inline void k800_set_secondary_pll_encoded(u32 data)
82{
83 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
84 via_write_reg(VIASR, 0x4A, data & 0xFF);
85 via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
86 via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
87 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
88}
89
90static inline void set_engine_pll_encoded(u32 data)
91{
92 via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */
93 via_write_reg(VIASR, 0x47, data & 0xFF);
94 via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF);
95 via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF);
96 via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */
97}
98
99static void cle266_set_primary_pll(struct via_pll_config config)
100{
101 cle266_set_primary_pll_encoded(cle266_encode_pll(config));
102}
103
104static void k800_set_primary_pll(struct via_pll_config config)
105{
106 k800_set_primary_pll_encoded(k800_encode_pll(config));
107}
108
109static void vx855_set_primary_pll(struct via_pll_config config)
110{
111 k800_set_primary_pll_encoded(vx855_encode_pll(config));
112}
113
114static void cle266_set_secondary_pll(struct via_pll_config config)
115{
116 cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
117}
118
119static void k800_set_secondary_pll(struct via_pll_config config)
120{
121 k800_set_secondary_pll_encoded(k800_encode_pll(config));
122}
123
124static void vx855_set_secondary_pll(struct via_pll_config config)
125{
126 k800_set_secondary_pll_encoded(vx855_encode_pll(config));
127}
128
129static void k800_set_engine_pll(struct via_pll_config config)
130{
131 set_engine_pll_encoded(k800_encode_pll(config));
132}
133
134static void vx855_set_engine_pll(struct via_pll_config config)
135{
136 set_engine_pll_encoded(vx855_encode_pll(config));
137}
138
139static void set_primary_pll_state(u8 state)
140{
141 u8 value;
142
143 switch (state) {
144 case VIA_STATE_ON:
145 value = 0x20;
146 break;
147 case VIA_STATE_OFF:
148 value = 0x00;
149 break;
150 default:
151 return;
152 }
153
154 via_write_reg_mask(VIASR, 0x2D, value, 0x30);
155}
156
157static void set_secondary_pll_state(u8 state)
158{
159 u8 value;
160
161 switch (state) {
162 case VIA_STATE_ON:
163 value = 0x08;
164 break;
165 case VIA_STATE_OFF:
166 value = 0x00;
167 break;
168 default:
169 return;
170 }
171
172 via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
173}
174
175static void set_engine_pll_state(u8 state)
176{
177 u8 value;
178
179 switch (state) {
180 case VIA_STATE_ON:
181 value = 0x02;
182 break;
183 case VIA_STATE_OFF:
184 value = 0x00;
185 break;
186 default:
187 return;
188 }
189
190 via_write_reg_mask(VIASR, 0x2D, value, 0x03);
191}
192
193static void set_primary_clock_state(u8 state)
194{
195 u8 value;
196
197 switch (state) {
198 case VIA_STATE_ON:
199 value = 0x20;
200 break;
201 case VIA_STATE_OFF:
202 value = 0x00;
203 break;
204 default:
205 return;
206 }
207
208 via_write_reg_mask(VIASR, 0x1B, value, 0x30);
209}
210
211static void set_secondary_clock_state(u8 state)
212{
213 u8 value;
214
215 switch (state) {
216 case VIA_STATE_ON:
217 value = 0x80;
218 break;
219 case VIA_STATE_OFF:
220 value = 0x00;
221 break;
222 default:
223 return;
224 }
225
226 via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
227}
228
229static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
230{
231 u8 data = 0;
232
233 switch (source) {
234 case VIA_CLKSRC_X1:
235 data = 0x00;
236 break;
237 case VIA_CLKSRC_TVX1:
238 data = 0x02;
239 break;
240 case VIA_CLKSRC_TVPLL:
241 data = 0x04; /* 0x06 should be the same */
242 break;
243 case VIA_CLKSRC_DVP1TVCLKR:
244 data = 0x0A;
245 break;
246 case VIA_CLKSRC_CAP0:
247 data = 0xC;
248 break;
249 case VIA_CLKSRC_CAP1:
250 data = 0x0E;
251 break;
252 }
253
254 if (!use_pll)
255 data |= 1;
256
257 return data;
258}
259
260static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
261{
262 u8 data = set_clock_source_common(source, use_pll) << 4;
263 via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
264}
265
266static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
267{
268 u8 data = set_clock_source_common(source, use_pll);
269 via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
270}
271
272static void dummy_set_clock_state(u8 state)
273{
274 printk(KERN_INFO "Using undocumented set clock state.\n%s", via_slap);
275}
276
277static void dummy_set_clock_source(enum via_clksrc source, bool use_pll)
278{
279 printk(KERN_INFO "Using undocumented set clock source.\n%s", via_slap);
280}
281
282static void dummy_set_pll_state(u8 state)
283{
284 printk(KERN_INFO "Using undocumented set PLL state.\n%s", via_slap);
285}
286
287static void dummy_set_pll(struct via_pll_config config)
288{
289 printk(KERN_INFO "Using undocumented set PLL.\n%s", via_slap);
290}
291
292void via_clock_init(struct via_clock *clock, int gfx_chip)
293{
294 switch (gfx_chip) {
295 case UNICHROME_CLE266:
296 case UNICHROME_K400:
297 clock->set_primary_clock_state = dummy_set_clock_state;
298 clock->set_primary_clock_source = dummy_set_clock_source;
299 clock->set_primary_pll_state = dummy_set_pll_state;
300 clock->set_primary_pll = cle266_set_primary_pll;
301
302 clock->set_secondary_clock_state = dummy_set_clock_state;
303 clock->set_secondary_clock_source = dummy_set_clock_source;
304 clock->set_secondary_pll_state = dummy_set_pll_state;
305 clock->set_secondary_pll = cle266_set_secondary_pll;
306
307 clock->set_engine_pll_state = dummy_set_pll_state;
308 clock->set_engine_pll = dummy_set_pll;
309 break;
310 case UNICHROME_K800:
311 case UNICHROME_PM800:
312 case UNICHROME_CN700:
313 case UNICHROME_CX700:
314 case UNICHROME_CN750:
315 case UNICHROME_K8M890:
316 case UNICHROME_P4M890:
317 case UNICHROME_P4M900:
318 case UNICHROME_VX800:
319 clock->set_primary_clock_state = set_primary_clock_state;
320 clock->set_primary_clock_source = set_primary_clock_source;
321 clock->set_primary_pll_state = set_primary_pll_state;
322 clock->set_primary_pll = k800_set_primary_pll;
323
324 clock->set_secondary_clock_state = set_secondary_clock_state;
325 clock->set_secondary_clock_source = set_secondary_clock_source;
326 clock->set_secondary_pll_state = set_secondary_pll_state;
327 clock->set_secondary_pll = k800_set_secondary_pll;
328
329 clock->set_engine_pll_state = set_engine_pll_state;
330 clock->set_engine_pll = k800_set_engine_pll;
331 break;
332 case UNICHROME_VX855:
333 case UNICHROME_VX900:
334 clock->set_primary_clock_state = set_primary_clock_state;
335 clock->set_primary_clock_source = set_primary_clock_source;
336 clock->set_primary_pll_state = set_primary_pll_state;
337 clock->set_primary_pll = vx855_set_primary_pll;
338
339 clock->set_secondary_clock_state = set_secondary_clock_state;
340 clock->set_secondary_clock_source = set_secondary_clock_source;
341 clock->set_secondary_pll_state = set_secondary_pll_state;
342 clock->set_secondary_pll = vx855_set_secondary_pll;
343
344 clock->set_engine_pll_state = set_engine_pll_state;
345 clock->set_engine_pll = vx855_set_engine_pll;
346 break;
347
348 }
349}
diff --git a/drivers/video/via/via_clock.h b/drivers/video/via/via_clock.h
new file mode 100644
index 000000000000..88714ae0d157
--- /dev/null
+++ b/drivers/video/via/via_clock.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4 * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
13 * the implied warranty of MERCHANTABILITY or FITNESS FOR
14 * A PARTICULAR PURPOSE.See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22/*
23 * clock and PLL management functions
24 */
25
26#ifndef __VIA_CLOCK_H__
27#define __VIA_CLOCK_H__
28
29#include <linux/types.h>
30
31enum via_clksrc {
32 VIA_CLKSRC_X1 = 0,
33 VIA_CLKSRC_TVX1,
34 VIA_CLKSRC_TVPLL,
35 VIA_CLKSRC_DVP1TVCLKR,
36 VIA_CLKSRC_CAP0,
37 VIA_CLKSRC_CAP1,
38};
39
40struct via_pll_config {
41 u16 multiplier;
42 u8 divisor;
43 u8 rshift;
44};
45
46struct via_clock {
47 void (*set_primary_clock_state)(u8 state);
48 void (*set_primary_clock_source)(enum via_clksrc src, bool use_pll);
49 void (*set_primary_pll_state)(u8 state);
50 void (*set_primary_pll)(struct via_pll_config config);
51
52 void (*set_secondary_clock_state)(u8 state);
53 void (*set_secondary_clock_source)(enum via_clksrc src, bool use_pll);
54 void (*set_secondary_pll_state)(u8 state);
55 void (*set_secondary_pll)(struct via_pll_config config);
56
57 void (*set_engine_pll_state)(u8 state);
58 void (*set_engine_pll)(struct via_pll_config config);
59};
60
61
62static inline u32 get_pll_internal_frequency(u32 ref_freq,
63 struct via_pll_config pll)
64{
65 return ref_freq / pll.divisor * pll.multiplier;
66}
67
68static inline u32 get_pll_output_frequency(u32 ref_freq,
69 struct via_pll_config pll)
70{
71 return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift;
72}
73
74void via_clock_init(struct via_clock *clock, int gfx_chip);
75
76#endif /* __VIA_CLOCK_H__ */
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
index f84c9b03b6bb..50de07f27a6c 100644
--- a/drivers/video/via/viamode.c
+++ b/drivers/video/via/viamode.c
@@ -37,7 +37,6 @@ struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
37{VIACR, CR69, 0xFF, 0x00}, 37{VIACR, CR69, 0xFF, 0x00},
38{VIACR, CR6A, 0xFF, 0x40}, 38{VIACR, CR6A, 0xFF, 0x40},
39{VIACR, CR6B, 0xFF, 0x00}, 39{VIACR, CR6B, 0xFF, 0x00},
40{VIACR, CR6C, 0xFF, 0x00},
41{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 40{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
42{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 41{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
43{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 42{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
@@ -83,7 +82,6 @@ struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
83{VIACR, CR69, 0xFF, 0x00}, 82{VIACR, CR69, 0xFF, 0x00},
84{VIACR, CR6A, 0xFD, 0x40}, 83{VIACR, CR6A, 0xFD, 0x40},
85{VIACR, CR6B, 0xFF, 0x00}, 84{VIACR, CR6B, 0xFF, 0x00},
86{VIACR, CR6C, 0xFF, 0x00},
87{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */ 85{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */
88{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */ 86{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
89{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */ 87{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
@@ -153,7 +151,7 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
153{VIASR, SR1B, 0xFF, 0xF0}, 151{VIASR, SR1B, 0xFF, 0xF0},
154{VIASR, SR1E, 0xFF, 0x01}, 152{VIASR, SR1E, 0xFF, 0x01},
155{VIASR, SR2A, 0xFF, 0x00}, 153{VIASR, SR2A, 0xFF, 0x00},
156{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */ 154{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
157{VIACR, CR32, 0xFF, 0x00}, 155{VIACR, CR32, 0xFF, 0x00},
158{VIACR, CR33, 0xFF, 0x00}, 156{VIACR, CR33, 0xFF, 0x00},
159{VIACR, CR35, 0xFF, 0x00}, 157{VIACR, CR35, 0xFF, 0x00},
@@ -162,7 +160,6 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
162{VIACR, CR69, 0xFF, 0x00}, 160{VIACR, CR69, 0xFF, 0x00},
163{VIACR, CR6A, 0xFF, 0x40}, 161{VIACR, CR6A, 0xFF, 0x40},
164{VIACR, CR6B, 0xFF, 0x00}, 162{VIACR, CR6B, 0xFF, 0x00},
165{VIACR, CR6C, 0xFF, 0x00},
166{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 163{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
167{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 164{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
168{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 165{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
@@ -192,7 +189,7 @@ struct io_reg VX855_ModeXregs[] = {
192{VIASR, SR2A, 0xF0, 0x00}, 189{VIASR, SR2A, 0xF0, 0x00},
193{VIASR, SR58, 0xFF, 0x00}, 190{VIASR, SR58, 0xFF, 0x00},
194{VIASR, SR59, 0xFF, 0x00}, 191{VIASR, SR59, 0xFF, 0x00},
195{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */ 192{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
196{VIACR, CR32, 0xFF, 0x00}, 193{VIACR, CR32, 0xFF, 0x00},
197{VIACR, CR33, 0x7F, 0x00}, 194{VIACR, CR33, 0x7F, 0x00},
198{VIACR, CR35, 0xFF, 0x00}, 195{VIACR, CR35, 0xFF, 0x00},
@@ -200,7 +197,6 @@ struct io_reg VX855_ModeXregs[] = {
200{VIACR, CR69, 0xFF, 0x00}, 197{VIACR, CR69, 0xFF, 0x00},
201{VIACR, CR6A, 0xFD, 0x60}, 198{VIACR, CR6A, 0xFD, 0x60},
202{VIACR, CR6B, 0xFF, 0x00}, 199{VIACR, CR6B, 0xFF, 0x00},
203{VIACR, CR6C, 0xFF, 0x00},
204{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 200{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
205{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 201{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
206{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 202{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 23:35:30 -0500