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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2012-02-17 02:55:06 -0500
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2012-03-08 13:41:35 -0500
commit9864ca20c50c2fcaba63767a336e16c88b46d7ad (patch)
tree9fa6b91a21415cd5dc5abbb1933555ae365ede5d /drivers/video/via
parent91dc1be8f698eb016343d534159a919678e3889c (diff)
viafb: modetable conversion
This patch converts the modetables used in viafb to - remove the strange thing that sync_end and blanking_end contained the length and not the absolute value - remove hundreds of useless defines - use fb_videomode and not our own definition so modes defined in the subsystem and received via EDID are compatible with ours As the modes are now stored in a flat structure and no longer in a tree like thing the lookup time was increased but as it is a rare event anyway it shouldn't matter. Otherwise the behaviour should be the same as before. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers/video/via')
-rw-r--r--drivers/video/via/dvi.c2
-rw-r--r--drivers/video/via/hw.c41
-rw-r--r--drivers/video/via/hw.h4
-rw-r--r--drivers/video/via/lcd.c53
-rw-r--r--drivers/video/via/share.h331
-rw-r--r--drivers/video/via/viamode.c713
-rw-r--r--drivers/video/via/viamode.h11
7 files changed, 120 insertions, 1035 deletions
diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c
index 3312c81e861c..6be72f0ba21d 100644
--- a/drivers/video/via/dvi.c
+++ b/drivers/video/via/dvi.c
@@ -176,7 +176,7 @@ void viafb_dvi_set_mode(const struct fb_var_screeninfo *var,
176 u16 cxres, u16 cyres, int iga) 176 u16 cxres, u16 cyres, int iga)
177{ 177{
178 struct fb_var_screeninfo dvi_var = *var; 178 struct fb_var_screeninfo dvi_var = *var;
179 struct crt_mode_table *rb_mode; 179 const struct fb_videomode *rb_mode;
180 int maxPixelClock; 180 int maxPixelClock;
181 181
182 maxPixelClock = viaparinfo->shared->tmds_setting_info.max_pixel_clock; 182 maxPixelClock = viaparinfo->shared->tmds_setting_info.max_pixel_clock;
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index da80d202f52a..1372ef4b9798 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1467,7 +1467,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
1467 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ 1467 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1468} 1468}
1469 1469
1470static struct display_timing var_to_timing(const struct fb_var_screeninfo *var, u16 cxres, u16 cyres) 1470struct display_timing var_to_timing(const struct fb_var_screeninfo *var,
1471 u16 cxres, u16 cyres)
1471{ 1472{
1472 struct display_timing timing; 1473 struct display_timing timing;
1473 u16 dx = (var->xres - cxres) / 2, dy = (var->yres - cyres) / 2; 1474 u16 dx = (var->xres - cxres) / 2, dy = (var->yres - cyres) / 2;
@@ -2007,20 +2008,20 @@ int viafb_setmode(void)
2007 2008
2008int viafb_get_refresh(int hres, int vres, u32 long_refresh) 2009int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2009{ 2010{
2010 struct crt_mode_table *best; 2011 const struct fb_videomode *best;
2011 2012
2012 best = viafb_get_best_mode(hres, vres, long_refresh); 2013 best = viafb_get_best_mode(hres, vres, long_refresh);
2013 if (!best) 2014 if (!best)
2014 return 60; 2015 return 60;
2015 2016
2016 if (abs(best->refresh_rate - long_refresh) > 3) { 2017 if (abs(best->refresh - long_refresh) > 3) {
2017 if (hres == 1200 && vres == 900) 2018 if (hres == 1200 && vres == 900)
2018 return 49; /* OLPC DCON only supports 50 Hz */ 2019 return 49; /* OLPC DCON only supports 50 Hz */
2019 else 2020 else
2020 return 60; 2021 return 60;
2021 } 2022 }
2022 2023
2023 return best->refresh_rate; 2024 return best->refresh;
2024} 2025}
2025 2026
2026static void device_off(void) 2027static void device_off(void)
@@ -2114,26 +2115,16 @@ void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2114} 2115}
2115 2116
2116void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, 2117void viafb_fill_var_timing_info(struct fb_var_screeninfo *var,
2117 struct crt_mode_table *mode) 2118 const struct fb_videomode *mode)
2118{ 2119{
2119 struct display_timing crt_reg; 2120 var->pixclock = mode->pixclock;
2120 2121 var->xres = mode->xres;
2121 crt_reg = mode->crtc; 2122 var->yres = mode->yres;
2122 var->pixclock = 1000000000 / (crt_reg.hor_total * crt_reg.ver_total) 2123 var->left_margin = mode->left_margin;
2123 * 1000 / mode->refresh_rate; 2124 var->right_margin = mode->right_margin;
2124 var->xres = crt_reg.hor_addr; 2125 var->hsync_len = mode->hsync_len;
2125 var->yres = crt_reg.ver_addr; 2126 var->upper_margin = mode->upper_margin;
2126 var->left_margin = 2127 var->lower_margin = mode->lower_margin;
2127 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); 2128 var->vsync_len = mode->vsync_len;
2128 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr; 2129 var->sync = mode->sync;
2129 var->hsync_len = crt_reg.hor_sync_end;
2130 var->upper_margin =
2131 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2132 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2133 var->vsync_len = crt_reg.ver_sync_end;
2134 var->sync = 0;
2135 if (mode->h_sync_polarity == POSITIVE)
2136 var->sync |= FB_SYNC_HOR_HIGH_ACT;
2137 if (mode->v_sync_polarity == POSITIVE)
2138 var->sync |= FB_SYNC_VERT_HIGH_ACT;
2139} 2130}
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index cacedc10699b..6be243cfc823 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -637,6 +637,8 @@ extern int viafb_LCD_ON;
637extern int viafb_DVI_ON; 637extern int viafb_DVI_ON;
638extern int viafb_hotplug; 638extern int viafb_hotplug;
639 639
640struct display_timing var_to_timing(const struct fb_var_screeninfo *var,
641 u16 cxres, u16 cyres);
640void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var, 642void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var,
641 u16 cxres, u16 cyres, int iga); 643 u16 cxres, u16 cyres, int iga);
642void viafb_set_vclock(u32 CLK, int set_iga); 644void viafb_set_vclock(u32 CLK, int set_iga);
@@ -660,7 +662,7 @@ void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
660 662
661int viafb_setmode(void); 663int viafb_setmode(void);
662void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, 664void viafb_fill_var_timing_info(struct fb_var_screeninfo *var,
663 struct crt_mode_table *mode); 665 const struct fb_videomode *mode);
664void __devinit viafb_init_chip_info(int chip_type); 666void __devinit viafb_init_chip_info(int chip_type);
665void __devinit viafb_init_dac(int set_iga); 667void __devinit viafb_init_dac(int set_iga);
666int viafb_get_refresh(int hres, int vres, u32 float_refresh); 668int viafb_get_refresh(int hres, int vres, u32 float_refresh);
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index 6e52711e9639..165037910536 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -75,9 +75,6 @@ static void check_diport_of_integrated_lvds(
75 struct lvds_chip_information *plvds_chip_info, 75 struct lvds_chip_information *plvds_chip_info,
76 struct lvds_setting_information 76 struct lvds_setting_information
77 *plvds_setting_info); 77 *plvds_setting_info);
78static struct display_timing lcd_centering_timging(struct display_timing
79 mode_crt_reg,
80 struct display_timing panel_crt_reg);
81 78
82static inline bool check_lvds_chip(int device_id_subaddr, int device_id) 79static inline bool check_lvds_chip(int device_id_subaddr, int device_id)
83{ 80{
@@ -552,39 +549,34 @@ void viafb_lcd_set_mode(const struct fb_var_screeninfo *var, u16 cxres,
552 int panel_hres = plvds_setting_info->lcd_panel_hres; 549 int panel_hres = plvds_setting_info->lcd_panel_hres;
553 int panel_vres = plvds_setting_info->lcd_panel_vres; 550 int panel_vres = plvds_setting_info->lcd_panel_vres;
554 u32 clock; 551 u32 clock;
555 struct display_timing mode_crt_reg, panel_crt_reg, timing; 552 struct display_timing timing;
556 struct crt_mode_table *mode_crt_table, *panel_crt_table; 553 struct fb_var_screeninfo panel_var;
554 const struct fb_videomode *mode_crt_table, *panel_crt_table;
557 555
558 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n"); 556 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
559 /* Get mode table */ 557 /* Get mode table */
560 mode_crt_table = viafb_get_best_mode(set_hres, set_vres, 60); 558 mode_crt_table = viafb_get_best_mode(set_hres, set_vres, 60);
561 mode_crt_reg = mode_crt_table->crtc;
562 /* Get panel table Pointer */ 559 /* Get panel table Pointer */
563 panel_crt_table = viafb_get_best_mode(panel_hres, panel_vres, 60); 560 panel_crt_table = viafb_get_best_mode(panel_hres, panel_vres, 60);
564 panel_crt_reg = panel_crt_table->crtc; 561 viafb_fill_var_timing_info(&panel_var, panel_crt_table);
565 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n"); 562 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
566 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) 563 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
567 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info); 564 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
568 clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total 565 clock = PICOS2KHZ(panel_crt_table->pixclock) * 1000;
569 * panel_crt_table->refresh_rate;
570 plvds_setting_info->vclk = clock; 566 plvds_setting_info->vclk = clock;
571 567
572 if (set_iga == IGA2 && (set_hres < panel_hres || set_vres < panel_vres) 568 if (set_iga == IGA2 && (set_hres < panel_hres || set_vres < panel_vres)
573 && plvds_setting_info->display_method == LCD_EXPANDSION) { 569 && plvds_setting_info->display_method == LCD_EXPANDSION) {
574 timing = panel_crt_reg; 570 timing = var_to_timing(&panel_var, panel_hres, panel_vres);
575 load_lcd_scaling(set_hres, set_vres, panel_hres, panel_vres); 571 load_lcd_scaling(set_hres, set_vres, panel_hres, panel_vres);
576 } else { 572 } else {
577 timing = lcd_centering_timging(mode_crt_reg, panel_crt_reg); 573 timing = var_to_timing(&panel_var, set_hres, set_vres);
578 if (set_iga == IGA2) 574 if (set_iga == IGA2)
579 /* disable scaling */ 575 /* disable scaling */
580 via_write_reg_mask(VIACR, 0x79, 0x00, 576 via_write_reg_mask(VIACR, 0x79, 0x00,
581 BIT0 + BIT1 + BIT2); 577 BIT0 + BIT1 + BIT2);
582 } 578 }
583 579
584 timing.hor_blank_end += timing.hor_blank_start;
585 timing.hor_sync_end += timing.hor_sync_start;
586 timing.ver_blank_end += timing.ver_blank_start;
587 timing.ver_sync_end += timing.ver_sync_start;
588 if (set_iga == IGA1) 580 if (set_iga == IGA1)
589 via_set_primary_timing(&timing); 581 via_set_primary_timing(&timing);
590 else if (set_iga == IGA2) 582 else if (set_iga == IGA2)
@@ -968,37 +960,6 @@ void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information
968 } 960 }
969} 961}
970 962
971static struct display_timing lcd_centering_timging(struct display_timing
972 mode_crt_reg,
973 struct display_timing panel_crt_reg)
974{
975 struct display_timing crt_reg;
976
977 crt_reg.hor_total = panel_crt_reg.hor_total;
978 crt_reg.hor_addr = mode_crt_reg.hor_addr;
979 crt_reg.hor_blank_start =
980 (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
981 crt_reg.hor_addr;
982 crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
983 crt_reg.hor_sync_start =
984 (panel_crt_reg.hor_sync_start -
985 panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
986 crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
987
988 crt_reg.ver_total = panel_crt_reg.ver_total;
989 crt_reg.ver_addr = mode_crt_reg.ver_addr;
990 crt_reg.ver_blank_start =
991 (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
992 crt_reg.ver_addr;
993 crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
994 crt_reg.ver_sync_start =
995 (panel_crt_reg.ver_sync_start -
996 panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
997 crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
998
999 return crt_reg;
1000}
1001
1002bool viafb_lcd_get_mobile_state(bool *mobile) 963bool viafb_lcd_get_mobile_state(bool *mobile)
1003{ 964{
1004 unsigned char __iomem *romptr, *tableptr, *biosptr; 965 unsigned char __iomem *romptr, *tableptr, *biosptr;
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
index c01c1c162726..3158dfc90bed 100644
--- a/drivers/video/via/share.h
+++ b/drivers/video/via/share.h
@@ -283,337 +283,6 @@
283#define HW_LAYOUT_LCD1_LCD2 0x04 283#define HW_LAYOUT_LCD1_LCD2 0x04
284#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10 284#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
285 285
286/* Definition Refresh Rate */
287#define REFRESH_49 49
288#define REFRESH_50 50
289#define REFRESH_60 60
290#define REFRESH_75 75
291#define REFRESH_85 85
292#define REFRESH_100 100
293#define REFRESH_120 120
294
295/* Definition Sync Polarity*/
296#define NEGATIVE 1
297#define POSITIVE 0
298
299/*480x640@60 Sync Polarity (GTF)
300*/
301#define M480X640_R60_HSP NEGATIVE
302#define M480X640_R60_VSP POSITIVE
303
304/*640x480@60 Sync Polarity (VESA Mode)
305*/
306#define M640X480_R60_HSP NEGATIVE
307#define M640X480_R60_VSP NEGATIVE
308
309/*640x480@75 Sync Polarity (VESA Mode)
310*/
311#define M640X480_R75_HSP NEGATIVE
312#define M640X480_R75_VSP NEGATIVE
313
314/*640x480@85 Sync Polarity (VESA Mode)
315*/
316#define M640X480_R85_HSP NEGATIVE
317#define M640X480_R85_VSP NEGATIVE
318
319/*640x480@100 Sync Polarity (GTF Mode)
320*/
321#define M640X480_R100_HSP NEGATIVE
322#define M640X480_R100_VSP POSITIVE
323
324/*640x480@120 Sync Polarity (GTF Mode)
325*/
326#define M640X480_R120_HSP NEGATIVE
327#define M640X480_R120_VSP POSITIVE
328
329/*720x480@60 Sync Polarity (GTF Mode)
330*/
331#define M720X480_R60_HSP NEGATIVE
332#define M720X480_R60_VSP POSITIVE
333
334/*720x576@60 Sync Polarity (GTF Mode)
335*/
336#define M720X576_R60_HSP NEGATIVE
337#define M720X576_R60_VSP POSITIVE
338
339/*800x600@60 Sync Polarity (VESA Mode)
340*/
341#define M800X600_R60_HSP POSITIVE
342#define M800X600_R60_VSP POSITIVE
343
344/*800x600@75 Sync Polarity (VESA Mode)
345*/
346#define M800X600_R75_HSP POSITIVE
347#define M800X600_R75_VSP POSITIVE
348
349/*800x600@85 Sync Polarity (VESA Mode)
350*/
351#define M800X600_R85_HSP POSITIVE
352#define M800X600_R85_VSP POSITIVE
353
354/*800x600@100 Sync Polarity (GTF Mode)
355*/
356#define M800X600_R100_HSP NEGATIVE
357#define M800X600_R100_VSP POSITIVE
358
359/*800x600@120 Sync Polarity (GTF Mode)
360*/
361#define M800X600_R120_HSP NEGATIVE
362#define M800X600_R120_VSP POSITIVE
363
364/*800x480@60 Sync Polarity (CVT Mode)
365*/
366#define M800X480_R60_HSP NEGATIVE
367#define M800X480_R60_VSP POSITIVE
368
369/*848x480@60 Sync Polarity (CVT Mode)
370*/
371#define M848X480_R60_HSP NEGATIVE
372#define M848X480_R60_VSP POSITIVE
373
374/*852x480@60 Sync Polarity (GTF Mode)
375*/
376#define M852X480_R60_HSP NEGATIVE
377#define M852X480_R60_VSP POSITIVE
378
379/*1024x512@60 Sync Polarity (GTF Mode)
380*/
381#define M1024X512_R60_HSP NEGATIVE
382#define M1024X512_R60_VSP POSITIVE
383
384/*1024x600@60 Sync Polarity (GTF Mode)
385*/
386#define M1024X600_R60_HSP NEGATIVE
387#define M1024X600_R60_VSP POSITIVE
388
389/*1024x768@60 Sync Polarity (VESA Mode)
390*/
391#define M1024X768_R60_HSP NEGATIVE
392#define M1024X768_R60_VSP NEGATIVE
393
394/*1024x768@75 Sync Polarity (VESA Mode)
395*/
396#define M1024X768_R75_HSP POSITIVE
397#define M1024X768_R75_VSP POSITIVE
398
399/*1024x768@85 Sync Polarity (VESA Mode)
400*/
401#define M1024X768_R85_HSP POSITIVE
402#define M1024X768_R85_VSP POSITIVE
403
404/*1024x768@100 Sync Polarity (GTF Mode)
405*/
406#define M1024X768_R100_HSP NEGATIVE
407#define M1024X768_R100_VSP POSITIVE
408
409/*1152x864@75 Sync Polarity (VESA Mode)
410*/
411#define M1152X864_R75_HSP POSITIVE
412#define M1152X864_R75_VSP POSITIVE
413
414/*1280x720@60 Sync Polarity (GTF Mode)
415*/
416#define M1280X720_R60_HSP NEGATIVE
417#define M1280X720_R60_VSP POSITIVE
418
419/* 1280x768@50 Sync Polarity (GTF Mode) */
420#define M1280X768_R50_HSP NEGATIVE
421#define M1280X768_R50_VSP POSITIVE
422
423/*1280x768@60 Sync Polarity (GTF Mode)
424*/
425#define M1280X768_R60_HSP NEGATIVE
426#define M1280X768_R60_VSP POSITIVE
427
428/*1280x800@60 Sync Polarity (CVT Mode)
429*/
430#define M1280X800_R60_HSP NEGATIVE
431#define M1280X800_R60_VSP POSITIVE
432
433/*1280x960@60 Sync Polarity (VESA Mode)
434*/
435#define M1280X960_R60_HSP POSITIVE
436#define M1280X960_R60_VSP POSITIVE
437
438/*1280x1024@60 Sync Polarity (VESA Mode)
439*/
440#define M1280X1024_R60_HSP POSITIVE
441#define M1280X1024_R60_VSP POSITIVE
442
443/* 1360x768@60 Sync Polarity (CVT Mode) */
444#define M1360X768_R60_HSP POSITIVE
445#define M1360X768_R60_VSP POSITIVE
446
447/* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */
448#define M1360X768_RB_R60_HSP POSITIVE
449#define M1360X768_RB_R60_VSP NEGATIVE
450
451/* 1368x768@50 Sync Polarity (GTF Mode) */
452#define M1368X768_R50_HSP NEGATIVE
453#define M1368X768_R50_VSP POSITIVE
454
455/* 1368x768@60 Sync Polarity (VESA Mode) */
456#define M1368X768_R60_HSP NEGATIVE
457#define M1368X768_R60_VSP POSITIVE
458
459/*1280x1024@75 Sync Polarity (VESA Mode)
460*/
461#define M1280X1024_R75_HSP POSITIVE
462#define M1280X1024_R75_VSP POSITIVE
463
464/*1280x1024@85 Sync Polarity (VESA Mode)
465*/
466#define M1280X1024_R85_HSP POSITIVE
467#define M1280X1024_R85_VSP POSITIVE
468
469/*1440x1050@60 Sync Polarity (GTF Mode)
470*/
471#define M1440X1050_R60_HSP NEGATIVE
472#define M1440X1050_R60_VSP POSITIVE
473
474/*1600x1200@60 Sync Polarity (VESA Mode)
475*/
476#define M1600X1200_R60_HSP POSITIVE
477#define M1600X1200_R60_VSP POSITIVE
478
479/*1600x1200@75 Sync Polarity (VESA Mode)
480*/
481#define M1600X1200_R75_HSP POSITIVE
482#define M1600X1200_R75_VSP POSITIVE
483
484/* 1680x1050@60 Sync Polarity (CVT Mode) */
485#define M1680x1050_R60_HSP NEGATIVE
486#define M1680x1050_R60_VSP NEGATIVE
487
488/* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
489#define M1680x1050_RB_R60_HSP POSITIVE
490#define M1680x1050_RB_R60_VSP NEGATIVE
491
492/* 1680x1050@75 Sync Polarity (CVT Mode) */
493#define M1680x1050_R75_HSP NEGATIVE
494#define M1680x1050_R75_VSP POSITIVE
495
496/*1920x1080@60 Sync Polarity (CVT Mode)
497*/
498#define M1920X1080_R60_HSP NEGATIVE
499#define M1920X1080_R60_VSP POSITIVE
500
501/* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */
502#define M1920X1080_RB_R60_HSP POSITIVE
503#define M1920X1080_RB_R60_VSP NEGATIVE
504
505/*1920x1440@60 Sync Polarity (VESA Mode)
506*/
507#define M1920X1440_R60_HSP NEGATIVE
508#define M1920X1440_R60_VSP POSITIVE
509
510/*1920x1440@75 Sync Polarity (VESA Mode)
511*/
512#define M1920X1440_R75_HSP NEGATIVE
513#define M1920X1440_R75_VSP POSITIVE
514
515#if 0
516/* 1400x1050@60 Sync Polarity (VESA Mode) */
517#define M1400X1050_R60_HSP NEGATIVE
518#define M1400X1050_R60_VSP NEGATIVE
519#endif
520
521/* 1400x1050@60 Sync Polarity (CVT Mode) */
522#define M1400X1050_R60_HSP NEGATIVE
523#define M1400X1050_R60_VSP POSITIVE
524
525/* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
526#define M1400X1050_RB_R60_HSP POSITIVE
527#define M1400X1050_RB_R60_VSP NEGATIVE
528
529/* 1400x1050@75 Sync Polarity (CVT Mode) */
530#define M1400X1050_R75_HSP NEGATIVE
531#define M1400X1050_R75_VSP POSITIVE
532
533/* 960x600@60 Sync Polarity (CVT Mode) */
534#define M960X600_R60_HSP NEGATIVE
535#define M960X600_R60_VSP POSITIVE
536
537/* 1000x600@60 Sync Polarity (GTF Mode) */
538#define M1000X600_R60_HSP NEGATIVE
539#define M1000X600_R60_VSP POSITIVE
540
541/* 1024x576@60 Sync Polarity (GTF Mode) */
542#define M1024X576_R60_HSP NEGATIVE
543#define M1024X576_R60_VSP POSITIVE
544
545/*1024x600@60 Sync Polarity (GTF Mode)*/
546#define M1024X600_R60_HSP NEGATIVE
547#define M1024X600_R60_VSP POSITIVE
548
549/* 1088x612@60 Sync Polarity (CVT Mode) */
550#define M1088X612_R60_HSP NEGATIVE
551#define M1088X612_R60_VSP POSITIVE
552
553/* 1152x720@60 Sync Polarity (CVT Mode) */
554#define M1152X720_R60_HSP NEGATIVE
555#define M1152X720_R60_VSP POSITIVE
556
557/* 1200x720@60 Sync Polarity (GTF Mode) */
558#define M1200X720_R60_HSP NEGATIVE
559#define M1200X720_R60_VSP POSITIVE
560
561/* 1200x900@60 Sync Polarity (DCON) */
562#define M1200X900_R60_HSP POSITIVE
563#define M1200X900_R60_VSP POSITIVE
564
565/* 1280x600@60 Sync Polarity (GTF Mode) */
566#define M1280x600_R60_HSP NEGATIVE
567#define M1280x600_R60_VSP POSITIVE
568
569/* 1280x720@50 Sync Polarity (GTF Mode) */
570#define M1280X720_R50_HSP NEGATIVE
571#define M1280X720_R50_VSP POSITIVE
572
573/* 1440x900@60 Sync Polarity (CVT Mode) */
574#define M1440X900_R60_HSP NEGATIVE
575#define M1440X900_R60_VSP POSITIVE
576
577/* 1440x900@75 Sync Polarity (CVT Mode) */
578#define M1440X900_R75_HSP NEGATIVE
579#define M1440X900_R75_VSP POSITIVE
580
581/* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
582#define M1440X900_RB_R60_HSP POSITIVE
583#define M1440X900_RB_R60_VSP NEGATIVE
584
585/* 1600x900@60 Sync Polarity (CVT Mode) */
586#define M1600X900_R60_HSP NEGATIVE
587#define M1600X900_R60_VSP POSITIVE
588
589/* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
590#define M1600X900_RB_R60_HSP POSITIVE
591#define M1600X900_RB_R60_VSP NEGATIVE
592
593/* 1600x1024@60 Sync Polarity (GTF Mode) */
594#define M1600X1024_R60_HSP NEGATIVE
595#define M1600X1024_R60_VSP POSITIVE
596
597/* 1792x1344@60 Sync Polarity (DMT Mode) */
598#define M1792x1344_R60_HSP NEGATIVE
599#define M1792x1344_R60_VSP POSITIVE
600
601/* 1856x1392@60 Sync Polarity (DMT Mode) */
602#define M1856x1392_R60_HSP NEGATIVE
603#define M1856x1392_R60_VSP POSITIVE
604
605/* 1920x1200@60 Sync Polarity (CVT Mode) */
606#define M1920X1200_R60_HSP NEGATIVE
607#define M1920X1200_R60_VSP POSITIVE
608
609/* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */
610#define M1920X1200_RB_R60_HSP POSITIVE
611#define M1920X1200_RB_R60_VSP NEGATIVE
612
613/* 2048x1536@60 Sync Polarity (CVT Mode) */
614#define M2048x1536_R60_HSP NEGATIVE
615#define M2048x1536_R60_VSP POSITIVE
616
617/* Definition CRTC Timing Index */ 286/* Definition CRTC Timing Index */
618#define H_TOTAL_INDEX 0 287#define H_TOTAL_INDEX 0
619#define H_ADDR_INDEX 1 288#define H_ADDR_INDEX 1
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
index 0911cac1b2ff..0666ab01cf4a 100644
--- a/drivers/video/via/viamode.c
+++ b/drivers/video/via/viamode.c
@@ -268,591 +268,78 @@ struct VPITTable VPIT = {
268/* Mode Table */ 268/* Mode Table */
269/********************/ 269/********************/
270 270
271/* 480x640 */ 271static const struct fb_videomode viafb_modes[] = {
272static struct crt_mode_table CRTM480x640[] = { 272 {NULL, 60, 480, 640, 40285, 72, 24, 19, 1, 48, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
273 /* r_rate, hsp, vsp */ 273 {NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, 0, 0, 0},
274 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 274 {NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0, 0, 0},
275 {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP, 275 {NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3, 0, 0, 0},
276 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/ 276 {NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
277}; 277 {NULL, 120, 640, 480, 19081, 104, 40, 31, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
278 278 {NULL, 60, 720, 480, 37426, 88, 16, 13, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
279/* 640x480*/ 279 {NULL, 60, 720, 576, 30611, 96, 24, 17, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
280static struct crt_mode_table CRTM640x480[] = { 280 {NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
281 /*r_rate,hsp,vsp */ 281 {NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
282 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 282 {NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
283 {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP, 283 {NULL, 100, 800, 600, 14667, 136, 48, 32, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
284 {800, 640, 640, 160, 656, 96, 525, 480, 480, 45, 490, 2} }, 284 {NULL, 120, 800, 600, 11911, 144, 56, 39, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
285 {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP, 285 {NULL, 60, 800, 480, 33602, 96, 24, 10, 3, 72, 7, FB_SYNC_VERT_HIGH_ACT, 0, 0},
286 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} }, 286 {NULL, 60, 848, 480, 31565, 104, 24, 12, 3, 80, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
287 {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP, 287 {NULL, 60, 856, 480, 31517, 104, 16, 13, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
288 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} }, 288 {NULL, 60, 1024, 512, 24218, 136, 32, 15, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
289 {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP, 289 {NULL, 60, 1024, 600, 20423, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
290 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/ 290 {NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, 0, 0, 0},
291 {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP, 291 {NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
292 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/ 292 {NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
293}; 293 {NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
294 294 {NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
295/*720x480 (GTF)*/ 295 {NULL, 60, 1280, 768, 12478, 200, 64, 23, 1, 136, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
296static struct crt_mode_table CRTM720x480[] = { 296 {NULL, 50, 1280, 768, 15342, 184, 56, 19, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
297 /*r_rate,hsp,vsp */ 297 {NULL, 60, 960, 600, 21964, 128, 32, 15, 3, 96, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
298 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 298 {NULL, 60, 1000, 600, 20803, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
299 {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP, 299 {NULL, 60, 1024, 576, 21278, 144, 40, 17, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
300 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} } 300 {NULL, 60, 1088, 612, 18825, 152, 48, 16, 3, 104, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
301 301 {NULL, 60, 1152, 720, 14974, 168, 56, 19, 3, 112, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
302}; 302 {NULL, 60, 1200, 720, 14248, 184, 56, 22, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
303 303 {NULL, 49, 1200, 900, 17703, 21, 11, 1, 1, 32, 10, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
304/*720x576 (GTF)*/ 304 {NULL, 60, 1280, 600, 16259, 184, 56, 18, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
305static struct crt_mode_table CRTM720x576[] = { 305 {NULL, 60, 1280, 800, 11938, 200, 72, 22, 3, 128, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
306 /*r_rate,hsp,vsp */ 306 {NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
307 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 307 {NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
308 {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP, 308 {NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
309 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} } 309 {NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
310}; 310 {NULL, 60, 1360, 768, 11759, 208, 72, 22, 3, 136, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
311 311 {NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
312/* 800x480 (CVT) */ 312 {NULL, 50, 1368, 768, 14301, 200, 56, 19, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
313static struct crt_mode_table CRTM800x480[] = { 313 {NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
314 /* r_rate, hsp, vsp */ 314 {NULL, 60, 1440, 900, 9372, 232, 80, 25, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
315 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 315 {NULL, 75, 1440, 900, 7311, 248, 96, 33, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
316 {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP, 316 {NULL, 60, 1440, 1040, 7993, 248, 96, 33, 1, 152, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
317 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} } 317 {NULL, 60, 1600, 900, 8449, 256, 88, 26, 3, 168, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
318}; 318 {NULL, 60, 1600, 1024, 7333, 272, 104, 32, 1, 168, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
319 319 {NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
320/* 800x600*/ 320 {NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
321static struct crt_mode_table CRTM800x600[] = { 321 {NULL, 60, 1680, 1050, 6832, 280, 104, 30, 3, 176, 6, 0, 0, 0},
322 /*r_rate,hsp,vsp */ 322 {NULL, 75, 1680, 1050, 5339, 296, 120, 40, 3, 176, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
323 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 323 {NULL, 60, 1792, 1344, 4883, 328, 128, 46, 1, 200, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
324 {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP, 324 {NULL, 60, 1856, 1392, 4581, 352, 96, 43, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
325 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} }, 325 {NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
326 {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP, 326 {NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
327 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} }, 327 {NULL, 60, 2048, 1536, 3738, 376, 152, 49, 3, 224, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0},
328 {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP, 328 {NULL, 60, 1280, 720, 13484, 216, 112, 20, 5, 40, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
329 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} }, 329 {NULL, 50, 1280, 720, 16538, 176, 48, 17, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
330 {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP, 330 {NULL, 60, 1920, 1080, 5776, 328, 128, 32, 3, 200, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
331 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} }, 331 {NULL, 60, 1920, 1200, 5164, 336, 136, 36, 3, 200, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
332 {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP, 332 {NULL, 60, 1400, 1050, 8210, 232, 88, 32, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0},
333 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} } 333 {NULL, 75, 1400, 1050, 6398, 248, 104, 42, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0} };
334}; 334
335 335static const struct fb_videomode viafb_rb_modes[] = {
336/* 848x480 (CVT) */ 336 {NULL, 60, 1360, 768, 13879, 80, 48, 14, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
337static struct crt_mode_table CRTM848x480[] = { 337 {NULL, 60, 1440, 900, 11249, 80, 48, 17, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0},
338 /* r_rate, hsp, vsp */ 338 {NULL, 60, 1400, 1050, 9892, 80, 48, 23, 3, 32, 4, FB_SYNC_HOR_HIGH_ACT, 0, 0},
339 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 339 {NULL, 60, 1600, 900, 10226, 80, 48, 18, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
340 {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP, 340 {NULL, 60, 1680, 1050, 8387, 80, 48, 21, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0},
341 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} } 341 {NULL, 60, 1920, 1080, 7212, 80, 48, 23, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
342}; 342 {NULL, 60, 1920, 1200, 6488, 80, 48, 26, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0} };
343
344/*856x480 (GTF) convert to 852x480*/
345static struct crt_mode_table CRTM852x480[] = {
346 /*r_rate,hsp,vsp */
347 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
348 {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
349 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
350};
351
352/*1024x512 (GTF)*/
353static struct crt_mode_table CRTM1024x512[] = {
354 /*r_rate,hsp,vsp */
355 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
356 {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
357 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
358
359};
360
361/* 1024x600*/
362static struct crt_mode_table CRTM1024x600[] = {
363 /*r_rate,hsp,vsp */
364 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
365 {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
366 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
367};
368
369/* 1024x768*/
370static struct crt_mode_table CRTM1024x768[] = {
371 /*r_rate,hsp,vsp */
372 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
373 {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
374 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
375 {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
376 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
377 {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
378 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
379 {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
380 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
381};
382
383/* 1152x864*/
384static struct crt_mode_table CRTM1152x864[] = {
385 /*r_rate,hsp,vsp */
386 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
387 {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
388 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
389
390};
391
392/* 1280x720 (HDMI 720P)*/
393static struct crt_mode_table CRTM1280x720[] = {
394 /*r_rate,hsp,vsp */
395 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
396 {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
397 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
398 {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
399 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
400};
401
402/*1280x768 (GTF)*/
403static struct crt_mode_table CRTM1280x768[] = {
404 /*r_rate,hsp,vsp */
405 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
406 {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
407 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
408 {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
409 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
410};
411
412/* 1280x800 (CVT) */
413static struct crt_mode_table CRTM1280x800[] = {
414 /* r_rate, hsp, vsp */
415 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
416 {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
417 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
418};
419
420/*1280x960*/
421static struct crt_mode_table CRTM1280x960[] = {
422 /*r_rate,hsp,vsp */
423 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
424 {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
425 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
426};
427
428/* 1280x1024*/
429static struct crt_mode_table CRTM1280x1024[] = {
430 /*r_rate,hsp,vsp */
431 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
432 {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
433 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
434 3} },
435 {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
436 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
437 3} },
438 {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
439 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
440};
441
442/* 1368x768 (GTF) */
443static struct crt_mode_table CRTM1368x768[] = {
444 /* r_rate, hsp, vsp */
445 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
446 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
447 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
448};
449
450/*1440x1050 (GTF)*/
451static struct crt_mode_table CRTM1440x1050[] = {
452 /*r_rate,hsp,vsp */
453 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
454 {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
455 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
456};
457
458/* 1600x1200*/
459static struct crt_mode_table CRTM1600x1200[] = {
460 /*r_rate,hsp,vsp */
461 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
462 {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
463 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
464 3} },
465 {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
466 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
467
468};
469
470/* 1680x1050 (CVT) */
471static struct crt_mode_table CRTM1680x1050[] = {
472 /* r_rate, hsp, vsp */
473 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
474 {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
475 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
476 6} },
477 {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
478 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
479};
480
481/* 1680x1050 (CVT Reduce Blanking) */
482static struct crt_mode_table CRTM1680x1050_RB[] = {
483 /* r_rate, hsp, vsp */
484 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
485 {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
486 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
487};
488
489/* 1920x1080 (CVT)*/
490static struct crt_mode_table CRTM1920x1080[] = {
491 /*r_rate,hsp,vsp */
492 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
493 {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
494 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
495};
496
497/* 1920x1080 (CVT with Reduce Blanking) */
498static struct crt_mode_table CRTM1920x1080_RB[] = {
499 /* r_rate, hsp, vsp */
500 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
501 {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
502 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
503};
504
505/* 1920x1440*/
506static struct crt_mode_table CRTM1920x1440[] = {
507 /*r_rate,hsp,vsp */
508 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
509 {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
510 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
511 3} },
512 {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
513 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
514};
515
516/* 1400x1050 (CVT) */
517static struct crt_mode_table CRTM1400x1050[] = {
518 /* r_rate, hsp, vsp */
519 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
520 {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
521 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
522 4} },
523 {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
524 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
525};
526
527/* 1400x1050 (CVT Reduce Blanking) */
528static struct crt_mode_table CRTM1400x1050_RB[] = {
529 /* r_rate, hsp, vsp */
530 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
531 {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
532 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
533};
534
535/* 960x600 (CVT) */
536static struct crt_mode_table CRTM960x600[] = {
537 /* r_rate, hsp, vsp */
538 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
539 {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
540 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
541};
542
543/* 1000x600 (GTF) */
544static struct crt_mode_table CRTM1000x600[] = {
545 /* r_rate, hsp, vsp */
546 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
547 {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
548 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
549};
550
551/* 1024x576 (GTF) */
552static struct crt_mode_table CRTM1024x576[] = {
553 /* r_rate, hsp, vsp */
554 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
555 {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
556 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
557};
558
559/* 1088x612 (CVT) */
560static struct crt_mode_table CRTM1088x612[] = {
561 /* r_rate, hsp, vsp */
562 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
563 {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
564 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
565};
566
567/* 1152x720 (CVT) */
568static struct crt_mode_table CRTM1152x720[] = {
569 /* r_rate, hsp, vsp */
570 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
571 {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
572 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
573};
574
575/* 1200x720 (GTF) */
576static struct crt_mode_table CRTM1200x720[] = {
577 /* r_rate, hsp, vsp */
578 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
579 {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
580 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
581};
582
583/* 1200x900 (DCON) */
584static struct crt_mode_table DCON1200x900[] = {
585 /* r_rate, hsp, vsp */
586 {REFRESH_49, M1200X900_R60_HSP, M1200X900_R60_VSP,
587 /* The correct htotal is 1240, but this doesn't raster on VX855. */
588 /* Via suggested changing to a multiple of 16, hence 1264. */
589 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
590 {1264, 1200, 1200, 64, 1211, 32, 912, 900, 900, 12, 901, 10} }
591};
592
593/* 1280x600 (GTF) */
594static struct crt_mode_table CRTM1280x600[] = {
595 /* r_rate, hsp, vsp */
596 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
597 {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
598 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
599};
600
601/* 1360x768 (CVT) */
602static struct crt_mode_table CRTM1360x768[] = {
603 /* r_rate, hsp, vsp */
604 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
605 {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
606 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
607};
608
609/* 1360x768 (CVT Reduce Blanking) */
610static struct crt_mode_table CRTM1360x768_RB[] = {
611 /* r_rate, hsp, vsp */
612 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
613 {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
614 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
615};
616
617/* 1366x768 (GTF) */
618static struct crt_mode_table CRTM1366x768[] = {
619 /* r_rate, hsp, vsp */
620 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
621 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
622 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
623 {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
624 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
625};
626
627/* 1440x900 (CVT) */
628static struct crt_mode_table CRTM1440x900[] = {
629 /* r_rate, hsp, vsp */
630 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
631 {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
632 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
633 {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
634 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
635};
636
637/* 1440x900 (CVT Reduce Blanking) */
638static struct crt_mode_table CRTM1440x900_RB[] = {
639 /* r_rate, hsp, vsp */
640 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
641 {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
642 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
643};
644
645/* 1600x900 (CVT) */
646static struct crt_mode_table CRTM1600x900[] = {
647 /* r_rate, hsp, vsp */
648 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
649 {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
650 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
651};
652
653/* 1600x900 (CVT Reduce Blanking) */
654static struct crt_mode_table CRTM1600x900_RB[] = {
655 /* r_rate, hsp, vsp */
656 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
657 {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
658 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
659};
660
661/* 1600x1024 (GTF) */
662static struct crt_mode_table CRTM1600x1024[] = {
663 /* r_rate, hsp, vsp */
664 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
665 {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
666 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
667};
668
669/* 1792x1344 (DMT) */
670static struct crt_mode_table CRTM1792x1344[] = {
671 /* r_rate, hsp, vsp */
672 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
673 {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
674 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
675};
676
677/* 1856x1392 (DMT) */
678static struct crt_mode_table CRTM1856x1392[] = {
679 /* r_rate, hsp, vsp */
680 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
681 {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
682 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
683};
684
685/* 1920x1200 (CVT) */
686static struct crt_mode_table CRTM1920x1200[] = {
687 /* r_rate, hsp, vsp */
688 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
689 {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
690 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
691};
692
693/* 1920x1200 (CVT with Reduce Blanking) */
694static struct crt_mode_table CRTM1920x1200_RB[] = {
695 /* r_rate, hsp, vsp */
696 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
697 {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
698 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
699};
700
701/* 2048x1536 (CVT) */
702static struct crt_mode_table CRTM2048x1536[] = {
703 /* r_rate, hsp, vsp */
704 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
705 {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
706 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
707};
708
709static struct VideoModeTable viafb_modes[] = {
710 /* Display : 480x640 (GTF) */
711 {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
712
713 /* Display : 640x480 */
714 {CRTM640x480, ARRAY_SIZE(CRTM640x480)},
715
716 /* Display : 720x480 (GTF) */
717 {CRTM720x480, ARRAY_SIZE(CRTM720x480)},
718
719 /* Display : 720x576 (GTF) */
720 {CRTM720x576, ARRAY_SIZE(CRTM720x576)},
721
722 /* Display : 800x600 */
723 {CRTM800x600, ARRAY_SIZE(CRTM800x600)},
724
725 /* Display : 800x480 (CVT) */
726 {CRTM800x480, ARRAY_SIZE(CRTM800x480)},
727
728 /* Display : 848x480 (CVT) */
729 {CRTM848x480, ARRAY_SIZE(CRTM848x480)},
730
731 /* Display : 852x480 (GTF) */
732 {CRTM852x480, ARRAY_SIZE(CRTM852x480)},
733
734 /* Display : 1024x512 (GTF) */
735 {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
736
737 /* Display : 1024x600 */
738 {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
739
740 /* Display : 1024x768 */
741 {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
742
743 /* Display : 1152x864 */
744 {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
745
746 /* Display : 1280x768 (GTF) */
747 {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
748
749 /* Display : 960x600 (CVT) */
750 {CRTM960x600, ARRAY_SIZE(CRTM960x600)},
751
752 /* Display : 1000x600 (GTF) */
753 {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
754
755 /* Display : 1024x576 (GTF) */
756 {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
757
758 /* Display : 1088x612 (GTF) */
759 {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
760
761 /* Display : 1152x720 (CVT) */
762 {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
763
764 /* Display : 1200x720 (GTF) */
765 {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
766
767 /* Display : 1200x900 (DCON) */
768 {DCON1200x900, ARRAY_SIZE(DCON1200x900)},
769
770 /* Display : 1280x600 (GTF) */
771 {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
772
773 /* Display : 1280x800 (CVT) */
774 {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
775
776 /* Display : 1280x960 */
777 {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
778
779 /* Display : 1280x1024 */
780 {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
781
782 /* Display : 1360x768 (CVT) */
783 {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
784
785 /* Display : 1366x768 */
786 {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
787
788 /* Display : 1368x768 (GTF) */
789 {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
790
791 /* Display : 1440x900 (CVT) */
792 {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
793
794 /* Display : 1440x1050 (GTF) */
795 {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
796
797 /* Display : 1600x900 (CVT) */
798 {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
799
800 /* Display : 1600x1024 (GTF) */
801 {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
802
803 /* Display : 1600x1200 */
804 {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
805
806 /* Display : 1680x1050 (CVT) */
807 {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
808
809 /* Display : 1792x1344 (DMT) */
810 {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
811
812 /* Display : 1856x1392 (DMT) */
813 {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
814
815 /* Display : 1920x1440 */
816 {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
817
818 /* Display : 2048x1536 */
819 {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
820
821 /* Display : 1280x720 */
822 {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
823
824 /* Display : 1920x1080 (CVT) */
825 {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
826
827 /* Display : 1920x1200 (CVT) */
828 {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
829
830 /* Display : 1400x1050 (CVT) */
831 {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
832};
833
834static struct VideoModeTable viafb_rb_modes[] = {
835 /* Display : 1360x768 (CVT Reduce Blanking) */
836 {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
837
838 /* Display : 1440x900 (CVT Reduce Blanking) */
839 {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)},
840
841 /* Display : 1400x1050 (CVT Reduce Blanking) */
842 {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)},
843
844 /* Display : 1600x900 (CVT Reduce Blanking) */
845 {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)},
846
847 /* Display : 1680x1050 (CVT Reduce Blanking) */
848 {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)},
849
850 /* Display : 1920x1080 (CVT Reduce Blanking) */
851 {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)},
852
853 /* Display : 1920x1200 (CVT Reduce Blanking) */
854 {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)}
855};
856 343
857int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs); 344int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
858int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs); 345int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
@@ -863,56 +350,34 @@ int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
863int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table); 350int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
864 351
865 352
866static struct VideoModeTable *get_modes(struct VideoModeTable *vmt, int n, 353static const struct fb_videomode *get_best_mode(
867 int hres, int vres) 354 const struct fb_videomode *modes, int n,
868{ 355 int hres, int vres, int refresh)
869 int i;
870
871 for (i = 0; i < n; i++)
872 if (vmt[i].mode_array &&
873 vmt[i].crtc[0].crtc.hor_addr == hres &&
874 vmt[i].crtc[0].crtc.ver_addr == vres)
875 return &viafb_modes[i];
876
877 return NULL;
878}
879
880static struct crt_mode_table *get_best_mode(struct VideoModeTable *vmt,
881 int refresh)
882{ 356{
883 struct crt_mode_table *best; 357 const struct fb_videomode *best = NULL;
884 int i; 358 int i;
885 359
886 if (!vmt) 360 for (i = 0; i < n; i++) {
887 return NULL; 361 if (modes[i].xres != hres || modes[i].yres != vres)
362 continue;
888 363
889 best = &vmt->crtc[0]; 364 if (!best || abs(modes[i].refresh - refresh) <
890 for (i = 1; i < vmt->mode_array; i++) { 365 abs(best->refresh - refresh))
891 if (abs(vmt->crtc[i].refresh_rate - refresh) 366 best = &modes[i];
892 < abs(best->refresh_rate - refresh))
893 best = &vmt->crtc[i];
894 } 367 }
895 368
896 return best; 369 return best;
897} 370}
898 371
899static struct VideoModeTable *viafb_get_mode(int hres, int vres) 372const struct fb_videomode *viafb_get_best_mode(int hres, int vres, int refresh)
900{
901 return get_modes(viafb_modes, ARRAY_SIZE(viafb_modes), hres, vres);
902}
903
904struct crt_mode_table *viafb_get_best_mode(int hres, int vres, int refresh)
905{ 373{
906 return get_best_mode(viafb_get_mode(hres, vres), refresh); 374 return get_best_mode(viafb_modes, ARRAY_SIZE(viafb_modes),
375 hres, vres, refresh);
907} 376}
908 377
909static struct VideoModeTable *viafb_get_rb_mode(int hres, int vres) 378const struct fb_videomode *viafb_get_best_rb_mode(int hres, int vres,
910{ 379 int refresh)
911 return get_modes(viafb_rb_modes, ARRAY_SIZE(viafb_rb_modes), hres,
912 vres);
913}
914
915struct crt_mode_table *viafb_get_best_rb_mode(int hres, int vres, int refresh)
916{ 380{
917 return get_best_mode(viafb_get_rb_mode(hres, vres), refresh); 381 return get_best_mode(viafb_rb_modes, ARRAY_SIZE(viafb_rb_modes),
382 hres, vres, refresh);
918} 383}
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
index 5917a2b00e1b..dd19106698e7 100644
--- a/drivers/video/via/viamode.h
+++ b/drivers/video/via/viamode.h
@@ -31,11 +31,6 @@ struct VPITTable {
31 unsigned char AR[StdAR]; 31 unsigned char AR[StdAR];
32}; 32};
33 33
34struct VideoModeTable {
35 struct crt_mode_table *crtc;
36 int mode_array;
37};
38
39struct patch_table { 34struct patch_table {
40 int table_length; 35 int table_length;
41 struct io_reg *io_reg_table; 36 struct io_reg *io_reg_table;
@@ -60,7 +55,9 @@ extern struct io_reg PM1024x768[];
60extern struct patch_table res_patch_table[]; 55extern struct patch_table res_patch_table[];
61extern struct VPITTable VPIT; 56extern struct VPITTable VPIT;
62 57
63struct crt_mode_table *viafb_get_best_mode(int hres, int vres, int refresh); 58const struct fb_videomode *viafb_get_best_mode(int hres, int vres,
64struct crt_mode_table *viafb_get_best_rb_mode(int hres, int vres, int refresh); 59 int refresh);
60const struct fb_videomode *viafb_get_best_rb_mode(int hres, int vres,
61 int refresh);
65 62
66#endif /* __VIAMODE_H__ */ 63#endif /* __VIAMODE_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 01:10:34 -0500