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authorJoseph Chan <JosephChan@via.com.tw>2008-10-16 01:03:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-16 14:21:42 -0400
commit9f291634aa2d79dee2d8a61c5bdffe166001c580 (patch)
tree823bbbd71203b101ad681e074f41b3a71da5f291 /drivers/video/via
parentb3a45d8e5d9049c3a47b3f97405b4123bef5155b (diff)
viafb: via_i2c.c, via_i2c.h, viamode.c, viamode.h
via_i2c.c, via_i2c.h: Implement i2c specification. viamode.c, viamode.c: all support modes information. Signed-off-by: Joseph Chan <josephchan@via.com.tw> Cc: Krzysztof Helt <krzysztof.h1@poczta.fm> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/via')
-rw-r--r--drivers/video/via/via_i2c.c177
-rw-r--r--drivers/video/via/via_i2c.h46
-rw-r--r--drivers/video/via/viamode.c1086
-rw-r--r--drivers/video/via/viamode.h177
4 files changed, 1486 insertions, 0 deletions
diff --git a/drivers/video/via/via_i2c.c b/drivers/video/via/via_i2c.c
new file mode 100644
index 000000000000..0f3ed4eb236d
--- /dev/null
+++ b/drivers/video/via/via_i2c.c
@@ -0,0 +1,177 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24static void via_i2c_setscl(void *data, int state)
25{
26 u8 val;
27 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
28
29 val = viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0xF0;
30 if (state)
31 val |= 0x20;
32 else
33 val &= ~0x20;
34 switch (via_i2c_chan->i2c_port) {
35 case I2CPORTINDEX:
36 val |= 0x01;
37 break;
38 case GPIOPORTINDEX:
39 val |= 0x80;
40 break;
41 default:
42 DEBUG_MSG("via_i2c: specify wrong i2c port.\n");
43 }
44 viafb_write_reg(via_i2c_chan->i2c_port, VIASR, val);
45}
46
47static int via_i2c_getscl(void *data)
48{
49 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
50
51 if (viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0x08)
52 return 1;
53 return 0;
54}
55
56static int via_i2c_getsda(void *data)
57{
58 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
59
60 if (viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0x04)
61 return 1;
62 return 0;
63}
64
65static void via_i2c_setsda(void *data, int state)
66{
67 u8 val;
68 struct via_i2c_stuff *via_i2c_chan = (struct via_i2c_stuff *)data;
69
70 val = viafb_read_reg(VIASR, via_i2c_chan->i2c_port) & 0xF0;
71 if (state)
72 val |= 0x10;
73 else
74 val &= ~0x10;
75 switch (via_i2c_chan->i2c_port) {
76 case I2CPORTINDEX:
77 val |= 0x01;
78 break;
79 case GPIOPORTINDEX:
80 val |= 0x40;
81 break;
82 default:
83 DEBUG_MSG("via_i2c: specify wrong i2c port.\n");
84 }
85 viafb_write_reg(via_i2c_chan->i2c_port, VIASR, val);
86}
87
88int viafb_i2c_readbyte(u8 slave_addr, u8 index, u8 *pdata)
89{
90 u8 mm1[] = {0x00};
91 struct i2c_msg msgs[2];
92
93 *pdata = 0;
94 msgs[0].flags = 0;
95 msgs[1].flags = I2C_M_RD;
96 msgs[0].addr = msgs[1].addr = slave_addr / 2;
97 mm1[0] = index;
98 msgs[0].len = 1; msgs[1].len = 1;
99 msgs[0].buf = mm1; msgs[1].buf = pdata;
100 i2c_transfer(&viaparinfo->i2c_stuff.adapter, msgs, 2);
101
102 return 0;
103}
104
105int viafb_i2c_writebyte(u8 slave_addr, u8 index, u8 data)
106{
107 u8 msg[2] = { index, data };
108 struct i2c_msg msgs;
109
110 msgs.flags = 0;
111 msgs.addr = slave_addr / 2;
112 msgs.len = 2;
113 msgs.buf = msg;
114 return i2c_transfer(&viaparinfo->i2c_stuff.adapter, &msgs, 1);
115}
116
117int viafb_i2c_readbytes(u8 slave_addr, u8 index, u8 *buff, int buff_len)
118{
119 u8 mm1[] = {0x00};
120 struct i2c_msg msgs[2];
121
122 msgs[0].flags = 0;
123 msgs[1].flags = I2C_M_RD;
124 msgs[0].addr = msgs[1].addr = slave_addr / 2;
125 mm1[0] = index;
126 msgs[0].len = 1; msgs[1].len = buff_len;
127 msgs[0].buf = mm1; msgs[1].buf = buff;
128 i2c_transfer(&viaparinfo->i2c_stuff.adapter, msgs, 2);
129 return 0;
130}
131
132int viafb_create_i2c_bus(void *viapar)
133{
134 int ret;
135 struct viafb_par *par = (struct viafb_par *)viapar;
136
137 strcpy(par->i2c_stuff.adapter.name, "via_i2c");
138 par->i2c_stuff.i2c_port = 0x0;
139 par->i2c_stuff.adapter.owner = THIS_MODULE;
140 par->i2c_stuff.adapter.id = 0x01FFFF;
141 par->i2c_stuff.adapter.class = 0;
142 par->i2c_stuff.adapter.algo_data = &par->i2c_stuff.algo;
143 par->i2c_stuff.adapter.dev.parent = NULL;
144 par->i2c_stuff.algo.setsda = via_i2c_setsda;
145 par->i2c_stuff.algo.setscl = via_i2c_setscl;
146 par->i2c_stuff.algo.getsda = via_i2c_getsda;
147 par->i2c_stuff.algo.getscl = via_i2c_getscl;
148 par->i2c_stuff.algo.udelay = 40;
149 par->i2c_stuff.algo.timeout = 20;
150 par->i2c_stuff.algo.data = &par->i2c_stuff;
151
152 i2c_set_adapdata(&par->i2c_stuff.adapter, &par->i2c_stuff);
153
154 /* Raise SCL and SDA */
155 par->i2c_stuff.i2c_port = I2CPORTINDEX;
156 via_i2c_setsda(&par->i2c_stuff, 1);
157 via_i2c_setscl(&par->i2c_stuff, 1);
158
159 par->i2c_stuff.i2c_port = GPIOPORTINDEX;
160 via_i2c_setsda(&par->i2c_stuff, 1);
161 via_i2c_setscl(&par->i2c_stuff, 1);
162 udelay(20);
163
164 ret = i2c_bit_add_bus(&par->i2c_stuff.adapter);
165 if (ret == 0)
166 DEBUG_MSG("I2C bus %s registered.\n",
167 par->i2c_stuff.adapter.name);
168 else
169 DEBUG_MSG("Failed to register I2C bus %s.\n",
170 par->i2c_stuff.adapter.name);
171 return ret;
172}
173
174void viafb_delete_i2c_buss(void *par)
175{
176 i2c_del_adapter(&((struct viafb_par *)par)->i2c_stuff.adapter);
177}
diff --git a/drivers/video/via/via_i2c.h b/drivers/video/via/via_i2c.h
new file mode 100644
index 000000000000..3a13242a3152
--- /dev/null
+++ b/drivers/video/via/via_i2c.h
@@ -0,0 +1,46 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __VIA_I2C_H__
22#define __VIA_I2C_H__
23
24#include <linux/i2c.h>
25#include <linux/i2c-algo-bit.h>
26
27struct via_i2c_stuff {
28 u16 i2c_port; /* GPIO or I2C port */
29 struct i2c_adapter adapter;
30 struct i2c_algo_bit_data algo;
31};
32
33#define I2CPORT 0x3c4
34#define I2CPORTINDEX 0x31
35#define GPIOPORT 0x3C4
36#define GPIOPORTINDEX 0x2C
37#define I2C_BUS 1
38#define GPIO_BUS 2
39#define DELAYPORT 0x3C3
40
41int viafb_i2c_readbyte(u8 slave_addr, u8 index, u8 *pdata);
42int viafb_i2c_writebyte(u8 slave_addr, u8 index, u8 data);
43int viafb_i2c_readbytes(u8 slave_addr, u8 index, u8 *buff, int buff_len);
44int viafb_create_i2c_bus(void *par);
45void viafb_delete_i2c_buss(void *par);
46#endif /* __VIA_I2C_H__ */
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
new file mode 100644
index 000000000000..6dcf583a837d
--- /dev/null
+++ b/drivers/video/via/viamode.c
@@ -0,0 +1,1086 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23struct res_map_refresh res_map_refresh_tbl[] = {
24/*hres, vres, vclock, vmode_refresh*/
25 {480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
26 {640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
27 {640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
28 {640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
29 {640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
30 {640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
31 {720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
32 {720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
33 {800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
34 {800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
35 {800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
36 {800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
37 {800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
38 {800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
39 {848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
40 {856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
41 {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
42 {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
43 {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
44 {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
45 {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
46 {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
47/* {1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},*/
48 {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
49 {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
50 {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
51 {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
52 {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
53 {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
54 {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
55 {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
56 {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
57 {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
58 {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
59 {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
60 {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
61 {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
62 {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
63 {960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
64 {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
65 {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
66 {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
67 {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
68 {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
69 {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
70 {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
71 {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
72 {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
73 {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
74 {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
75 {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
76 {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
77 {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
78 {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
79 {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
80 {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
81 {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
82 {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
83 {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
84 {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
85 {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
86 {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
87};
88
89struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
90{VIASR, SR15, 0x02, 0x02},
91{VIASR, SR16, 0xBF, 0x08},
92{VIASR, SR17, 0xFF, 0x1F},
93{VIASR, SR18, 0xFF, 0x4E},
94{VIASR, SR1A, 0xFB, 0x08},
95{VIASR, SR1E, 0x0F, 0x01},
96{VIASR, SR2A, 0xFF, 0x00},
97{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
98{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
99{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
100{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
101{VIACR, CR32, 0xFF, 0x00},
102{VIACR, CR33, 0xFF, 0x00},
103{VIACR, CR34, 0xFF, 0x00},
104{VIACR, CR35, 0xFF, 0x00},
105{VIACR, CR36, 0x08, 0x00},
106{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
107{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
108{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
109{VIACR, CR69, 0xFF, 0x00},
110{VIACR, CR6A, 0xFF, 0x40},
111{VIACR, CR6B, 0xFF, 0x00},
112{VIACR, CR6C, 0xFF, 0x00},
113{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
114{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
115{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
116{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
117{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
118{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
119{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
120{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
121{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
122{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
123{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
124{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
125{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
126{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
127{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
128{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
129{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
130{VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */
131{VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */
132{VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */
133{VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */
134{VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */
135{VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */
136{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
137{VIACR, CR96, 0xFF, 0x00},
138{VIACR, CR97, 0xFF, 0x00},
139{VIACR, CR99, 0xFF, 0x00},
140{VIACR, CR9B, 0xFF, 0x00}
141};
142
143/* Video Mode Table for VT3314 chipset*/
144/* Common Setting for Video Mode */
145struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
146{VIASR, SR15, 0x02, 0x02},
147{VIASR, SR16, 0xBF, 0x08},
148{VIASR, SR17, 0xFF, 0x1F},
149{VIASR, SR18, 0xFF, 0x4E},
150{VIASR, SR1A, 0xFB, 0x82},
151{VIASR, SR1B, 0xFF, 0xF0},
152{VIASR, SR1F, 0xFF, 0x00},
153{VIASR, SR1E, 0xFF, 0x01},
154{VIASR, SR22, 0xFF, 0x1F},
155{VIASR, SR2A, 0x0F, 0x00},
156{VIASR, SR2E, 0xFF, 0xFF},
157{VIASR, SR3F, 0xFF, 0xFF},
158{VIASR, SR40, 0xF7, 0x00},
159{VIASR, CR30, 0xFF, 0x04},
160{VIACR, CR32, 0xFF, 0x00},
161{VIACR, CR33, 0x7F, 0x00},
162{VIACR, CR34, 0xFF, 0x00},
163{VIACR, CR35, 0xFF, 0x00},
164{VIACR, CR36, 0xFF, 0x31},
165{VIACR, CR41, 0xFF, 0x80},
166{VIACR, CR42, 0xFF, 0x00},
167{VIACR, CR55, 0x80, 0x00},
168{VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/
169{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
170{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
171{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
172{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
173{VIACR, CR69, 0xFF, 0x00},
174{VIACR, CR6A, 0xFD, 0x40},
175{VIACR, CR6B, 0xFF, 0x00},
176{VIACR, CR6C, 0xFF, 0x00},
177{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */
178{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
179{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
180{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */
181{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
182{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
183{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
184{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
185{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
186{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
187{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
188{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
189{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
190{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
191{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
192{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
193{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
194{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
195{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
196{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
197{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
198{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
199{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
200{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
201{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
202{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
203{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
204{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
205{VIACR, CR96, 0xFF, 0x00},
206{VIACR, CR97, 0xFF, 0x00},
207{VIACR, CR99, 0xFF, 0x00},
208{VIACR, CR9B, 0xFF, 0x00},
209{VIACR, CR9D, 0xFF, 0x80},
210{VIACR, CR9E, 0xFF, 0x80}
211};
212
213struct io_reg KM400_ModeXregs[] = {
214 {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
215 {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
216 {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
217 {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
218 {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
219 {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
220 {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
221 {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */
222 {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
223 {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
224 {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
225 {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */
226 {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
227 {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
228 {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
229 {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
230 {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
231 {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
232 {VIACR, CR33, 0xFF, 0x00},
233 {VIACR, CR55, 0x80, 0x00},
234 {VIACR, CR5D, 0x80, 0x00},
235 {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
236 {VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
237 {VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
238 {VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
239 {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
240 {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
241 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
242 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
243 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
244 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
245 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
246 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
247 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
248 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
249 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
250 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
251 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
252 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
253 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
254 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
255 {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
256 {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
257 {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
258 {VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */
259 {VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */
260 {VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */
261 {VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */
262 {VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */
263 {VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */
264 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
265 {VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */
266 {VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */
267 {VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/
268 {VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/
269};
270
271/* For VT3324: Common Setting for Video Mode */
272struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
273{VIASR, SR15, 0x02, 0x02},
274{VIASR, SR16, 0xBF, 0x08},
275{VIASR, SR17, 0xFF, 0x1F},
276{VIASR, SR18, 0xFF, 0x4E},
277{VIASR, SR1A, 0xFB, 0x08},
278{VIASR, SR1B, 0xFF, 0xF0},
279{VIASR, SR1E, 0xFF, 0x01},
280{VIASR, SR2A, 0xFF, 0x00},
281{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
282{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
283{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
284{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
285{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
286{VIACR, CR32, 0xFF, 0x00},
287{VIACR, CR33, 0xFF, 0x00},
288{VIACR, CR34, 0xFF, 0x00},
289{VIACR, CR35, 0xFF, 0x00},
290{VIACR, CR36, 0x08, 0x00},
291{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
292{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
293{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
294{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
295{VIACR, CRA3, 0xFF, 0x00}, /* Secondary Display Starting Address */
296{VIACR, CR69, 0xFF, 0x00},
297{VIACR, CR6A, 0xFF, 0x40},
298{VIACR, CR6B, 0xFF, 0x00},
299{VIACR, CR6C, 0xFF, 0x00},
300{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
301{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
302{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
303{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
304{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
305{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
306{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
307{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
308{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
309{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
310{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
311{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
312{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
313{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
314{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
315{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
316{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
317{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
318{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
319{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
320{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
321{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
322{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
323{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
324{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
325{VIACR, CR96, 0xFF, 0x00},
326{VIACR, CR97, 0xFF, 0x00},
327{VIACR, CR99, 0xFF, 0x00},
328{VIACR, CR9B, 0xFF, 0x00},
329{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
330};
331
332/* For VT3353: Common Setting for Video Mode */
333struct io_reg VX800_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
334{VIASR, SR15, 0x02, 0x02},
335{VIASR, SR16, 0xBF, 0x08},
336{VIASR, SR17, 0xFF, 0x1F},
337{VIASR, SR18, 0xFF, 0x4E},
338{VIASR, SR1A, 0xFB, 0x08},
339{VIASR, SR1B, 0xFF, 0xF0},
340{VIASR, SR1E, 0xFF, 0x01},
341{VIASR, SR2A, 0xFF, 0x00},
342{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
343{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
344{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
345{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
346{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
347{VIACR, CR32, 0xFF, 0x00},
348{VIACR, CR33, 0xFF, 0x00},
349{VIACR, CR34, 0xFF, 0x00},
350{VIACR, CR35, 0xFF, 0x00},
351{VIACR, CR36, 0x08, 0x00},
352{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
353{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
354{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
355{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
356{VIACR, CRA3, 0xFF, 0x00}, /* Secondary Display Starting Address */
357{VIACR, CR69, 0xFF, 0x00},
358{VIACR, CR6A, 0xFF, 0x40},
359{VIACR, CR6B, 0xFF, 0x00},
360{VIACR, CR6C, 0xFF, 0x00},
361{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
362{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
363{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
364{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
365{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
366{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
367{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
368{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
369{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
370{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
371{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
372{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
373{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
374{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
375{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
376{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
377{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
378{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
379{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
380{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
381{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
382{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
383{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
384{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
385{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
386{VIACR, CR96, 0xFF, 0x00},
387{VIACR, CR97, 0xFF, 0x00},
388{VIACR, CR99, 0xFF, 0x00},
389{VIACR, CR9B, 0xFF, 0x00},
390{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
391};
392
393/* Video Mode Table */
394/* Common Setting for Video Mode */
395struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
396{VIASR, SR2A, 0x0F, 0x00},
397{VIASR, SR15, 0x02, 0x02},
398{VIASR, SR16, 0xBF, 0x08},
399{VIASR, SR17, 0xFF, 0x1F},
400{VIASR, SR18, 0xFF, 0x4E},
401{VIASR, SR1A, 0xFB, 0x08},
402
403{VIACR, CR32, 0xFF, 0x00},
404{VIACR, CR34, 0xFF, 0x00},
405{VIACR, CR35, 0xFF, 0x00},
406{VIACR, CR36, 0x08, 0x00},
407{VIACR, CR6A, 0xFF, 0x80},
408{VIACR, CR6A, 0xFF, 0xC0},
409
410{VIACR, CR55, 0x80, 0x00},
411{VIACR, CR5D, 0x80, 0x00},
412
413{VIAGR, GR20, 0xFF, 0x00},
414{VIAGR, GR21, 0xFF, 0x00},
415{VIAGR, GR22, 0xFF, 0x00},
416 /* LCD Parameters */
417{VIACR, CR7A, 0xFF, 0x01}, /* LCD Parameter 1 */
418{VIACR, CR7B, 0xFF, 0x02}, /* LCD Parameter 2 */
419{VIACR, CR7C, 0xFF, 0x03}, /* LCD Parameter 3 */
420{VIACR, CR7D, 0xFF, 0x04}, /* LCD Parameter 4 */
421{VIACR, CR7E, 0xFF, 0x07}, /* LCD Parameter 5 */
422{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Parameter 6 */
423{VIACR, CR80, 0xFF, 0x0D}, /* LCD Parameter 7 */
424{VIACR, CR81, 0xFF, 0x13}, /* LCD Parameter 8 */
425{VIACR, CR82, 0xFF, 0x16}, /* LCD Parameter 9 */
426{VIACR, CR83, 0xFF, 0x19}, /* LCD Parameter 10 */
427{VIACR, CR84, 0xFF, 0x1C}, /* LCD Parameter 11 */
428{VIACR, CR85, 0xFF, 0x1D}, /* LCD Parameter 12 */
429{VIACR, CR86, 0xFF, 0x1E}, /* LCD Parameter 13 */
430{VIACR, CR87, 0xFF, 0x1F}, /* LCD Parameter 14 */
431
432};
433
434/* Mode:1024X768 */
435struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
436{VIASR, 0x18, 0xFF, 0x4C}
437};
438
439struct patch_table res_patch_table[] = {
440 {VIA_RES_1024X768, ARRAY_SIZE(PM1024x768), PM1024x768}
441};
442
443/* struct VPITTable {
444 unsigned char Misc;
445 unsigned char SR[StdSR];
446 unsigned char CR[StdCR];
447 unsigned char GR[StdGR];
448 unsigned char AR[StdAR];
449 };*/
450
451struct VPITTable VPIT = {
452 /* Msic */
453 0xC7,
454 /* Sequencer */
455 {0x01, 0x0F, 0x00, 0x0E},
456 /* Graphic Controller */
457 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
458 /* Attribute Controller */
459 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
460 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
461 0x01, 0x00, 0x0F, 0x00}
462};
463
464/********************/
465/* Mode Table */
466/********************/
467
468/* 480x640 */
469struct crt_mode_table CRTM480x640[] = {
470 /* r_rate, vclk, hsp, vsp */
471 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
472 {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP,
473 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/
474};
475
476/* 640x480*/
477struct crt_mode_table CRTM640x480[] = {
478 /*r_rate,vclk,hsp,vsp */
479 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
480 {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP,
481 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
482 {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP,
483 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
484 {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP,
485 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
486 {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP,
487 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
488 {REFRESH_120, CLK_52_406M, M640X480_R120_HSP,
489 M640X480_R120_VSP,
490 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481,
491 3} } /*GTF*/
492};
493
494/*720x480 (GTF)*/
495struct crt_mode_table CRTM720x480[] = {
496 /*r_rate,vclk,hsp,vsp */
497 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
498 {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP,
499 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
500
501};
502
503/*720x576 (GTF)*/
504struct crt_mode_table CRTM720x576[] = {
505 /*r_rate,vclk,hsp,vsp */
506 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
507 {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP,
508 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
509};
510
511/* 800x480 (CVT) */
512struct crt_mode_table CRTM800x480[] = {
513 /* r_rate, vclk, hsp, vsp */
514 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
515 {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP,
516 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
517};
518
519/* 800x600*/
520struct crt_mode_table CRTM800x600[] = {
521 /*r_rate,vclk,hsp,vsp */
522 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
523 {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP,
524 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
525 {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP,
526 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
527 {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP,
528 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
529 {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP,
530 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
531 {REFRESH_120, CLK_83_950M, M800X600_R120_HSP,
532 M800X600_R120_VSP,
533 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601,
534 3} }
535};
536
537/* 848x480 (CVT) */
538struct crt_mode_table CRTM848x480[] = {
539 /* r_rate, vclk, hsp, vsp */
540 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
541 {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP,
542 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
543};
544
545/*856x480 (GTF) convert to 852x480*/
546struct crt_mode_table CRTM852x480[] = {
547 /*r_rate,vclk,hsp,vsp */
548 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
549 {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP,
550 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
551};
552
553/*1024x512 (GTF)*/
554struct crt_mode_table CRTM1024x512[] = {
555 /*r_rate,vclk,hsp,vsp */
556 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
557 {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP,
558 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
559
560};
561
562/* 1024x600*/
563struct crt_mode_table CRTM1024x600[] = {
564 /*r_rate,vclk,hsp,vsp */
565 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
566 {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP,
567 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
568};
569
570/* 1024x768*/
571struct crt_mode_table CRTM1024x768[] = {
572 /*r_rate,vclk,hsp,vsp */
573 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
574 {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP,
575 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
576 {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP,
577 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
578 {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP,
579 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
580 {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP,
581 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
582};
583
584/* 1152x864*/
585struct crt_mode_table CRTM1152x864[] = {
586 /*r_rate,vclk,hsp,vsp */
587 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
588 {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP,
589 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
590
591};
592
593/* 1280x720 (HDMI 720P)*/
594struct crt_mode_table CRTM1280x720[] = {
595 /*r_rate,vclk,hsp,vsp */
596 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
597 {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP,
598 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
599 {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP,
600 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
601};
602
603/*1280x768 (GTF)*/
604struct crt_mode_table CRTM1280x768[] = {
605 /*r_rate,vclk,hsp,vsp */
606 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
607 {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP,
608 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
609 {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP,
610 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
611};
612
613/* 1280x800 (CVT) */
614struct crt_mode_table CRTM1280x800[] = {
615 /* r_rate, vclk, hsp, vsp */
616 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
617 {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP,
618 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
619};
620
621/*1280x960*/
622struct crt_mode_table CRTM1280x960[] = {
623 /*r_rate,vclk,hsp,vsp */
624 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
625 {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP,
626 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
627};
628
629/* 1280x1024*/
630struct crt_mode_table CRTM1280x1024[] = {
631 /*r_rate,vclk,,hsp,vsp */
632 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
633 {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
634 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
635 3} },
636 {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
637 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
638 3} },
639 {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
640 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
641};
642
643/* 1368x768 (GTF) */
644struct crt_mode_table CRTM1368x768[] = {
645 /* r_rate, vclk, hsp, vsp */
646 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
647 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
648 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
649};
650
651/*1440x1050 (GTF)*/
652struct crt_mode_table CRTM1440x1050[] = {
653 /*r_rate,vclk,hsp,vsp */
654 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
655 {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
656 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
657};
658
659/* 1600x1200*/
660struct crt_mode_table CRTM1600x1200[] = {
661 /*r_rate,vclk,hsp,vsp */
662 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
663 {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
664 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
665 3} },
666 {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
667 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
668
669};
670
671/* 1680x1050 (CVT) */
672struct crt_mode_table CRTM1680x1050[] = {
673 /* r_rate, vclk, hsp, vsp */
674 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
675 {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
676 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
677 6} },
678 {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
679 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
680};
681
682/* 1680x1050 (CVT Reduce Blanking) */
683struct crt_mode_table CRTM1680x1050_RB[] = {
684 /* r_rate, vclk, hsp, vsp */
685 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
686 {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP,
687 M1680x1050_RB_R60_VSP,
688 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
689};
690
691/* 1920x1080 (CVT)*/
692struct crt_mode_table CRTM1920x1080[] = {
693 /*r_rate,vclk,hsp,vsp */
694 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
695 {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
696 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
697};
698
699/* 1920x1080 (CVT with Reduce Blanking) */
700struct crt_mode_table CRTM1920x1080_RB[] = {
701 /* r_rate, vclk, hsp, vsp */
702 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
703 {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP,
704 M1920X1080_RB_R60_VSP,
705 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
706};
707
708/* 1920x1440*/
709struct crt_mode_table CRTM1920x1440[] = {
710 /*r_rate,vclk,hsp,vsp */
711 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
712 {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
713 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
714 3} },
715 {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
716 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
717};
718
719/* 1400x1050 (CVT) */
720struct crt_mode_table CRTM1400x1050[] = {
721 /* r_rate, vclk, hsp, vsp */
722 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
723 {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
724 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
725 4} },
726 {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
727 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
728};
729
730/* 1400x1050 (CVT Reduce Blanking) */
731struct crt_mode_table CRTM1400x1050_RB[] = {
732 /* r_rate, vclk, hsp, vsp */
733 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
734 {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP,
735 M1400X1050_RB_R60_VSP,
736 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
737};
738
739/* 960x600 (CVT) */
740struct crt_mode_table CRTM960x600[] = {
741 /* r_rate, vclk, hsp, vsp */
742 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
743 {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP,
744 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
745};
746
747/* 1000x600 (GTF) */
748struct crt_mode_table CRTM1000x600[] = {
749 /* r_rate, vclk, hsp, vsp */
750 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
751 {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP,
752 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
753};
754
755/* 1024x576 (GTF) */
756struct crt_mode_table CRTM1024x576[] = {
757 /* r_rate, vclk, hsp, vsp */
758 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
759 {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP,
760 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
761};
762
763/* 1088x612 (CVT) */
764struct crt_mode_table CRTM1088x612[] = {
765 /* r_rate, vclk, hsp, vsp */
766 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
767 {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP,
768 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
769};
770
771/* 1152x720 (CVT) */
772struct crt_mode_table CRTM1152x720[] = {
773 /* r_rate, vclk, hsp, vsp */
774 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
775 {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP,
776 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
777};
778
779/* 1200x720 (GTF) */
780struct crt_mode_table CRTM1200x720[] = {
781 /* r_rate, vclk, hsp, vsp */
782 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
783 {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP,
784 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
785};
786
787/* 1280x600 (GTF) */
788struct crt_mode_table CRTM1280x600[] = {
789 /* r_rate, vclk, hsp, vsp */
790 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
791 {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP,
792 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
793};
794
795/* 1360x768 (CVT) */
796struct crt_mode_table CRTM1360x768[] = {
797 /* r_rate, vclk, hsp, vsp */
798 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
799 {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP,
800 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
801};
802
803/* 1360x768 (CVT Reduce Blanking) */
804struct crt_mode_table CRTM1360x768_RB[] = {
805 /* r_rate, vclk, hsp, vsp */
806 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
807 {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP,
808 M1360X768_RB_R60_VSP,
809 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
810};
811
812/* 1366x768 (GTF) */
813struct crt_mode_table CRTM1366x768[] = {
814 /* r_rate, vclk, hsp, vsp */
815 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
816 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
817 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
818 {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP,
819 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
820};
821
822/* 1440x900 (CVT) */
823struct crt_mode_table CRTM1440x900[] = {
824 /* r_rate, vclk, hsp, vsp */
825 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
826 {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP,
827 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
828 {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP,
829 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
830};
831
832/* 1440x900 (CVT Reduce Blanking) */
833struct crt_mode_table CRTM1440x900_RB[] = {
834 /* r_rate, vclk, hsp, vsp */
835 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
836 {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP,
837 M1440X900_RB_R60_VSP,
838 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
839};
840
841/* 1600x900 (CVT) */
842struct crt_mode_table CRTM1600x900[] = {
843 /* r_rate, vclk, hsp, vsp */
844 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
845 {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP,
846 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
847};
848
849/* 1600x900 (CVT Reduce Blanking) */
850struct crt_mode_table CRTM1600x900_RB[] = {
851 /* r_rate, vclk, hsp, vsp */
852 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
853 {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP,
854 M1600X900_RB_R60_VSP,
855 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
856};
857
858/* 1600x1024 (GTF) */
859struct crt_mode_table CRTM1600x1024[] = {
860 /* r_rate, vclk, hsp, vsp */
861 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
862 {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
863 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
864};
865
866/* 1792x1344 (DMT) */
867struct crt_mode_table CRTM1792x1344[] = {
868 /* r_rate, vclk, hsp, vsp */
869 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
870 {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
871 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
872};
873
874/* 1856x1392 (DMT) */
875struct crt_mode_table CRTM1856x1392[] = {
876 /* r_rate, vclk, hsp, vsp */
877 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
878 {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
879 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
880};
881
882/* 1920x1200 (CVT) */
883struct crt_mode_table CRTM1920x1200[] = {
884 /* r_rate, vclk, hsp, vsp */
885 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
886 {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
887 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
888};
889
890/* 1920x1200 (CVT with Reduce Blanking) */
891struct crt_mode_table CRTM1920x1200_RB[] = {
892 /* r_rate, vclk, hsp, vsp */
893 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
894 {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP,
895 M1920X1200_RB_R60_VSP,
896 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
897};
898
899/* 2048x1536 (CVT) */
900struct crt_mode_table CRTM2048x1536[] = {
901 /* r_rate, vclk, hsp, vsp */
902 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
903 {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
904 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
905};
906
907/* Video Mode Table */
908/* struct VideoModeTable {*/
909/* int ModeIndex;*/
910/* struct crt_mode_table *crtc;*/
911/* int mode_array;*/
912/* };*/
913struct VideoModeTable CLE266Modes[] = {
914 /* Display : 480x640 (GTF) */
915 {VIA_RES_480X640, CRTM480x640, ARRAY_SIZE(CRTM480x640)},
916
917 /* Display : 640x480 */
918 {VIA_RES_640X480, CRTM640x480, ARRAY_SIZE(CRTM640x480)},
919
920 /* Display : 720x480 (GTF) */
921 {VIA_RES_720X480, CRTM720x480, ARRAY_SIZE(CRTM720x480)},
922
923 /* Display : 720x576 (GTF) */
924 {VIA_RES_720X576, CRTM720x576, ARRAY_SIZE(CRTM720x576)},
925
926 /* Display : 800x600 */
927 {VIA_RES_800X600, CRTM800x600, ARRAY_SIZE(CRTM800x600)},
928
929 /* Display : 800x480 (CVT) */
930 {VIA_RES_800X480, CRTM800x480, ARRAY_SIZE(CRTM800x480)},
931
932 /* Display : 848x480 (CVT) */
933 {VIA_RES_848X480, CRTM848x480, ARRAY_SIZE(CRTM848x480)},
934
935 /* Display : 852x480 (GTF) */
936 {VIA_RES_856X480, CRTM852x480, ARRAY_SIZE(CRTM852x480)},
937
938 /* Display : 1024x512 (GTF) */
939 {VIA_RES_1024X512, CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
940
941 /* Display : 1024x600 */
942 {VIA_RES_1024X600, CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
943
944 /* Display : 1024x576 (GTF) */
945 /*{ VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, */
946
947 /* Display : 1024x768 */
948 {VIA_RES_1024X768, CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
949
950 /* Display : 1152x864 */
951 {VIA_RES_1152X864, CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
952
953 /* Display : 1280x768 (GTF) */
954 {VIA_RES_1280X768, CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
955
956 /* Display : 960x600 (CVT) */
957 {VIA_RES_960X600, CRTM960x600, ARRAY_SIZE(CRTM960x600)},
958
959 /* Display : 1000x600 (GTF) */
960 {VIA_RES_1000X600, CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
961
962 /* Display : 1024x576 (GTF) */
963 {VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
964
965 /* Display : 1088x612 (GTF) */
966 {VIA_RES_1088X612, CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
967
968 /* Display : 1152x720 (CVT) */
969 {VIA_RES_1152X720, CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
970
971 /* Display : 1200x720 (GTF) */
972 {VIA_RES_1200X720, CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
973
974 /* Display : 1280x600 (GTF) */
975 {VIA_RES_1280X600, CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
976
977 /* Display : 1280x800 (CVT) */
978 {VIA_RES_1280X800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
979
980 /* Display : 1280x800 (GTF) */
981 /*{ M1280x800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, */
982
983 /* Display : 1280x960 */
984 {VIA_RES_1280X960, CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
985
986 /* Display : 1280x1024 */
987 {VIA_RES_1280X1024, CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
988
989 /* Display : 1360x768 (CVT) */
990 {VIA_RES_1360X768, CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
991
992 /* Display : 1360x768 (CVT Reduce Blanking) */
993 {VIA_RES_1360X768_RB, CRTM1360x768_RB,
994 ARRAY_SIZE(CRTM1360x768_RB)},
995
996 /* Display : 1366x768 */
997 {VIA_RES_1366X768, CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
998
999 /* Display : 1368x768 (GTF) */
1000 /*{ M1368x768,CRTM1368x768,ARRAY_SIZE(CRTM1368x768)}, */
1001 /* Display : 1368x768 (GTF) */
1002 {VIA_RES_1368X768, CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
1003
1004 /* Display : 1440x900 (CVT) */
1005 {VIA_RES_1440X900, CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
1006
1007 /* Display : 1440x900 (CVT Reduce Blanking) */
1008 {VIA_RES_1440X900_RB, CRTM1440x900_RB,
1009 ARRAY_SIZE(CRTM1440x900_RB)},
1010
1011 /* Display : 1440x1050 (GTF) */
1012 {VIA_RES_1440X1050, CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
1013
1014 /* Display : 1400x1050 (CVT Reduce Blanking) */
1015 {VIA_RES_1400X1050_RB, CRTM1400x1050_RB,
1016 ARRAY_SIZE(CRTM1400x1050_RB)},
1017
1018 /* Display : 1600x900 (CVT) */
1019 {VIA_RES_1600X900, CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
1020
1021 /* Display : 1600x900 (CVT Reduce Blanking) */
1022 {VIA_RES_1600X900_RB, CRTM1600x900_RB,
1023 ARRAY_SIZE(CRTM1600x900_RB)},
1024
1025 /* Display : 1600x1024 (GTF) */
1026 {VIA_RES_1600X1024, CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
1027
1028 /* Display : 1600x1200 */
1029 {VIA_RES_1600X1200, CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
1030
1031 /* Display : 1680x1050 (CVT) */
1032 {VIA_RES_1680X1050, CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
1033
1034 /* Display : 1680x1050 (CVT Reduce Blanking) */
1035 {VIA_RES_1680X1050_RB, CRTM1680x1050_RB,
1036 ARRAY_SIZE(CRTM1680x1050_RB)},
1037
1038 /* Display : 1792x1344 (DMT) */
1039 {VIA_RES_1792X1344, CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
1040
1041 /* Display : 1856x1392 (DMT) */
1042 {VIA_RES_1856X1392, CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
1043
1044 /* Display : 1920x1440 */
1045 {VIA_RES_1920X1440, CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
1046
1047 /* Display : 2048x1536 */
1048 {VIA_RES_2048X1536, CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
1049
1050 /* Display : 1280x720 */
1051 {VIA_RES_1280X720, CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
1052
1053 /* Display : 1920x1080 (CVT) */
1054 {VIA_RES_1920X1080, CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
1055
1056 /* Display : 1920x1080 (CVT Reduce Blanking) */
1057 {VIA_RES_1920X1080_RB, CRTM1920x1080_RB,
1058 ARRAY_SIZE(CRTM1920x1080_RB)},
1059
1060 /* Display : 1920x1200 (CVT) */
1061 {VIA_RES_1920X1200, CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
1062
1063 /* Display : 1920x1200 (CVT Reduce Blanking) */
1064 {VIA_RES_1920X1200_RB, CRTM1920x1200_RB,
1065 ARRAY_SIZE(CRTM1920x1200_RB)},
1066
1067 /* Display : 1400x1050 (CVT) */
1068 {VIA_RES_1400X1050, CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
1069};
1070struct crt_mode_table CEAM1280x720[] = {
1071 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP,
1072 M1280X720_CEA_R60_VSP,
1073 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
1074 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
1075};
1076struct crt_mode_table CEAM1920x1080[] = {
1077 {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP,
1078 M1920X1080_CEA_R60_VSP,
1079 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
1080 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
1081};
1082struct VideoModeTable CEA_HDMI_Modes[] = {
1083 /* Display : 1280x720 */
1084 {VIA_RES_1280X720, CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
1085 {VIA_RES_1920X1080, CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
1086};
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
new file mode 100644
index 000000000000..1a5de50a23a2
--- /dev/null
+++ b/drivers/video/via/viamode.h
@@ -0,0 +1,177 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __VIAMODE_H__
23#define __VIAMODE_H__
24
25#include "global.h"
26
27struct VPITTable {
28 unsigned char Misc;
29 unsigned char SR[StdSR];
30 unsigned char GR[StdGR];
31 unsigned char AR[StdAR];
32};
33
34struct VideoModeTable {
35 int ModeIndex;
36 struct crt_mode_table *crtc;
37 int mode_array;
38};
39
40struct patch_table {
41 int mode_index;
42 int table_length;
43 struct io_reg *io_reg_table;
44};
45
46struct res_map_refresh {
47 int hres;
48 int vres;
49 int pixclock;
50 int vmode_refresh;
51};
52
53#define NUM_TOTAL_RES_MAP_REFRESH ARRAY_SIZE(res_map_refresh_tbl)
54#define NUM_TOTAL_CEA_MODES ARRAY_SIZE(CEA_HDMI_Modes)
55#define NUM_TOTAL_CN400_ModeXregs ARRAY_SIZE(CN400_ModeXregs)
56#define NUM_TOTAL_CN700_ModeXregs ARRAY_SIZE(CN700_ModeXregs)
57#define NUM_TOTAL_KM400_ModeXregs ARRAY_SIZE(KM400_ModeXregs)
58#define NUM_TOTAL_CX700_ModeXregs ARRAY_SIZE(CX700_ModeXregs)
59#define NUM_TOTAL_VX800_ModeXregs ARRAY_SIZE(VX800_ModeXregs)
60#define NUM_TOTAL_CLE266_ModeXregs ARRAY_SIZE(CLE266_ModeXregs)
61#define NUM_TOTAL_PATCH_MODE ARRAY_SIZE(res_patch_table)
62#define NUM_TOTAL_MODETABLE ARRAY_SIZE(CLE266Modes)
63
64/********************/
65/* Mode Table */
66/********************/
67
68/* 480x640 */
69extern struct crt_mode_table CRTM480x640[1];
70/* 640x480*/
71extern struct crt_mode_table CRTM640x480[5];
72/*720x480 (GTF)*/
73extern struct crt_mode_table CRTM720x480[1];
74/*720x576 (GTF)*/
75extern struct crt_mode_table CRTM720x576[1];
76/* 800x480 (CVT) */
77extern struct crt_mode_table CRTM800x480[1];
78/* 800x600*/
79extern struct crt_mode_table CRTM800x600[5];
80/* 848x480 (CVT) */
81extern struct crt_mode_table CRTM848x480[1];
82/*856x480 (GTF) convert to 852x480*/
83extern struct crt_mode_table CRTM852x480[1];
84/*1024x512 (GTF)*/
85extern struct crt_mode_table CRTM1024x512[1];
86/* 1024x600*/
87extern struct crt_mode_table CRTM1024x600[1];
88/* 1024x768*/
89extern struct crt_mode_table CRTM1024x768[4];
90/* 1152x864*/
91extern struct crt_mode_table CRTM1152x864[1];
92/* 1280x720 (HDMI 720P)*/
93extern struct crt_mode_table CRTM1280x720[2];
94/*1280x768 (GTF)*/
95extern struct crt_mode_table CRTM1280x768[2];
96/* 1280x800 (CVT) */
97extern struct crt_mode_table CRTM1280x800[1];
98/*1280x960*/
99extern struct crt_mode_table CRTM1280x960[1];
100/* 1280x1024*/
101extern struct crt_mode_table CRTM1280x1024[3];
102/* 1368x768 (GTF) */
103extern struct crt_mode_table CRTM1368x768[1];
104/*1440x1050 (GTF)*/
105extern struct crt_mode_table CRTM1440x1050[1];
106/* 1600x1200*/
107extern struct crt_mode_table CRTM1600x1200[2];
108/* 1680x1050 (CVT) */
109extern struct crt_mode_table CRTM1680x1050[2];
110/* 1680x1050 (CVT Reduce Blanking) */
111extern struct crt_mode_table CRTM1680x1050_RB[1];
112/* 1920x1080 (CVT)*/
113extern struct crt_mode_table CRTM1920x1080[1];
114/* 1920x1080 (CVT with Reduce Blanking) */
115extern struct crt_mode_table CRTM1920x1080_RB[1];
116/* 1920x1440*/
117extern struct crt_mode_table CRTM1920x1440[2];
118/* 1400x1050 (CVT) */
119extern struct crt_mode_table CRTM1400x1050[2];
120/* 1400x1050 (CVT Reduce Blanking) */
121extern struct crt_mode_table CRTM1400x1050_RB[1];
122/* 960x600 (CVT) */
123extern struct crt_mode_table CRTM960x600[1];
124/* 1000x600 (GTF) */
125extern struct crt_mode_table CRTM1000x600[1];
126/* 1024x576 (GTF) */
127extern struct crt_mode_table CRTM1024x576[1];
128/* 1088x612 (CVT) */
129extern struct crt_mode_table CRTM1088x612[1];
130/* 1152x720 (CVT) */
131extern struct crt_mode_table CRTM1152x720[1];
132/* 1200x720 (GTF) */
133extern struct crt_mode_table CRTM1200x720[1];
134/* 1280x600 (GTF) */
135extern struct crt_mode_table CRTM1280x600[1];
136/* 1360x768 (CVT) */
137extern struct crt_mode_table CRTM1360x768[1];
138/* 1360x768 (CVT Reduce Blanking) */
139extern struct crt_mode_table CRTM1360x768_RB[1];
140/* 1366x768 (GTF) */
141extern struct crt_mode_table CRTM1366x768[2];
142/* 1440x900 (CVT) */
143extern struct crt_mode_table CRTM1440x900[2];
144/* 1440x900 (CVT Reduce Blanking) */
145extern struct crt_mode_table CRTM1440x900_RB[1];
146/* 1600x900 (CVT) */
147extern struct crt_mode_table CRTM1600x900[1];
148/* 1600x900 (CVT Reduce Blanking) */
149extern struct crt_mode_table CRTM1600x900_RB[1];
150/* 1600x1024 (GTF) */
151extern struct crt_mode_table CRTM1600x1024[1];
152/* 1792x1344 (DMT) */
153extern struct crt_mode_table CRTM1792x1344[1];
154/* 1856x1392 (DMT) */
155extern struct crt_mode_table CRTM1856x1392[1];
156/* 1920x1200 (CVT) */
157extern struct crt_mode_table CRTM1920x1200[1];
158/* 1920x1200 (CVT with Reduce Blanking) */
159extern struct crt_mode_table CRTM1920x1200_RB[1];
160/* 2048x1536 (CVT) */
161extern struct crt_mode_table CRTM2048x1536[1];
162extern struct VideoModeTable CLE266Modes[47];
163extern struct crt_mode_table CEAM1280x720[1];
164extern struct crt_mode_table CEAM1920x1080[1];
165extern struct VideoModeTable CEA_HDMI_Modes[2];
166
167extern struct res_map_refresh res_map_refresh_tbl[61];
168extern struct io_reg CN400_ModeXregs[52];
169extern struct io_reg CN700_ModeXregs[66];
170extern struct io_reg KM400_ModeXregs[55];
171extern struct io_reg CX700_ModeXregs[58];
172extern struct io_reg VX800_ModeXregs[58];
173extern struct io_reg CLE266_ModeXregs[32];
174extern struct io_reg PM1024x768[2];
175extern struct patch_table res_patch_table[1];
176extern struct VPITTable VPIT;
177#endif /* __VIAMODE_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 18:45:31 -0500