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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2010-07-10 20:57:34 -0400
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2010-07-23 10:37:05 -0400
commit1f844350909fe249cf6d9722da1735e4076ff7f0 (patch)
treeddb2918562f81635e4136763f59e31e61085ad01 /drivers/video/via/hw.c
parentcc3fd679a344468e892a109b8de3e2948ce14e0f (diff)
viafb: PLL value cleanup
viafb: PLL value cleanup This is a big change of how PLL values are handled on the road to dynamic PLL value generation. The table was converted automatically in the relevant parameters for frequency generation. Sadly there were some bits set whose meaning is unknown. Those differences are documented but ignored as the unichrome code implies that they are not important (a big thanks to Luc for his amazing work). The PLL values for 31490000 and 133308000 are deleted as they were more than 5% off and not used anyway. The values for CX700@60466000 and VX855@153920000 are corrected as they were wrong and easily correctable as enough correct values was available because CX700 and VX855 support the same values only with a little difference in hardware format. All remaining values are not more than 2% off. Additionally the surrounding code is changed as needed especially the byte order of the values written to hardware to allow nicer conversion functions. This is mostly a change preparing for dynamic PLL generation and the two corrected values aside no runtime change is expected. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Joseph Chan <JosephChan@via.com.tw>
Diffstat (limited to 'drivers/video/via/hw.c')
-rw-r--r--drivers/video/via/hw.c578
1 files changed, 402 insertions, 176 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 05be8c13765e..7dcb4d5bb9c3 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -23,143 +23,341 @@
23#include "global.h" 23#include "global.h"
24 24
25static struct pll_map pll_value[] = { 25static struct pll_map pll_value[] = {
26 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, 26 {25175000,
27 CX700_25_175M, VX855_25_175M}, 27 {99, 7, 3},
28 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, 28 {85, 3, 4}, /* ignoring bit difference: 0x00008000 */
29 CX700_29_581M, VX855_29_581M}, 29 {141, 5, 4},
30 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, 30 {141, 5, 4} },
31 CX700_26_880M, VX855_26_880M}, 31 {29581000,
32 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, 32 {33, 4, 2},
33 CX700_31_490M, VX855_31_490M}, 33 {66, 2, 4}, /* ignoring bit difference: 0x00808000 */
34 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, 34 {166, 5, 4}, /* ignoring bit difference: 0x00008000 */
35 CX700_31_500M, VX855_31_500M}, 35 {165, 5, 4} },
36 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, 36 {26880000,
37 CX700_31_728M, VX855_31_728M}, 37 {15, 4, 1},
38 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, 38 {30, 2, 3}, /* ignoring bit difference: 0x00808000 */
39 CX700_32_668M, VX855_32_668M}, 39 {150, 5, 4},
40 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, 40 {150, 5, 4} },
41 CX700_36_000M, VX855_36_000M}, 41 {31500000,
42 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, 42 {53, 3, 3}, /* ignoring bit difference: 0x00008000 */
43 CX700_40_000M, VX855_40_000M}, 43 {141, 4, 4}, /* ignoring bit difference: 0x00008000 */
44 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, 44 {176, 5, 4},
45 CX700_41_291M, VX855_41_291M}, 45 {176, 5, 4} },
46 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, 46 {31728000,
47 CX700_43_163M, VX855_43_163M}, 47 {31, 7, 1},
48 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, 48 {177, 5, 4}, /* ignoring bit difference: 0x00008000 */
49 CX700_45_250M, VX855_45_250M}, 49 {177, 5, 4},
50 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, 50 {142, 4, 4} },
51 CX700_46_000M, VX855_46_000M}, 51 {32688000,
52 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, 52 {73, 4, 3},
53 CX700_46_996M, VX855_46_996M}, 53 {146, 4, 4}, /* ignoring bit difference: 0x00008000 */
54 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, 54 {183, 5, 4},
55 CX700_48_000M, VX855_48_000M}, 55 {146, 4, 4} },
56 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, 56 {36000000,
57 CX700_48_875M, VX855_48_875M}, 57 {101, 5, 3}, /* ignoring bit difference: 0x00008000 */
58 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, 58 {161, 4, 4}, /* ignoring bit difference: 0x00008000 */
59 CX700_49_500M, VX855_49_500M}, 59 {202, 5, 4},
60 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, 60 {161, 4, 4} },
61 CX700_52_406M, VX855_52_406M}, 61 {40000000,
62 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, 62 {89, 4, 3},
63 CX700_52_977M, VX855_52_977M}, 63 {89, 4, 3}, /* ignoring bit difference: 0x00008000 */
64 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, 64 {112, 5, 3},
65 CX700_56_250M, VX855_56_250M}, 65 {112, 5, 3} },
66 {CLK_57_275M, 0, 0, 0, VX855_57_275M}, 66 {41291000,
67 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, 67 {23, 4, 1},
68 CX700_60_466M, VX855_60_466M}, 68 {69, 3, 3}, /* ignoring bit difference: 0x00008000 */
69 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, 69 {115, 5, 3},
70 CX700_61_500M, VX855_61_500M}, 70 {115, 5, 3} },
71 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, 71 {43163000,
72 CX700_65_000M, VX855_65_000M}, 72 {121, 5, 3},
73 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, 73 {121, 5, 3}, /* ignoring bit difference: 0x00008000 */
74 CX700_65_178M, VX855_65_178M}, 74 {121, 5, 3},
75 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, 75 {121, 5, 3} },
76 CX700_66_750M, VX855_66_750M}, 76 {45250000,
77 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, 77 {127, 5, 3},
78 CX700_68_179M, VX855_68_179M}, 78 {127, 5, 3}, /* ignoring bit difference: 0x00808000 */
79 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, 79 {127, 5, 3},
80 CX700_69_924M, VX855_69_924M}, 80 {127, 5, 3} },
81 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, 81 {46000000,
82 CX700_70_159M, VX855_70_159M}, 82 {90, 7, 2},
83 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, 83 {103, 4, 3}, /* ignoring bit difference: 0x00008000 */
84 CX700_72_000M, VX855_72_000M}, 84 {129, 5, 3},
85 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, 85 {103, 4, 3} },
86 CX700_78_750M, VX855_78_750M}, 86 {46996000,
87 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, 87 {105, 4, 3}, /* ignoring bit difference: 0x00008000 */
88 CX700_80_136M, VX855_80_136M}, 88 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */
89 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, 89 {131, 5, 3}, /* ignoring bit difference: 0x00808000 */
90 CX700_83_375M, VX855_83_375M}, 90 {105, 4, 3} },
91 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, 91 {48000000,
92 CX700_83_950M, VX855_83_950M}, 92 {67, 20, 0},
93 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, 93 {134, 5, 3}, /* ignoring bit difference: 0x00808000 */
94 CX700_84_750M, VX855_84_750M}, 94 {134, 5, 3},
95 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, 95 {134, 5, 3} },
96 CX700_85_860M, VX855_85_860M}, 96 {48875000,
97 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, 97 {99, 29, 0},
98 CX700_88_750M, VX855_88_750M}, 98 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */
99 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, 99 {82, 3, 3}, /* ignoring bit difference: 0x00808000 */
100 CX700_94_500M, VX855_94_500M}, 100 {137, 5, 3} },
101 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, 101 {49500000,
102 CX700_97_750M, VX855_97_750M}, 102 {83, 6, 2},
103 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M, 103 {83, 3, 3}, /* ignoring bit difference: 0x00008000 */
104 CX700_101_000M, VX855_101_000M}, 104 {138, 5, 3},
105 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M, 105 {83, 3, 3} },
106 CX700_106_500M, VX855_106_500M}, 106 {52406000,
107 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M, 107 {117, 4, 3},
108 CX700_108_000M, VX855_108_000M}, 108 {117, 4, 3}, /* ignoring bit difference: 0x00008000 */
109 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M, 109 {117, 4, 3},
110 CX700_113_309M, VX855_113_309M}, 110 {88, 3, 3} },
111 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M, 111 {52977000,
112 CX700_118_840M, VX855_118_840M}, 112 {37, 5, 1},
113 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M, 113 {148, 5, 3}, /* ignoring bit difference: 0x00808000 */
114 CX700_119_000M, VX855_119_000M}, 114 {148, 5, 3},
115 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M, 115 {148, 5, 3} },
116 CX700_121_750M, 0}, 116 {56250000,
117 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M, 117 {55, 7, 1}, /* ignoring bit difference: 0x00008000 */
118 CX700_125_104M, 0}, 118 {126, 4, 3}, /* ignoring bit difference: 0x00008000 */
119 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M, 119 {157, 5, 3},
120 CX700_133_308M, 0}, 120 {157, 5, 3} },
121 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M, 121 {57275000,
122 CX700_135_000M, VX855_135_000M}, 122 {0, 0, 0},
123 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M, 123 {2, 2, 0},
124 CX700_136_700M, VX855_136_700M}, 124 {2, 2, 0},
125 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M, 125 {157, 5, 3} }, /* ignoring bit difference: 0x00808000 */
126 CX700_138_400M, VX855_138_400M}, 126 {60466000,
127 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M, 127 {76, 9, 1},
128 CX700_146_760M, VX855_146_760M}, 128 {169, 5, 3}, /* ignoring bit difference: 0x00808000 */
129 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M, 129 {169, 5, 3}, /* FIXED: old = {72, 2, 3} */
130 CX700_153_920M, VX855_153_920M}, 130 {169, 5, 3} },
131 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M, 131 {61500000,
132 CX700_156_000M, VX855_156_000M}, 132 {86, 20, 0},
133 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M, 133 {172, 5, 3}, /* ignoring bit difference: 0x00808000 */
134 CX700_157_500M, VX855_157_500M}, 134 {172, 5, 3},
135 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M, 135 {172, 5, 3} },
136 CX700_162_000M, VX855_162_000M}, 136 {65000000,
137 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M, 137 {109, 6, 2}, /* ignoring bit difference: 0x00008000 */
138 CX700_187_000M, VX855_187_000M}, 138 {109, 3, 3}, /* ignoring bit difference: 0x00008000 */
139 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M, 139 {109, 3, 3},
140 CX700_193_295M, VX855_193_295M}, 140 {109, 3, 3} },
141 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M, 141 {65178000,
142 CX700_202_500M, VX855_202_500M}, 142 {91, 5, 2},
143 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M, 143 {182, 5, 3}, /* ignoring bit difference: 0x00808000 */
144 CX700_204_000M, VX855_204_000M}, 144 {109, 3, 3},
145 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M, 145 {182, 5, 3} },
146 CX700_218_500M, VX855_218_500M}, 146 {66750000,
147 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M, 147 {75, 4, 2},
148 CX700_234_000M, VX855_234_000M}, 148 {150, 4, 3}, /* ignoring bit difference: 0x00808000 */
149 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M, 149 {150, 4, 3},
150 CX700_267_250M, VX855_267_250M}, 150 {112, 3, 3} },
151 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M, 151 {68179000,
152 CX700_297_500M, VX855_297_500M}, 152 {19, 4, 0},
153 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, 153 {114, 3, 3}, /* ignoring bit difference: 0x00008000 */
154 CX700_74_481M, VX855_74_481M}, 154 {190, 5, 3},
155 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M, 155 {191, 5, 3} },
156 CX700_172_798M, VX855_172_798M}, 156 {69924000,
157 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M, 157 {83, 17, 0},
158 CX700_122_614M, VX855_122_614M}, 158 {195, 5, 3}, /* ignoring bit difference: 0x00808000 */
159 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, 159 {195, 5, 3},
160 CX700_74_270M, 0}, 160 {195, 5, 3} },
161 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M, 161 {70159000,
162 CX700_148_500M, VX855_148_500M} 162 {98, 20, 0},
163 {196, 5, 3}, /* ignoring bit difference: 0x00808000 */
164 {196, 5, 3},
165 {195, 5, 3} },
166 {72000000,
167 {121, 24, 0},
168 {161, 4, 3}, /* ignoring bit difference: 0x00808000 */
169 {161, 4, 3},
170 {161, 4, 3} },
171 {78750000,
172 {33, 3, 1},
173 {66, 3, 2}, /* ignoring bit difference: 0x00008000 */
174 {110, 5, 2},
175 {110, 5, 2} },
176 {80136000,
177 {28, 5, 0},
178 {68, 3, 2}, /* ignoring bit difference: 0x00008000 */
179 {112, 5, 2},
180 {112, 5, 2} },
181 {83375000,
182 {93, 2, 3},
183 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */
184 {93, 4, 2}, /* ignoring bit difference: 0x00800000 */
185 {117, 5, 2} },
186 {83950000,
187 {41, 7, 0},
188 {117, 5, 2}, /* ignoring bit difference: 0x00008000 */
189 {117, 5, 2},
190 {117, 5, 2} },
191 {84750000,
192 {118, 5, 2},
193 {118, 5, 2}, /* ignoring bit difference: 0x00808000 */
194 {118, 5, 2},
195 {118, 5, 2} },
196 {85860000,
197 {84, 7, 1},
198 {120, 5, 2}, /* ignoring bit difference: 0x00808000 */
199 {120, 5, 2},
200 {118, 5, 2} },
201 {88750000,
202 {31, 5, 0},
203 {124, 5, 2}, /* ignoring bit difference: 0x00808000 */
204 {174, 7, 2}, /* ignoring bit difference: 0x00808000 */
205 {124, 5, 2} },
206 {94500000,
207 {33, 5, 0},
208 {132, 5, 2}, /* ignoring bit difference: 0x00008000 */
209 {132, 5, 2},
210 {132, 5, 2} },
211 {97750000,
212 {82, 6, 1},
213 {137, 5, 2}, /* ignoring bit difference: 0x00808000 */
214 {137, 5, 2},
215 {137, 5, 2} },
216 {101000000,
217 {127, 9, 1},
218 {141, 5, 2}, /* ignoring bit difference: 0x00808000 */
219 {141, 5, 2},
220 {141, 5, 2} },
221 {106500000,
222 {119, 4, 2},
223 {119, 4, 2}, /* ignoring bit difference: 0x00808000 */
224 {119, 4, 2},
225 {149, 5, 2} },
226 {108000000,
227 {121, 4, 2},
228 {121, 4, 2}, /* ignoring bit difference: 0x00808000 */
229 {151, 5, 2},
230 {151, 5, 2} },
231 {113309000,
232 {95, 12, 0},
233 {95, 3, 2}, /* ignoring bit difference: 0x00808000 */
234 {95, 3, 2},
235 {159, 5, 2} },
236 {118840000,
237 {83, 5, 1},
238 {166, 5, 2}, /* ignoring bit difference: 0x00808000 */
239 {166, 5, 2},
240 {166, 5, 2} },
241 {119000000,
242 {108, 13, 0},
243 {133, 4, 2}, /* ignoring bit difference: 0x00808000 */
244 {133, 4, 2},
245 {167, 5, 2} },
246 {121750000,
247 {85, 5, 1},
248 {170, 5, 2}, /* ignoring bit difference: 0x00808000 */
249 {68, 2, 2},
250 {0, 0, 0} },
251 {125104000,
252 {53, 6, 0}, /* ignoring bit difference: 0x00008000 */
253 {106, 3, 2}, /* ignoring bit difference: 0x00008000 */
254 {175, 5, 2},
255 {0, 0, 0} },
256 {135000000,
257 {94, 5, 1},
258 {28, 3, 0}, /* ignoring bit difference: 0x00804000 */
259 {151, 4, 2},
260 {189, 5, 2} },
261 {136700000,
262 {115, 12, 0},
263 {191, 5, 2}, /* ignoring bit difference: 0x00808000 */
264 {191, 5, 2},
265 {191, 5, 2} },
266 {138400000,
267 {87, 9, 0},
268 {116, 3, 2}, /* ignoring bit difference: 0x00808000 */
269 {116, 3, 2},
270 {194, 5, 2} },
271 {146760000,
272 {103, 5, 1},
273 {206, 5, 2}, /* ignoring bit difference: 0x00808000 */
274 {206, 5, 2},
275 {206, 5, 2} },
276 {153920000,
277 {86, 8, 0},
278 {86, 4, 1}, /* ignoring bit difference: 0x00808000 */
279 {86, 4, 1},
280 {86, 4, 1} }, /* FIXED: old = {84, 2, 1} */
281 {156000000,
282 {109, 5, 1},
283 {109, 5, 1}, /* ignoring bit difference: 0x00808000 */
284 {109, 5, 1},
285 {108, 5, 1} },
286 {157500000,
287 {55, 5, 0}, /* ignoring bit difference: 0x00008000 */
288 {22, 2, 0}, /* ignoring bit difference: 0x00802000 */
289 {110, 5, 1},
290 {110, 5, 1} },
291 {162000000,
292 {113, 5, 1},
293 {113, 5, 1}, /* ignoring bit difference: 0x00808000 */
294 {113, 5, 1},
295 {113, 5, 1} },
296 {187000000,
297 {118, 9, 0},
298 {131, 5, 1}, /* ignoring bit difference: 0x00808000 */
299 {131, 5, 1},
300 {131, 5, 1} },
301 {193295000,
302 {108, 8, 0},
303 {81, 3, 1}, /* ignoring bit difference: 0x00808000 */
304 {135, 5, 1},
305 {135, 5, 1} },
306 {202500000,
307 {99, 7, 0},
308 {85, 3, 1}, /* ignoring bit difference: 0x00808000 */
309 {142, 5, 1},
310 {142, 5, 1} },
311 {204000000,
312 {100, 7, 0},
313 {143, 5, 1}, /* ignoring bit difference: 0x00808000 */
314 {143, 5, 1},
315 {143, 5, 1} },
316 {218500000,
317 {92, 6, 0},
318 {153, 5, 1}, /* ignoring bit difference: 0x00808000 */
319 {153, 5, 1},
320 {153, 5, 1} },
321 {234000000,
322 {98, 6, 0},
323 {98, 3, 1}, /* ignoring bit difference: 0x00008000 */
324 {98, 3, 1},
325 {164, 5, 1} },
326 {267250000,
327 {112, 6, 0},
328 {112, 3, 1}, /* ignoring bit difference: 0x00808000 */
329 {187, 5, 1},
330 {187, 5, 1} },
331 {297500000,
332 {102, 5, 0}, /* ignoring bit difference: 0x00008000 */
333 {166, 4, 1}, /* ignoring bit difference: 0x00008000 */
334 {208, 5, 1},
335 {208, 5, 1} },
336 {74481000,
337 {26, 5, 0},
338 {125, 3, 3}, /* ignoring bit difference: 0x00808000 */
339 {208, 5, 3},
340 {209, 5, 3} },
341 {172798000,
342 {121, 5, 1},
343 {121, 5, 1}, /* ignoring bit difference: 0x00808000 */
344 {121, 5, 1},
345 {121, 5, 1} },
346 {122614000,
347 {60, 7, 0},
348 {137, 4, 2}, /* ignoring bit difference: 0x00808000 */
349 {137, 4, 2},
350 {172, 5, 2} },
351 {74270000,
352 {83, 8, 1},
353 {208, 5, 3},
354 {208, 5, 3},
355 {0, 0, 0} },
356 {148500000,
357 {83, 8, 0},
358 {208, 5, 2},
359 {166, 4, 2},
360 {208, 5, 2} }
163}; 361};
164 362
165static struct fifo_depth_select display_fifo_depth_reg = { 363static struct fifo_depth_select display_fifo_depth_reg = {
@@ -1360,40 +1558,70 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1360 1558
1361} 1559}
1362 1560
1561static u32 cle266_encode_pll(struct pll_config pll)
1562{
1563 return (pll.multiplier << 8)
1564 | (pll.rshift << 6)
1565 | pll.divisor;
1566}
1567
1568static u32 k800_encode_pll(struct pll_config pll)
1569{
1570 return ((pll.divisor - 2) << 16)
1571 | (pll.rshift << 10)
1572 | (pll.multiplier - 2);
1573}
1574
1575static u32 vx855_encode_pll(struct pll_config pll)
1576{
1577 return (pll.divisor << 16)
1578 | (pll.rshift << 10)
1579 | pll.multiplier;
1580}
1581
1363u32 viafb_get_clk_value(int clk) 1582u32 viafb_get_clk_value(int clk)
1364{ 1583{
1365 int i; 1584 u32 value = 0;
1585 int i = 0;
1366 1586
1367 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) { 1587 while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1368 if (clk == pll_value[i].clk) { 1588 i++;
1369 switch (viaparinfo->chip_info->gfx_chip_name) { 1589
1370 case UNICHROME_CLE266: 1590 if (i == NUM_TOTAL_PLL_TABLE) {
1371 case UNICHROME_K400: 1591 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1372 return pll_value[i].cle266_pll; 1592 } else {
1373 1593 switch (viaparinfo->chip_info->gfx_chip_name) {
1374 case UNICHROME_K800: 1594 case UNICHROME_CLE266:
1375 case UNICHROME_PM800: 1595 case UNICHROME_K400:
1376 case UNICHROME_CN700: 1596 value = cle266_encode_pll(pll_value[i].cle266_pll);
1377 return pll_value[i].k800_pll; 1597 break;
1378 1598
1379 case UNICHROME_CX700: 1599 case UNICHROME_K800:
1380 case UNICHROME_K8M890: 1600 case UNICHROME_PM800:
1381 case UNICHROME_P4M890: 1601 case UNICHROME_CN700:
1382 case UNICHROME_P4M900: 1602 value = k800_encode_pll(pll_value[i].k800_pll);
1383 case UNICHROME_VX800: 1603 break;
1384 return pll_value[i].cx700_pll; 1604
1385 case UNICHROME_VX855: 1605 case UNICHROME_CX700:
1386 return pll_value[i].vx855_pll; 1606 case UNICHROME_CN750:
1387 } 1607 case UNICHROME_K8M890:
1608 case UNICHROME_P4M890:
1609 case UNICHROME_P4M900:
1610 case UNICHROME_VX800:
1611 value = k800_encode_pll(pll_value[i].cx700_pll);
1612 break;
1613
1614 case UNICHROME_VX855:
1615 value = vx855_encode_pll(pll_value[i].vx855_pll);
1616 break;
1388 } 1617 }
1389 } 1618 }
1390 1619
1391 DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n"); 1620 return value;
1392 return 0;
1393} 1621}
1394 1622
1395/* Set VCLK*/ 1623/* Set VCLK*/
1396void viafb_set_vclock(u32 CLK, int set_iga) 1624void viafb_set_vclock(u32 clk, int set_iga)
1397{ 1625{
1398 /* H.W. Reset : ON */ 1626 /* H.W. Reset : ON */
1399 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); 1627 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
@@ -1403,26 +1631,23 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1403 switch (viaparinfo->chip_info->gfx_chip_name) { 1631 switch (viaparinfo->chip_info->gfx_chip_name) {
1404 case UNICHROME_CLE266: 1632 case UNICHROME_CLE266:
1405 case UNICHROME_K400: 1633 case UNICHROME_K400:
1406 viafb_write_reg(SR46, VIASR, CLK / 0x100); 1634 via_write_reg(VIASR, SR46, (clk & 0x00FF));
1407 viafb_write_reg(SR47, VIASR, CLK % 0x100); 1635 via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1408 break; 1636 break;
1409 1637
1410 case UNICHROME_K800: 1638 case UNICHROME_K800:
1411 case UNICHROME_PM800: 1639 case UNICHROME_PM800:
1412 case UNICHROME_CN700: 1640 case UNICHROME_CN700:
1413 case UNICHROME_CX700: 1641 case UNICHROME_CX700:
1642 case UNICHROME_CN750:
1414 case UNICHROME_K8M890: 1643 case UNICHROME_K8M890:
1415 case UNICHROME_P4M890: 1644 case UNICHROME_P4M890:
1416 case UNICHROME_P4M900: 1645 case UNICHROME_P4M900:
1417 case UNICHROME_VX800: 1646 case UNICHROME_VX800:
1418 case UNICHROME_VX855: 1647 case UNICHROME_VX855:
1419 viafb_write_reg(SR44, VIASR, CLK / 0x10000); 1648 via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1420 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000); 1649 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1421 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100); 1650 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1422 DEBUG_MSG(KERN_INFO "\nSR45=%x",
1423 (CLK & 0xFFFF) / 0x100);
1424 viafb_write_reg(SR46, VIASR, CLK % 0x100);
1425 DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1426 break; 1651 break;
1427 } 1652 }
1428 } 1653 }
@@ -1432,22 +1657,23 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1432 switch (viaparinfo->chip_info->gfx_chip_name) { 1657 switch (viaparinfo->chip_info->gfx_chip_name) {
1433 case UNICHROME_CLE266: 1658 case UNICHROME_CLE266:
1434 case UNICHROME_K400: 1659 case UNICHROME_K400:
1435 viafb_write_reg(SR44, VIASR, CLK / 0x100); 1660 via_write_reg(VIASR, SR44, (clk & 0x00FF));
1436 viafb_write_reg(SR45, VIASR, CLK % 0x100); 1661 via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1437 break; 1662 break;
1438 1663
1439 case UNICHROME_K800: 1664 case UNICHROME_K800:
1440 case UNICHROME_PM800: 1665 case UNICHROME_PM800:
1441 case UNICHROME_CN700: 1666 case UNICHROME_CN700:
1442 case UNICHROME_CX700: 1667 case UNICHROME_CX700:
1668 case UNICHROME_CN750:
1443 case UNICHROME_K8M890: 1669 case UNICHROME_K8M890:
1444 case UNICHROME_P4M890: 1670 case UNICHROME_P4M890:
1445 case UNICHROME_P4M900: 1671 case UNICHROME_P4M900:
1446 case UNICHROME_VX800: 1672 case UNICHROME_VX800:
1447 case UNICHROME_VX855: 1673 case UNICHROME_VX855:
1448 viafb_write_reg(SR4A, VIASR, CLK / 0x10000); 1674 via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1449 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100); 1675 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1450 viafb_write_reg(SR4C, VIASR, CLK % 0x100); 1676 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1451 break; 1677 break;
1452 } 1678 }
1453 } 1679 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 22:11:13 -0500