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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2010-10-24 00:02:14 -0400
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2010-10-24 09:04:55 -0400
commit51f4332bb5fef869e8a89895a7bac6b4c03b4946 (patch)
treeeb505244dcfa4a20f30cf1da47c04f9bc4efcdd7 /drivers/video/via/hw.c
parentadac8d65f399b02e8a2222fc75c658e4b8d24f65 (diff)
viafb: add initial VX900 support
This patch adds basic support for the new VX900 IGP. Almost everything that was implemented for other IGPs is expected to work also on VX900 after this patch. The only known issue is that on the CRT output mode setting does not always work. It is clear that the possibility for regressions is zero. A big thanks to VIA Technologies for making this possible and supporting this work. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Joseph Chan <JosephChan@via.com.tw> Cc: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'drivers/video/via/hw.c')
-rw-r--r--drivers/video/via/hw.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 7d7010acf148..36d73f940d8b 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -1429,6 +1429,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1429 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; 1429 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1430 } 1430 }
1431 1431
1432 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1433 iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH;
1434 iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD;
1435 iga1_fifo_high_threshold =
1436 VX900_IGA1_FIFO_HIGH_THRESHOLD;
1437 iga1_display_queue_expire_num =
1438 VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1439 }
1440
1432 /* Set Display FIFO Depath Select */ 1441 /* Set Display FIFO Depath Select */
1433 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); 1442 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1434 viafb_load_reg_num = 1443 viafb_load_reg_num =
@@ -1569,6 +1578,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1569 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; 1578 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1570 } 1579 }
1571 1580
1581 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1582 iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH;
1583 iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD;
1584 iga2_fifo_high_threshold =
1585 VX900_IGA2_FIFO_HIGH_THRESHOLD;
1586 iga2_display_queue_expire_num =
1587 VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1588 }
1589
1572 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { 1590 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1573 /* Set Display FIFO Depath Select */ 1591 /* Set Display FIFO Depath Select */
1574 reg_value = 1592 reg_value =
@@ -1689,6 +1707,7 @@ u32 viafb_get_clk_value(int clk)
1689 break; 1707 break;
1690 1708
1691 case UNICHROME_VX855: 1709 case UNICHROME_VX855:
1710 case UNICHROME_VX900:
1692 value = vx855_encode_pll(pll_value[i].vx855_pll); 1711 value = vx855_encode_pll(pll_value[i].vx855_pll);
1693 break; 1712 break;
1694 } 1713 }
@@ -1722,6 +1741,7 @@ void viafb_set_vclock(u32 clk, int set_iga)
1722 case UNICHROME_P4M900: 1741 case UNICHROME_P4M900:
1723 case UNICHROME_VX800: 1742 case UNICHROME_VX800:
1724 case UNICHROME_VX855: 1743 case UNICHROME_VX855:
1744 case UNICHROME_VX900:
1725 via_write_reg(VIASR, SR44, (clk & 0x0000FF)); 1745 via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1726 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8); 1746 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1727 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16); 1747 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
@@ -1748,6 +1768,7 @@ void viafb_set_vclock(u32 clk, int set_iga)
1748 case UNICHROME_P4M900: 1768 case UNICHROME_P4M900:
1749 case UNICHROME_VX800: 1769 case UNICHROME_VX800:
1750 case UNICHROME_VX855: 1770 case UNICHROME_VX855:
1771 case UNICHROME_VX900:
1751 via_write_reg(VIASR, SR4A, (clk & 0x0000FF)); 1772 via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1752 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8); 1773 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1753 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16); 1774 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
@@ -2179,6 +2200,7 @@ static void __devinit init_gfx_chip_info(int chip_type)
2179 switch (viaparinfo->chip_info->gfx_chip_name) { 2200 switch (viaparinfo->chip_info->gfx_chip_name) {
2180 case UNICHROME_VX800: 2201 case UNICHROME_VX800:
2181 case UNICHROME_VX855: 2202 case UNICHROME_VX855:
2203 case UNICHROME_VX900:
2182 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1; 2204 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2183 break; 2205 break;
2184 case UNICHROME_K8M890: 2206 case UNICHROME_K8M890:
@@ -2403,6 +2425,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2403 break; 2425 break;
2404 2426
2405 case UNICHROME_VX855: 2427 case UNICHROME_VX855:
2428 case UNICHROME_VX900:
2406 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs); 2429 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2407 break; 2430 break;
2408 } 2431 }