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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/sa1100fb.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/video/sa1100fb.c')
-rw-r--r--drivers/video/sa1100fb.c1574
1 files changed, 1574 insertions, 0 deletions
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
new file mode 100644
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+++ b/drivers/video/sa1100fb.c
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1/*
2 * linux/drivers/video/sa1100fb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas
5 * Based on acornfb.c Copyright (C) Russell King.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * StrongARM 1100 LCD Controller Frame Buffer Driver
12 *
13 * Please direct your questions and comments on this driver to the following
14 * email address:
15 *
16 * linux-arm-kernel@lists.arm.linux.org.uk
17 *
18 * Clean patches should be sent to the ARM Linux Patch System. Please see the
19 * following web page for more information:
20 *
21 * http://www.arm.linux.org.uk/developer/patches/info.shtml
22 *
23 * Thank you.
24 *
25 * Known problems:
26 * - With the Neponset plugged into an Assabet, LCD powerdown
27 * doesn't work (LCD stays powered up). Therefore we shouldn't
28 * blank the screen.
29 * - We don't limit the CPU clock rate nor the mode selection
30 * according to the available SDRAM bandwidth.
31 *
32 * Other notes:
33 * - Linear grayscale palettes and the kernel.
34 * Such code does not belong in the kernel. The kernel frame buffer
35 * drivers do not expect a linear colourmap, but a colourmap based on
36 * the VT100 standard mapping.
37 *
38 * If your _userspace_ requires a linear colourmap, then the setup of
39 * such a colourmap belongs _in userspace_, not in the kernel. Code
40 * to set the colourmap correctly from user space has been sent to
41 * David Neuer. It's around 8 lines of C code, plus another 4 to
42 * detect if we are using grayscale.
43 *
44 * - The following must never be specified in a panel definition:
45 * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
46 *
47 * - The following should be specified:
48 * either LCCR0_Color or LCCR0_Mono
49 * either LCCR0_Sngl or LCCR0_Dual
50 * either LCCR0_Act or LCCR0_Pas
51 * either LCCR3_OutEnH or LCCD3_OutEnL
52 * either LCCR3_PixRsEdg or LCCR3_PixFlEdg
53 * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
54 *
55 * Code Status:
56 * 1999/04/01:
57 * - Driver appears to be working for Brutus 320x200x8bpp mode. Other
58 * resolutions are working, but only the 8bpp mode is supported.
59 * Changes need to be made to the palette encode and decode routines
60 * to support 4 and 16 bpp modes.
61 * Driver is not designed to be a module. The FrameBuffer is statically
62 * allocated since dynamic allocation of a 300k buffer cannot be
63 * guaranteed.
64 *
65 * 1999/06/17:
66 * - FrameBuffer memory is now allocated at run-time when the
67 * driver is initialized.
68 *
69 * 2000/04/10: Nicolas Pitre <nico@cam.org>
70 * - Big cleanup for dynamic selection of machine type at run time.
71 *
72 * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
73 * - Support for Bitsy aka Compaq iPAQ H3600 added.
74 *
75 * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
76 * Jeff Sutherland <jsutherland@accelent.com>
77 * - Resolved an issue caused by a change made to the Assabet's PLD
78 * earlier this year which broke the framebuffer driver for newer
79 * Phase 4 Assabets. Some other parameters were changed to optimize
80 * for the Sharp display.
81 *
82 * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
83 * - XP860 support added
84 *
85 * 2000/08/19: Mark Huang <mhuang@livetoy.com>
86 * - Allows standard options to be passed on the kernel command line
87 * for most common passive displays.
88 *
89 * 2000/08/29:
90 * - s/save_flags_cli/local_irq_save/
91 * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
92 *
93 * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
94 * - Updated LART stuff. Fixed some minor bugs.
95 *
96 * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
97 * - Pangolin support added
98 *
99 * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
100 * - Huw Webpanel support added
101 *
102 * 2000/11/23: Eric Peng <ericpeng@coventive.com>
103 * - Freebird add
104 *
105 * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com>
106 * Cliff Brake <cbrake@accelent.com>
107 * - Added PM callback
108 *
109 * 2001/05/26: <rmk@arm.linux.org.uk>
110 * - Fix 16bpp so that (a) we use the right colours rather than some
111 * totally random colour depending on what was in page 0, and (b)
112 * we don't de-reference a NULL pointer.
113 * - remove duplicated implementation of consistent_alloc()
114 * - convert dma address types to dma_addr_t
115 * - remove unused 'montype' stuff
116 * - remove redundant zero inits of init_var after the initial
117 * memzero.
118 * - remove allow_modeset (acornfb idea does not belong here)
119 *
120 * 2001/05/28: <rmk@arm.linux.org.uk>
121 * - massive cleanup - move machine dependent data into structures
122 * - I've left various #warnings in - if you see one, and know
123 * the hardware concerned, please get in contact with me.
124 *
125 * 2001/05/31: <rmk@arm.linux.org.uk>
126 * - Fix LCCR1 HSW value, fix all machine type specifications to
127 * keep values in line. (Please check your machine type specs)
128 *
129 * 2001/06/10: <rmk@arm.linux.org.uk>
130 * - Fiddle with the LCD controller from task context only; mainly
131 * so that we can run with interrupts on, and sleep.
132 * - Convert #warnings into #errors. No pain, no gain. ;)
133 *
134 * 2001/06/14: <rmk@arm.linux.org.uk>
135 * - Make the palette BPS value for 12bpp come out correctly.
136 * - Take notice of "greyscale" on any colour depth.
137 * - Make truecolor visuals use the RGB channel encoding information.
138 *
139 * 2001/07/02: <rmk@arm.linux.org.uk>
140 * - Fix colourmap problems.
141 *
142 * 2001/07/13: <abraham@2d3d.co.za>
143 * - Added support for the ICP LCD-Kit01 on LART. This LCD is
144 * manufactured by Prime View, model no V16C6448AB
145 *
146 * 2001/07/23: <rmk@arm.linux.org.uk>
147 * - Hand merge version from handhelds.org CVS tree. See patch
148 * notes for 595/1 for more information.
149 * - Drop 12bpp (it's 16bpp with different colour register mappings).
150 * - This hardware can not do direct colour. Therefore we don't
151 * support it.
152 *
153 * 2001/07/27: <rmk@arm.linux.org.uk>
154 * - Halve YRES on dual scan LCDs.
155 *
156 * 2001/08/22: <rmk@arm.linux.org.uk>
157 * - Add b/w iPAQ pixclock value.
158 *
159 * 2001/10/12: <rmk@arm.linux.org.uk>
160 * - Add patch 681/1 and clean up stork definitions.
161 */
162
163#include <linux/config.h>
164#include <linux/module.h>
165#include <linux/kernel.h>
166#include <linux/sched.h>
167#include <linux/errno.h>
168#include <linux/string.h>
169#include <linux/interrupt.h>
170#include <linux/slab.h>
171#include <linux/fb.h>
172#include <linux/delay.h>
173#include <linux/init.h>
174#include <linux/ioport.h>
175#include <linux/cpufreq.h>
176#include <linux/device.h>
177#include <linux/dma-mapping.h>
178
179#include <asm/hardware.h>
180#include <asm/io.h>
181#include <asm/irq.h>
182#include <asm/mach-types.h>
183#include <asm/uaccess.h>
184#include <asm/arch/assabet.h>
185#include <asm/arch/shannon.h>
186
187/*
188 * debugging?
189 */
190#define DEBUG 0
191/*
192 * Complain if VAR is out of range.
193 */
194#define DEBUG_VAR 1
195
196#undef ASSABET_PAL_VIDEO
197
198#include "sa1100fb.h"
199
200extern void (*sa1100fb_backlight_power)(int on);
201extern void (*sa1100fb_lcd_power)(int on);
202
203/*
204 * IMHO this looks wrong. In 8BPP, length should be 8.
205 */
206static struct sa1100fb_rgb rgb_8 = {
207 .red = { .offset = 0, .length = 4, },
208 .green = { .offset = 0, .length = 4, },
209 .blue = { .offset = 0, .length = 4, },
210 .transp = { .offset = 0, .length = 0, },
211};
212
213static struct sa1100fb_rgb def_rgb_16 = {
214 .red = { .offset = 11, .length = 5, },
215 .green = { .offset = 5, .length = 6, },
216 .blue = { .offset = 0, .length = 5, },
217 .transp = { .offset = 0, .length = 0, },
218};
219
220#ifdef CONFIG_SA1100_ASSABET
221#ifndef ASSABET_PAL_VIDEO
222/*
223 * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
224 * takes an RGB666 signal, but we provide it with an RGB565 signal
225 * instead (def_rgb_16).
226 */
227static struct sa1100fb_mach_info lq039q2ds54_info __initdata = {
228 .pixclock = 171521, .bpp = 16,
229 .xres = 320, .yres = 240,
230
231 .hsync_len = 5, .vsync_len = 1,
232 .left_margin = 61, .upper_margin = 3,
233 .right_margin = 9, .lower_margin = 0,
234
235 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
236
237 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
238 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
239};
240#else
241static struct sa1100fb_mach_info pal_info __initdata = {
242 .pixclock = 67797, .bpp = 16,
243 .xres = 640, .yres = 512,
244
245 .hsync_len = 64, .vsync_len = 6,
246 .left_margin = 125, .upper_margin = 70,
247 .right_margin = 115, .lower_margin = 36,
248
249 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
250 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
251};
252#endif
253#endif
254
255#ifdef CONFIG_SA1100_H3800
256static struct sa1100fb_mach_info h3800_info __initdata = {
257 .pixclock = 174757, .bpp = 16,
258 .xres = 320, .yres = 240,
259
260 .hsync_len = 3, .vsync_len = 3,
261 .left_margin = 12, .upper_margin = 10,
262 .right_margin = 17, .lower_margin = 1,
263
264 .cmap_static = 1,
265
266 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
267 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
268};
269#endif
270
271#ifdef CONFIG_SA1100_H3600
272static struct sa1100fb_mach_info h3600_info __initdata = {
273 .pixclock = 174757, .bpp = 16,
274 .xres = 320, .yres = 240,
275
276 .hsync_len = 3, .vsync_len = 3,
277 .left_margin = 12, .upper_margin = 10,
278 .right_margin = 17, .lower_margin = 1,
279
280 .cmap_static = 1,
281
282 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
283 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
284};
285
286static struct sa1100fb_rgb h3600_rgb_16 = {
287 .red = { .offset = 12, .length = 4, },
288 .green = { .offset = 7, .length = 4, },
289 .blue = { .offset = 1, .length = 4, },
290 .transp = { .offset = 0, .length = 0, },
291};
292#endif
293
294#ifdef CONFIG_SA1100_H3100
295static struct sa1100fb_mach_info h3100_info __initdata = {
296 .pixclock = 406977, .bpp = 4,
297 .xres = 320, .yres = 240,
298
299 .hsync_len = 26, .vsync_len = 41,
300 .left_margin = 4, .upper_margin = 0,
301 .right_margin = 4, .lower_margin = 0,
302
303 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
304 .cmap_greyscale = 1,
305 .cmap_inverse = 1,
306
307 .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
308 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
309};
310#endif
311
312#ifdef CONFIG_SA1100_COLLIE
313static struct sa1100fb_mach_info collie_info __initdata = {
314 .pixclock = 171521, .bpp = 16,
315 .xres = 320, .yres = 240,
316
317 .hsync_len = 5, .vsync_len = 1,
318 .left_margin = 11, .upper_margin = 2,
319 .right_margin = 30, .lower_margin = 0,
320
321 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
322
323 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
324 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
325};
326#endif
327
328#ifdef LART_GREY_LCD
329static struct sa1100fb_mach_info lart_grey_info __initdata = {
330 .pixclock = 150000, .bpp = 4,
331 .xres = 320, .yres = 240,
332
333 .hsync_len = 1, .vsync_len = 1,
334 .left_margin = 4, .upper_margin = 0,
335 .right_margin = 2, .lower_margin = 0,
336
337 .cmap_greyscale = 1,
338 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
339
340 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
341 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
342};
343#endif
344#ifdef LART_COLOR_LCD
345static struct sa1100fb_mach_info lart_color_info __initdata = {
346 .pixclock = 150000, .bpp = 16,
347 .xres = 320, .yres = 240,
348
349 .hsync_len = 2, .vsync_len = 3,
350 .left_margin = 69, .upper_margin = 14,
351 .right_margin = 8, .lower_margin = 4,
352
353 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
354 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
355};
356#endif
357#ifdef LART_VIDEO_OUT
358static struct sa1100fb_mach_info lart_video_info __initdata = {
359 .pixclock = 39721, .bpp = 16,
360 .xres = 640, .yres = 480,
361
362 .hsync_len = 95, .vsync_len = 2,
363 .left_margin = 40, .upper_margin = 32,
364 .right_margin = 24, .lower_margin = 11,
365
366 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
367
368 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
369 .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
370};
371#endif
372
373#ifdef LART_KIT01_LCD
374static struct sa1100fb_mach_info lart_kit01_info __initdata = {
375 .pixclock = 63291, .bpp = 16,
376 .xres = 640, .yres = 480,
377
378 .hsync_len = 64, .vsync_len = 3,
379 .left_margin = 122, .upper_margin = 45,
380 .right_margin = 10, .lower_margin = 10,
381
382 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
383 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
384};
385#endif
386
387#ifdef CONFIG_SA1100_SHANNON
388static struct sa1100fb_mach_info shannon_info __initdata = {
389 .pixclock = 152500, .bpp = 8,
390 .xres = 640, .yres = 480,
391
392 .hsync_len = 4, .vsync_len = 3,
393 .left_margin = 2, .upper_margin = 0,
394 .right_margin = 1, .lower_margin = 0,
395
396 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
397
398 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
399 .lccr3 = LCCR3_ACBsDiv(512),
400};
401#endif
402
403
404
405static struct sa1100fb_mach_info * __init
406sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
407{
408 struct sa1100fb_mach_info *inf = NULL;
409
410 /*
411 * R G B T
412 * default {11,5}, { 5,6}, { 0,5}, { 0,0}
413 * h3600 {12,4}, { 7,4}, { 1,4}, { 0,0}
414 * freebird { 8,4}, { 4,4}, { 0,4}, {12,4}
415 */
416#ifdef CONFIG_SA1100_ASSABET
417 if (machine_is_assabet()) {
418#ifndef ASSABET_PAL_VIDEO
419 inf = &lq039q2ds54_info;
420#else
421 inf = &pal_info;
422#endif
423 }
424#endif
425#ifdef CONFIG_SA1100_H3100
426 if (machine_is_h3100()) {
427 inf = &h3100_info;
428 }
429#endif
430#ifdef CONFIG_SA1100_H3600
431 if (machine_is_h3600()) {
432 inf = &h3600_info;
433 fbi->rgb[RGB_16] = &h3600_rgb_16;
434 }
435#endif
436#ifdef CONFIG_SA1100_H3800
437 if (machine_is_h3800()) {
438 inf = &h3800_info;
439 }
440#endif
441#ifdef CONFIG_SA1100_COLLIE
442 if (machine_is_collie()) {
443 inf = &collie_info;
444 }
445#endif
446#ifdef CONFIG_SA1100_LART
447 if (machine_is_lart()) {
448#ifdef LART_GREY_LCD
449 inf = &lart_grey_info;
450#endif
451#ifdef LART_COLOR_LCD
452 inf = &lart_color_info;
453#endif
454#ifdef LART_VIDEO_OUT
455 inf = &lart_video_info;
456#endif
457#ifdef LART_KIT01_LCD
458 inf = &lart_kit01_info;
459#endif
460 }
461#endif
462#ifdef CONFIG_SA1100_SHANNON
463 if (machine_is_shannon()) {
464 inf = &shannon_info;
465 }
466#endif
467 return inf;
468}
469
470static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
471static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
472
473static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
474{
475 unsigned long flags;
476
477 local_irq_save(flags);
478 /*
479 * We need to handle two requests being made at the same time.
480 * There are two important cases:
481 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
482 * We must perform the unblanking, which will do our REENABLE for us.
483 * 2. When we are blanking, but immediately unblank before we have
484 * blanked. We do the "REENABLE" thing here as well, just to be sure.
485 */
486 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
487 state = (u_int) -1;
488 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
489 state = C_REENABLE;
490
491 if (state != (u_int)-1) {
492 fbi->task_state = state;
493 schedule_work(&fbi->task);
494 }
495 local_irq_restore(flags);
496}
497
498static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
499{
500 chan &= 0xffff;
501 chan >>= 16 - bf->length;
502 return chan << bf->offset;
503}
504
505/*
506 * Convert bits-per-pixel to a hardware palette PBS value.
507 */
508static inline u_int palette_pbs(struct fb_var_screeninfo *var)
509{
510 int ret = 0;
511 switch (var->bits_per_pixel) {
512 case 4: ret = 0 << 12; break;
513 case 8: ret = 1 << 12; break;
514 case 16: ret = 2 << 12; break;
515 }
516 return ret;
517}
518
519static int
520sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
521 u_int trans, struct fb_info *info)
522{
523 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
524 u_int val, ret = 1;
525
526 if (regno < fbi->palette_size) {
527 val = ((red >> 4) & 0xf00);
528 val |= ((green >> 8) & 0x0f0);
529 val |= ((blue >> 12) & 0x00f);
530
531 if (regno == 0)
532 val |= palette_pbs(&fbi->fb.var);
533
534 fbi->palette_cpu[regno] = val;
535 ret = 0;
536 }
537 return ret;
538}
539
540static int
541sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
542 u_int trans, struct fb_info *info)
543{
544 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
545 unsigned int val;
546 int ret = 1;
547
548 /*
549 * If inverse mode was selected, invert all the colours
550 * rather than the register number. The register number
551 * is what you poke into the framebuffer to produce the
552 * colour you requested.
553 */
554 if (fbi->cmap_inverse) {
555 red = 0xffff - red;
556 green = 0xffff - green;
557 blue = 0xffff - blue;
558 }
559
560 /*
561 * If greyscale is true, then we convert the RGB value
562 * to greyscale no mater what visual we are using.
563 */
564 if (fbi->fb.var.grayscale)
565 red = green = blue = (19595 * red + 38470 * green +
566 7471 * blue) >> 16;
567
568 switch (fbi->fb.fix.visual) {
569 case FB_VISUAL_TRUECOLOR:
570 /*
571 * 12 or 16-bit True Colour. We encode the RGB value
572 * according to the RGB bitfield information.
573 */
574 if (regno < 16) {
575 u32 *pal = fbi->fb.pseudo_palette;
576
577 val = chan_to_field(red, &fbi->fb.var.red);
578 val |= chan_to_field(green, &fbi->fb.var.green);
579 val |= chan_to_field(blue, &fbi->fb.var.blue);
580
581 pal[regno] = val;
582 ret = 0;
583 }
584 break;
585
586 case FB_VISUAL_STATIC_PSEUDOCOLOR:
587 case FB_VISUAL_PSEUDOCOLOR:
588 ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
589 break;
590 }
591
592 return ret;
593}
594
595/*
596 * sa1100fb_display_dma_period()
597 * Calculate the minimum period (in picoseconds) between two DMA
598 * requests for the LCD controller. If we hit this, it means we're
599 * doing nothing but LCD DMA.
600 */
601static unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
602{
603 /*
604 * Period = pixclock * bits_per_byte * bytes_per_transfer
605 * / memory_bits_per_pixel;
606 */
607 return var->pixclock * 8 * 16 / var->bits_per_pixel;
608}
609
610/*
611 * sa1100fb_check_var():
612 * Round up in the following order: bits_per_pixel, xres,
613 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
614 * bitfields, horizontal timing, vertical timing.
615 */
616static int
617sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
618{
619 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
620 int rgbidx;
621
622 if (var->xres < MIN_XRES)
623 var->xres = MIN_XRES;
624 if (var->yres < MIN_YRES)
625 var->yres = MIN_YRES;
626 if (var->xres > fbi->max_xres)
627 var->xres = fbi->max_xres;
628 if (var->yres > fbi->max_yres)
629 var->yres = fbi->max_yres;
630 var->xres_virtual = max(var->xres_virtual, var->xres);
631 var->yres_virtual = max(var->yres_virtual, var->yres);
632
633 DPRINTK("var->bits_per_pixel=%d\n", var->bits_per_pixel);
634 switch (var->bits_per_pixel) {
635 case 4:
636 rgbidx = RGB_8;
637 break;
638 case 8:
639 rgbidx = RGB_8;
640 break;
641 case 16:
642 rgbidx = RGB_16;
643 break;
644 default:
645 return -EINVAL;
646 }
647
648 /*
649 * Copy the RGB parameters for this display
650 * from the machine specific parameters.
651 */
652 var->red = fbi->rgb[rgbidx]->red;
653 var->green = fbi->rgb[rgbidx]->green;
654 var->blue = fbi->rgb[rgbidx]->blue;
655 var->transp = fbi->rgb[rgbidx]->transp;
656
657 DPRINTK("RGBT length = %d:%d:%d:%d\n",
658 var->red.length, var->green.length, var->blue.length,
659 var->transp.length);
660
661 DPRINTK("RGBT offset = %d:%d:%d:%d\n",
662 var->red.offset, var->green.offset, var->blue.offset,
663 var->transp.offset);
664
665#ifdef CONFIG_CPU_FREQ
666 printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz\n",
667 sa1100fb_display_dma_period(var),
668 cpufreq_get(smp_processor_id()));
669#endif
670
671 return 0;
672}
673
674static inline void sa1100fb_set_truecolor(u_int is_true_color)
675{
676 if (machine_is_assabet()) {
677#if 1 // phase 4 or newer Assabet's
678 if (is_true_color)
679 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
680 else
681 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
682#else
683 // older Assabet's
684 if (is_true_color)
685 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
686 else
687 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
688#endif
689 }
690}
691
692/*
693 * sa1100fb_set_par():
694 * Set the user defined part of the display for the specified console
695 */
696static int sa1100fb_set_par(struct fb_info *info)
697{
698 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
699 struct fb_var_screeninfo *var = &info->var;
700 unsigned long palette_mem_size;
701
702 DPRINTK("set_par\n");
703
704 if (var->bits_per_pixel == 16)
705 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
706 else if (!fbi->cmap_static)
707 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
708 else {
709 /*
710 * Some people have weird ideas about wanting static
711 * pseudocolor maps. I suspect their user space
712 * applications are broken.
713 */
714 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
715 }
716
717 fbi->fb.fix.line_length = var->xres_virtual *
718 var->bits_per_pixel / 8;
719 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
720
721 palette_mem_size = fbi->palette_size * sizeof(u16);
722
723 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
724
725 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
726 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
727
728 /*
729 * Set (any) board control register to handle new color depth
730 */
731 sa1100fb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
732 sa1100fb_activate_var(var, fbi);
733
734 return 0;
735}
736
737#if 0
738static int
739sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
740 struct fb_info *info)
741{
742 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
743
744 /*
745 * Make sure the user isn't doing something stupid.
746 */
747 if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->cmap_static))
748 return -EINVAL;
749
750 return gen_set_cmap(cmap, kspc, con, info);
751}
752#endif
753
754/*
755 * Formal definition of the VESA spec:
756 * On
757 * This refers to the state of the display when it is in full operation
758 * Stand-By
759 * This defines an optional operating state of minimal power reduction with
760 * the shortest recovery time
761 * Suspend
762 * This refers to a level of power management in which substantial power
763 * reduction is achieved by the display. The display can have a longer
764 * recovery time from this state than from the Stand-by state
765 * Off
766 * This indicates that the display is consuming the lowest level of power
767 * and is non-operational. Recovery from this state may optionally require
768 * the user to manually power on the monitor
769 *
770 * Now, the fbdev driver adds an additional state, (blank), where they
771 * turn off the video (maybe by colormap tricks), but don't mess with the
772 * video itself: think of it semantically between on and Stand-By.
773 *
774 * So here's what we should do in our fbdev blank routine:
775 *
776 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
777 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
778 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
779 * VESA_POWERDOWN (mode 3) Video off, front/back light off
780 *
781 * This will match the matrox implementation.
782 */
783/*
784 * sa1100fb_blank():
785 * Blank the display by setting all palette values to zero. Note, the
786 * 12 and 16 bpp modes don't really use the palette, so this will not
787 * blank the display in all modes.
788 */
789static int sa1100fb_blank(int blank, struct fb_info *info)
790{
791 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
792 int i;
793
794 DPRINTK("sa1100fb_blank: blank=%d\n", blank);
795
796 switch (blank) {
797 case FB_BLANK_POWERDOWN:
798 case FB_BLANK_VSYNC_SUSPEND:
799 case FB_BLANK_HSYNC_SUSPEND:
800 case FB_BLANK_NORMAL:
801 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
802 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
803 for (i = 0; i < fbi->palette_size; i++)
804 sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
805 sa1100fb_schedule_work(fbi, C_DISABLE);
806 break;
807
808 case FB_BLANK_UNBLANK:
809 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
810 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
811 fb_set_cmap(&fbi->fb.cmap, info);
812 sa1100fb_schedule_work(fbi, C_ENABLE);
813 }
814 return 0;
815}
816
817static int sa1100fb_mmap(struct fb_info *info, struct file *file,
818 struct vm_area_struct *vma)
819{
820 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
821 unsigned long start, len, off = vma->vm_pgoff << PAGE_SHIFT;
822
823 if (off < info->fix.smem_len) {
824 vma->vm_pgoff += 1; /* skip over the palette */
825 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
826 fbi->map_dma, fbi->map_size);
827 }
828
829 start = info->fix.mmio_start;
830 len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.mmio_len);
831
832 if ((vma->vm_end - vma->vm_start + off) > len)
833 return -EINVAL;
834
835 off += start & PAGE_MASK;
836 vma->vm_pgoff = off >> PAGE_SHIFT;
837 vma->vm_flags |= VM_IO;
838 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
839 return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
840 vma->vm_end - vma->vm_start,
841 vma->vm_page_prot);
842}
843
844static struct fb_ops sa1100fb_ops = {
845 .owner = THIS_MODULE,
846 .fb_check_var = sa1100fb_check_var,
847 .fb_set_par = sa1100fb_set_par,
848// .fb_set_cmap = sa1100fb_set_cmap,
849 .fb_setcolreg = sa1100fb_setcolreg,
850 .fb_fillrect = cfb_fillrect,
851 .fb_copyarea = cfb_copyarea,
852 .fb_imageblit = cfb_imageblit,
853 .fb_blank = sa1100fb_blank,
854 .fb_cursor = soft_cursor,
855 .fb_mmap = sa1100fb_mmap,
856};
857
858/*
859 * Calculate the PCD value from the clock rate (in picoseconds).
860 * We take account of the PPCR clock setting.
861 */
862static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock)
863{
864 unsigned int pcd = cpuclock / 100;
865
866 pcd *= pixclock;
867 pcd /= 10000000;
868
869 return pcd + 1; /* make up for integer math truncations */
870}
871
872/*
873 * sa1100fb_activate_var():
874 * Configures LCD Controller based on entries in var parameter. Settings are
875 * only written to the controller if changes were made.
876 */
877static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
878{
879 struct sa1100fb_lcd_reg new_regs;
880 u_int half_screen_size, yres, pcd;
881 u_long flags;
882
883 DPRINTK("Configuring SA1100 LCD\n");
884
885 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
886 var->xres, var->hsync_len,
887 var->left_margin, var->right_margin);
888 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
889 var->yres, var->vsync_len,
890 var->upper_margin, var->lower_margin);
891
892#if DEBUG_VAR
893 if (var->xres < 16 || var->xres > 1024)
894 printk(KERN_ERR "%s: invalid xres %d\n",
895 fbi->fb.fix.id, var->xres);
896 if (var->hsync_len < 1 || var->hsync_len > 64)
897 printk(KERN_ERR "%s: invalid hsync_len %d\n",
898 fbi->fb.fix.id, var->hsync_len);
899 if (var->left_margin < 1 || var->left_margin > 255)
900 printk(KERN_ERR "%s: invalid left_margin %d\n",
901 fbi->fb.fix.id, var->left_margin);
902 if (var->right_margin < 1 || var->right_margin > 255)
903 printk(KERN_ERR "%s: invalid right_margin %d\n",
904 fbi->fb.fix.id, var->right_margin);
905 if (var->yres < 1 || var->yres > 1024)
906 printk(KERN_ERR "%s: invalid yres %d\n",
907 fbi->fb.fix.id, var->yres);
908 if (var->vsync_len < 1 || var->vsync_len > 64)
909 printk(KERN_ERR "%s: invalid vsync_len %d\n",
910 fbi->fb.fix.id, var->vsync_len);
911 if (var->upper_margin < 0 || var->upper_margin > 255)
912 printk(KERN_ERR "%s: invalid upper_margin %d\n",
913 fbi->fb.fix.id, var->upper_margin);
914 if (var->lower_margin < 0 || var->lower_margin > 255)
915 printk(KERN_ERR "%s: invalid lower_margin %d\n",
916 fbi->fb.fix.id, var->lower_margin);
917#endif
918
919 new_regs.lccr0 = fbi->lccr0 |
920 LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
921 LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
922
923 new_regs.lccr1 =
924 LCCR1_DisWdth(var->xres) +
925 LCCR1_HorSnchWdth(var->hsync_len) +
926 LCCR1_BegLnDel(var->left_margin) +
927 LCCR1_EndLnDel(var->right_margin);
928
929 /*
930 * If we have a dual scan LCD, then we need to halve
931 * the YRES parameter.
932 */
933 yres = var->yres;
934 if (fbi->lccr0 & LCCR0_Dual)
935 yres /= 2;
936
937 new_regs.lccr2 =
938 LCCR2_DisHght(yres) +
939 LCCR2_VrtSnchWdth(var->vsync_len) +
940 LCCR2_BegFrmDel(var->upper_margin) +
941 LCCR2_EndFrmDel(var->lower_margin);
942
943 pcd = get_pcd(var->pixclock, cpufreq_get(0));
944 new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->lccr3 |
945 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
946 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
947
948 DPRINTK("nlccr0 = 0x%08lx\n", new_regs.lccr0);
949 DPRINTK("nlccr1 = 0x%08lx\n", new_regs.lccr1);
950 DPRINTK("nlccr2 = 0x%08lx\n", new_regs.lccr2);
951 DPRINTK("nlccr3 = 0x%08lx\n", new_regs.lccr3);
952
953 half_screen_size = var->bits_per_pixel;
954 half_screen_size = half_screen_size * var->xres * var->yres / 16;
955
956 /* Update shadow copy atomically */
957 local_irq_save(flags);
958 fbi->dbar1 = fbi->palette_dma;
959 fbi->dbar2 = fbi->screen_dma + half_screen_size;
960
961 fbi->reg_lccr0 = new_regs.lccr0;
962 fbi->reg_lccr1 = new_regs.lccr1;
963 fbi->reg_lccr2 = new_regs.lccr2;
964 fbi->reg_lccr3 = new_regs.lccr3;
965 local_irq_restore(flags);
966
967 /*
968 * Only update the registers if the controller is enabled
969 * and something has changed.
970 */
971 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
972 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
973 (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
974 sa1100fb_schedule_work(fbi, C_REENABLE);
975
976 return 0;
977}
978
979/*
980 * NOTE! The following functions are purely helpers for set_ctrlr_state.
981 * Do not call them directly; set_ctrlr_state does the correct serialisation
982 * to ensure that things happen in the right way 100% of time time.
983 * -- rmk
984 */
985static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
986{
987 DPRINTK("backlight o%s\n", on ? "n" : "ff");
988
989 if (sa1100fb_backlight_power)
990 sa1100fb_backlight_power(on);
991}
992
993static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
994{
995 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
996
997 if (sa1100fb_lcd_power)
998 sa1100fb_lcd_power(on);
999}
1000
1001static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
1002{
1003 u_int mask = 0;
1004
1005 /*
1006 * Enable GPIO<9:2> for LCD use if:
1007 * 1. Active display, or
1008 * 2. Color Dual Passive display
1009 *
1010 * see table 11.8 on page 11-27 in the SA1100 manual
1011 * -- Erik.
1012 *
1013 * SA1110 spec update nr. 25 says we can and should
1014 * clear LDD15 to 12 for 4 or 8bpp modes with active
1015 * panels.
1016 */
1017 if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
1018 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
1019 mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
1020
1021 if (fbi->fb.var.bits_per_pixel > 8 ||
1022 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
1023 mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
1024
1025 }
1026
1027 if (mask) {
1028 GPDR |= mask;
1029 GAFR |= mask;
1030 }
1031}
1032
1033static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
1034{
1035 DPRINTK("Enabling LCD controller\n");
1036
1037 /*
1038 * Make sure the mode bits are present in the first palette entry
1039 */
1040 fbi->palette_cpu[0] &= 0xcfff;
1041 fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
1042
1043 /* Sequence from 11.7.10 */
1044 LCCR3 = fbi->reg_lccr3;
1045 LCCR2 = fbi->reg_lccr2;
1046 LCCR1 = fbi->reg_lccr1;
1047 LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
1048 DBAR1 = fbi->dbar1;
1049 DBAR2 = fbi->dbar2;
1050 LCCR0 |= LCCR0_LEN;
1051
1052 if (machine_is_shannon()) {
1053 GPDR |= SHANNON_GPIO_DISP_EN;
1054 GPSR |= SHANNON_GPIO_DISP_EN;
1055 }
1056
1057 DPRINTK("DBAR1 = 0x%08x\n", DBAR1);
1058 DPRINTK("DBAR2 = 0x%08x\n", DBAR2);
1059 DPRINTK("LCCR0 = 0x%08x\n", LCCR0);
1060 DPRINTK("LCCR1 = 0x%08x\n", LCCR1);
1061 DPRINTK("LCCR2 = 0x%08x\n", LCCR2);
1062 DPRINTK("LCCR3 = 0x%08x\n", LCCR3);
1063}
1064
1065static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
1066{
1067 DECLARE_WAITQUEUE(wait, current);
1068
1069 DPRINTK("Disabling LCD controller\n");
1070
1071 if (machine_is_shannon()) {
1072 GPCR |= SHANNON_GPIO_DISP_EN;
1073 }
1074
1075 set_current_state(TASK_UNINTERRUPTIBLE);
1076 add_wait_queue(&fbi->ctrlr_wait, &wait);
1077
1078 LCSR = 0xffffffff; /* Clear LCD Status Register */
1079 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
1080 LCCR0 &= ~LCCR0_LEN; /* Disable LCD Controller */
1081
1082 schedule_timeout(20 * HZ / 1000);
1083 remove_wait_queue(&fbi->ctrlr_wait, &wait);
1084}
1085
1086/*
1087 * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
1088 */
1089static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
1090{
1091 struct sa1100fb_info *fbi = dev_id;
1092 unsigned int lcsr = LCSR;
1093
1094 if (lcsr & LCSR_LDD) {
1095 LCCR0 |= LCCR0_LDM;
1096 wake_up(&fbi->ctrlr_wait);
1097 }
1098
1099 LCSR = lcsr;
1100 return IRQ_HANDLED;
1101}
1102
1103/*
1104 * This function must be called from task context only, since it will
1105 * sleep when disabling the LCD controller, or if we get two contending
1106 * processes trying to alter state.
1107 */
1108static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
1109{
1110 u_int old_state;
1111
1112 down(&fbi->ctrlr_sem);
1113
1114 old_state = fbi->state;
1115
1116 /*
1117 * Hack around fbcon initialisation.
1118 */
1119 if (old_state == C_STARTUP && state == C_REENABLE)
1120 state = C_ENABLE;
1121
1122 switch (state) {
1123 case C_DISABLE_CLKCHANGE:
1124 /*
1125 * Disable controller for clock change. If the
1126 * controller is already disabled, then do nothing.
1127 */
1128 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1129 fbi->state = state;
1130 sa1100fb_disable_controller(fbi);
1131 }
1132 break;
1133
1134 case C_DISABLE_PM:
1135 case C_DISABLE:
1136 /*
1137 * Disable controller
1138 */
1139 if (old_state != C_DISABLE) {
1140 fbi->state = state;
1141
1142 __sa1100fb_backlight_power(fbi, 0);
1143 if (old_state != C_DISABLE_CLKCHANGE)
1144 sa1100fb_disable_controller(fbi);
1145 __sa1100fb_lcd_power(fbi, 0);
1146 }
1147 break;
1148
1149 case C_ENABLE_CLKCHANGE:
1150 /*
1151 * Enable the controller after clock change. Only
1152 * do this if we were disabled for the clock change.
1153 */
1154 if (old_state == C_DISABLE_CLKCHANGE) {
1155 fbi->state = C_ENABLE;
1156 sa1100fb_enable_controller(fbi);
1157 }
1158 break;
1159
1160 case C_REENABLE:
1161 /*
1162 * Re-enable the controller only if it was already
1163 * enabled. This is so we reprogram the control
1164 * registers.
1165 */
1166 if (old_state == C_ENABLE) {
1167 sa1100fb_disable_controller(fbi);
1168 sa1100fb_setup_gpio(fbi);
1169 sa1100fb_enable_controller(fbi);
1170 }
1171 break;
1172
1173 case C_ENABLE_PM:
1174 /*
1175 * Re-enable the controller after PM. This is not
1176 * perfect - think about the case where we were doing
1177 * a clock change, and we suspended half-way through.
1178 */
1179 if (old_state != C_DISABLE_PM)
1180 break;
1181 /* fall through */
1182
1183 case C_ENABLE:
1184 /*
1185 * Power up the LCD screen, enable controller, and
1186 * turn on the backlight.
1187 */
1188 if (old_state != C_ENABLE) {
1189 fbi->state = C_ENABLE;
1190 sa1100fb_setup_gpio(fbi);
1191 __sa1100fb_lcd_power(fbi, 1);
1192 sa1100fb_enable_controller(fbi);
1193 __sa1100fb_backlight_power(fbi, 1);
1194 }
1195 break;
1196 }
1197 up(&fbi->ctrlr_sem);
1198}
1199
1200/*
1201 * Our LCD controller task (which is called when we blank or unblank)
1202 * via keventd.
1203 */
1204static void sa1100fb_task(void *dummy)
1205{
1206 struct sa1100fb_info *fbi = dummy;
1207 u_int state = xchg(&fbi->task_state, -1);
1208
1209 set_ctrlr_state(fbi, state);
1210}
1211
1212#ifdef CONFIG_CPU_FREQ
1213/*
1214 * Calculate the minimum DMA period over all displays that we own.
1215 * This, together with the SDRAM bandwidth defines the slowest CPU
1216 * frequency that can be selected.
1217 */
1218static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi)
1219{
1220#if 0
1221 unsigned int min_period = (unsigned int)-1;
1222 int i;
1223
1224 for (i = 0; i < MAX_NR_CONSOLES; i++) {
1225 struct display *disp = &fb_display[i];
1226 unsigned int period;
1227
1228 /*
1229 * Do we own this display?
1230 */
1231 if (disp->fb_info != &fbi->fb)
1232 continue;
1233
1234 /*
1235 * Ok, calculate its DMA period
1236 */
1237 period = sa1100fb_display_dma_period(&disp->var);
1238 if (period < min_period)
1239 min_period = period;
1240 }
1241
1242 return min_period;
1243#else
1244 /*
1245 * FIXME: we need to verify _all_ consoles.
1246 */
1247 return sa1100fb_display_dma_period(&fbi->fb.var);
1248#endif
1249}
1250
1251/*
1252 * CPU clock speed change handler. We need to adjust the LCD timing
1253 * parameters when the CPU clock is adjusted by the power management
1254 * subsystem.
1255 */
1256static int
1257sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
1258 void *data)
1259{
1260 struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
1261 struct cpufreq_freqs *f = data;
1262 u_int pcd;
1263
1264 switch (val) {
1265 case CPUFREQ_PRECHANGE:
1266 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1267 break;
1268
1269 case CPUFREQ_POSTCHANGE:
1270 pcd = get_pcd(fbi->fb.var.pixclock, f->new);
1271 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1272 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1273 break;
1274 }
1275 return 0;
1276}
1277
1278static int
1279sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val,
1280 void *data)
1281{
1282 struct sa1100fb_info *fbi = TO_INF(nb, freq_policy);
1283 struct cpufreq_policy *policy = data;
1284
1285 switch (val) {
1286 case CPUFREQ_ADJUST:
1287 case CPUFREQ_INCOMPATIBLE:
1288 printk(KERN_DEBUG "min dma period: %d ps, "
1289 "new clock %d kHz\n", sa1100fb_min_dma_period(fbi),
1290 policy->max);
1291 /* todo: fill in min/max values */
1292 break;
1293 case CPUFREQ_NOTIFY:
1294 do {} while(0);
1295 /* todo: panic if min/max values aren't fulfilled
1296 * [can't really happen unless there's a bug in the
1297 * CPU policy verififcation process *
1298 */
1299 break;
1300 }
1301 return 0;
1302}
1303#endif
1304
1305#ifdef CONFIG_PM
1306/*
1307 * Power management hooks. Note that we won't be called from IRQ context,
1308 * unlike the blank functions above, so we may sleep.
1309 */
1310static int sa1100fb_suspend(struct device *dev, u32 state, u32 level)
1311{
1312 struct sa1100fb_info *fbi = dev_get_drvdata(dev);
1313
1314 if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
1315 set_ctrlr_state(fbi, C_DISABLE_PM);
1316 return 0;
1317}
1318
1319static int sa1100fb_resume(struct device *dev, u32 level)
1320{
1321 struct sa1100fb_info *fbi = dev_get_drvdata(dev);
1322
1323 if (level == RESUME_ENABLE)
1324 set_ctrlr_state(fbi, C_ENABLE_PM);
1325 return 0;
1326}
1327#else
1328#define sa1100fb_suspend NULL
1329#define sa1100fb_resume NULL
1330#endif
1331
1332/*
1333 * sa1100fb_map_video_memory():
1334 * Allocates the DRAM memory for the frame buffer. This buffer is
1335 * remapped into a non-cached, non-buffered, memory region to
1336 * allow palette and pixel writes to occur without flushing the
1337 * cache. Once this area is remapped, all virtual memory
1338 * access to the video memory should occur at the new region.
1339 */
1340static int __init sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
1341{
1342 /*
1343 * We reserve one page for the palette, plus the size
1344 * of the framebuffer.
1345 */
1346 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1347 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1348 &fbi->map_dma, GFP_KERNEL);
1349
1350 if (fbi->map_cpu) {
1351 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1352 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1353 /*
1354 * FIXME: this is actually the wrong thing to place in
1355 * smem_start. But fbdev suffers from the problem that
1356 * it needs an API which doesn't exist (in this case,
1357 * dma_writecombine_mmap)
1358 */
1359 fbi->fb.fix.smem_start = fbi->screen_dma;
1360 }
1361
1362 return fbi->map_cpu ? 0 : -ENOMEM;
1363}
1364
1365/* Fake monspecs to fill in fbinfo structure */
1366static struct fb_monspecs monspecs __initdata = {
1367 .hfmin = 30000,
1368 .hfmax = 70000,
1369 .vfmin = 50,
1370 .vfmax = 65,
1371};
1372
1373
1374static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev)
1375{
1376 struct sa1100fb_mach_info *inf;
1377 struct sa1100fb_info *fbi;
1378
1379 fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16,
1380 GFP_KERNEL);
1381 if (!fbi)
1382 return NULL;
1383
1384 memset(fbi, 0, sizeof(struct sa1100fb_info));
1385 fbi->dev = dev;
1386
1387 strcpy(fbi->fb.fix.id, SA1100_NAME);
1388
1389 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1390 fbi->fb.fix.type_aux = 0;
1391 fbi->fb.fix.xpanstep = 0;
1392 fbi->fb.fix.ypanstep = 0;
1393 fbi->fb.fix.ywrapstep = 0;
1394 fbi->fb.fix.accel = FB_ACCEL_NONE;
1395
1396 fbi->fb.var.nonstd = 0;
1397 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1398 fbi->fb.var.height = -1;
1399 fbi->fb.var.width = -1;
1400 fbi->fb.var.accel_flags = 0;
1401 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1402
1403 fbi->fb.fbops = &sa1100fb_ops;
1404 fbi->fb.flags = FBINFO_DEFAULT;
1405 fbi->fb.monspecs = monspecs;
1406 fbi->fb.pseudo_palette = (fbi + 1);
1407
1408 fbi->rgb[RGB_8] = &rgb_8;
1409 fbi->rgb[RGB_16] = &def_rgb_16;
1410
1411 inf = sa1100fb_get_machine_info(fbi);
1412
1413 /*
1414 * People just don't seem to get this. We don't support
1415 * anything but correct entries now, so panic if someone
1416 * does something stupid.
1417 */
1418 if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
1419 inf->pixclock == 0)
1420 panic("sa1100fb error: invalid LCCR3 fields set or zero "
1421 "pixclock.");
1422
1423 fbi->max_xres = inf->xres;
1424 fbi->fb.var.xres = inf->xres;
1425 fbi->fb.var.xres_virtual = inf->xres;
1426 fbi->max_yres = inf->yres;
1427 fbi->fb.var.yres = inf->yres;
1428 fbi->fb.var.yres_virtual = inf->yres;
1429 fbi->max_bpp = inf->bpp;
1430 fbi->fb.var.bits_per_pixel = inf->bpp;
1431 fbi->fb.var.pixclock = inf->pixclock;
1432 fbi->fb.var.hsync_len = inf->hsync_len;
1433 fbi->fb.var.left_margin = inf->left_margin;
1434 fbi->fb.var.right_margin = inf->right_margin;
1435 fbi->fb.var.vsync_len = inf->vsync_len;
1436 fbi->fb.var.upper_margin = inf->upper_margin;
1437 fbi->fb.var.lower_margin = inf->lower_margin;
1438 fbi->fb.var.sync = inf->sync;
1439 fbi->fb.var.grayscale = inf->cmap_greyscale;
1440 fbi->cmap_inverse = inf->cmap_inverse;
1441 fbi->cmap_static = inf->cmap_static;
1442 fbi->lccr0 = inf->lccr0;
1443 fbi->lccr3 = inf->lccr3;
1444 fbi->state = C_STARTUP;
1445 fbi->task_state = (u_char)-1;
1446 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1447 fbi->max_bpp / 8;
1448
1449 init_waitqueue_head(&fbi->ctrlr_wait);
1450 INIT_WORK(&fbi->task, sa1100fb_task, fbi);
1451 init_MUTEX(&fbi->ctrlr_sem);
1452
1453 return fbi;
1454}
1455
1456static int __init sa1100fb_probe(struct device *dev)
1457{
1458 struct sa1100fb_info *fbi;
1459 int ret;
1460
1461 if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
1462 return -EBUSY;
1463
1464 fbi = sa1100fb_init_fbinfo(dev);
1465 ret = -ENOMEM;
1466 if (!fbi)
1467 goto failed;
1468
1469 /* Initialize video memory */
1470 ret = sa1100fb_map_video_memory(fbi);
1471 if (ret)
1472 goto failed;
1473
1474 ret = request_irq(IRQ_LCD, sa1100fb_handle_irq, SA_INTERRUPT,
1475 "LCD", fbi);
1476 if (ret) {
1477 printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
1478 goto failed;
1479 }
1480
1481#ifdef ASSABET_PAL_VIDEO
1482 if (machine_is_assabet())
1483 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
1484#endif
1485
1486 /*
1487 * This makes sure that our colour bitfield
1488 * descriptors are correctly initialised.
1489 */
1490 sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
1491
1492 dev_set_drvdata(dev, fbi);
1493
1494 ret = register_framebuffer(&fbi->fb);
1495 if (ret < 0)
1496 goto failed;
1497
1498#ifdef CONFIG_CPU_FREQ
1499 fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
1500 fbi->freq_policy.notifier_call = sa1100fb_freq_policy;
1501 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1502 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1503#endif
1504
1505 /* This driver cannot be unloaded at the moment */
1506 return 0;
1507
1508failed:
1509 dev_set_drvdata(dev, NULL);
1510 kfree(fbi);
1511 release_mem_region(0xb0100000, 0x10000);
1512 return ret;
1513}
1514
1515static struct device_driver sa1100fb_driver = {
1516 .name = "sa11x0-fb",
1517 .bus = &platform_bus_type,
1518 .probe = sa1100fb_probe,
1519 .suspend = sa1100fb_suspend,
1520 .resume = sa1100fb_resume,
1521};
1522
1523int __init sa1100fb_init(void)
1524{
1525 if (fb_get_options("sa1100fb", NULL))
1526 return -ENODEV;
1527
1528 return driver_register(&sa1100fb_driver);
1529}
1530
1531int __init sa1100fb_setup(char *options)
1532{
1533#if 0
1534 char *this_opt;
1535
1536 if (!options || !*options)
1537 return 0;
1538
1539 while ((this_opt = strsep(&options, ",")) != NULL) {
1540
1541 if (!strncmp(this_opt, "bpp:", 4))
1542 current_par.max_bpp =
1543 simple_strtoul(this_opt + 4, NULL, 0);
1544
1545 if (!strncmp(this_opt, "lccr0:", 6))
1546 lcd_shadow.lccr0 =
1547 simple_strtoul(this_opt + 6, NULL, 0);
1548 if (!strncmp(this_opt, "lccr1:", 6)) {
1549 lcd_shadow.lccr1 =
1550 simple_strtoul(this_opt + 6, NULL, 0);
1551 current_par.max_xres =
1552 (lcd_shadow.lccr1 & 0x3ff) + 16;
1553 }
1554 if (!strncmp(this_opt, "lccr2:", 6)) {
1555 lcd_shadow.lccr2 =
1556 simple_strtoul(this_opt + 6, NULL, 0);
1557 current_par.max_yres =
1558 (lcd_shadow.
1559 lccr0 & LCCR0_SDS) ? ((lcd_shadow.
1560 lccr2 & 0x3ff) +
1561 1) *
1562 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
1563 }
1564 if (!strncmp(this_opt, "lccr3:", 6))
1565 lcd_shadow.lccr3 =
1566 simple_strtoul(this_opt + 6, NULL, 0);
1567 }
1568#endif
1569 return 0;
1570}
1571
1572module_init(sa1100fb_init);
1573MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
1574MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 11:06:13 -0500