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authorDavid Miller <davem@davemloft.net>2011-01-11 18:51:08 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-03-22 02:47:03 -0400
commitd907ec04cc498e11e039e0fff8eb58cf01e885da (patch)
treee6c2f96da0807b3a4bdf60dc4c1d4c323b0fa519 /drivers/video/s3fb.c
parenta4ade83948e0ffc317b8227d92107271a0acdda5 (diff)
svga: Make svga_wseq_mask() take an iomem regbase pointer.
Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/video/s3fb.c')
-rw-r--r--drivers/video/s3fb.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c
index f37c38bbe879..efe77b683bfa 100644
--- a/drivers/video/s3fb.c
+++ b/drivers/video/s3fb.c
@@ -510,7 +510,7 @@ static int s3fb_set_par(struct fb_info *info)
510 svga_wcrt_mask(0x11, 0x00, 0x80); 510 svga_wcrt_mask(0x11, 0x00, 0x80);
511 511
512 /* Blank screen and turn off sync */ 512 /* Blank screen and turn off sync */
513 svga_wseq_mask(0x01, 0x20, 0x20); 513 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
514 svga_wcrt_mask(0x17, 0x00, 0x80); 514 svga_wcrt_mask(0x17, 0x00, 0x80);
515 515
516 /* Set default values */ 516 /* Set default values */
@@ -700,8 +700,8 @@ static int s3fb_set_par(struct fb_info *info)
700 } 700 }
701 701
702 if (par->chip != CHIP_988_VIRGE_VX) { 702 if (par->chip != CHIP_988_VIRGE_VX) {
703 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10); 703 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
704 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80); 704 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
705 } 705 }
706 706
707 s3_set_pixclock(info, info->var.pixclock); 707 s3_set_pixclock(info, info->var.pixclock);
@@ -718,7 +718,7 @@ static int s3fb_set_par(struct fb_info *info)
718 memset_io(info->screen_base, 0x00, screen_size); 718 memset_io(info->screen_base, 0x00, screen_size);
719 /* Device and screen back on */ 719 /* Device and screen back on */
720 svga_wcrt_mask(0x17, 0x80, 0x80); 720 svga_wcrt_mask(0x17, 0x80, 0x80);
721 svga_wseq_mask(0x01, 0x00, 0x20); 721 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
722 722
723 return 0; 723 return 0;
724} 724}
@@ -788,31 +788,33 @@ static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
788 788
789static int s3fb_blank(int blank_mode, struct fb_info *info) 789static int s3fb_blank(int blank_mode, struct fb_info *info)
790{ 790{
791 struct s3fb_info *par = info->par;
792
791 switch (blank_mode) { 793 switch (blank_mode) {
792 case FB_BLANK_UNBLANK: 794 case FB_BLANK_UNBLANK:
793 pr_debug("fb%d: unblank\n", info->node); 795 pr_debug("fb%d: unblank\n", info->node);
794 svga_wcrt_mask(0x56, 0x00, 0x06); 796 svga_wcrt_mask(0x56, 0x00, 0x06);
795 svga_wseq_mask(0x01, 0x00, 0x20); 797 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
796 break; 798 break;
797 case FB_BLANK_NORMAL: 799 case FB_BLANK_NORMAL:
798 pr_debug("fb%d: blank\n", info->node); 800 pr_debug("fb%d: blank\n", info->node);
799 svga_wcrt_mask(0x56, 0x00, 0x06); 801 svga_wcrt_mask(0x56, 0x00, 0x06);
800 svga_wseq_mask(0x01, 0x20, 0x20); 802 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
801 break; 803 break;
802 case FB_BLANK_HSYNC_SUSPEND: 804 case FB_BLANK_HSYNC_SUSPEND:
803 pr_debug("fb%d: hsync\n", info->node); 805 pr_debug("fb%d: hsync\n", info->node);
804 svga_wcrt_mask(0x56, 0x02, 0x06); 806 svga_wcrt_mask(0x56, 0x02, 0x06);
805 svga_wseq_mask(0x01, 0x20, 0x20); 807 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
806 break; 808 break;
807 case FB_BLANK_VSYNC_SUSPEND: 809 case FB_BLANK_VSYNC_SUSPEND:
808 pr_debug("fb%d: vsync\n", info->node); 810 pr_debug("fb%d: vsync\n", info->node);
809 svga_wcrt_mask(0x56, 0x04, 0x06); 811 svga_wcrt_mask(0x56, 0x04, 0x06);
810 svga_wseq_mask(0x01, 0x20, 0x20); 812 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
811 break; 813 break;
812 case FB_BLANK_POWERDOWN: 814 case FB_BLANK_POWERDOWN:
813 pr_debug("fb%d: sync down\n", info->node); 815 pr_debug("fb%d: sync down\n", info->node);
814 svga_wcrt_mask(0x56, 0x06, 0x06); 816 svga_wcrt_mask(0x56, 0x06, 0x06);
815 svga_wseq_mask(0x01, 0x20, 0x20); 817 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
816 break; 818 break;
817 } 819 }
818 820