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authorJoe Perches <joe@perches.com>2013-09-19 21:35:55 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2013-10-29 06:53:07 -0400
commit31b6780c15a4e3a90fe260e977f5186772ce7afb (patch)
tree9147371d1b0f5b6dbf1806a7af125552a67fbc3b /drivers/video/s3fb.c
parentf51a07d05c5142e73f781d878f411d63d3548a49 (diff)
framebuffer: Use fb_<level>
Neaten and shorten the code using the new fb_<level> macros. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/s3fb.c')
-rw-r--r--drivers/video/s3fb.c62
1 files changed, 32 insertions, 30 deletions
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c
index d158d2c0460f..d4436f587a95 100644
--- a/drivers/video/s3fb.c
+++ b/drivers/video/s3fb.c
@@ -306,8 +306,8 @@ static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
306 306
307 if ((map->width != 8) || (map->height != 16) || 307 if ((map->width != 8) || (map->height != 16) ||
308 (map->depth != 1) || (map->length != 256)) { 308 (map->depth != 1) || (map->length != 256)) {
309 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", 309 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
310 info->node, map->width, map->height, map->depth, map->length); 310 map->width, map->height, map->depth, map->length);
311 return; 311 return;
312 } 312 }
313 313
@@ -476,7 +476,7 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
476 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, 476 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
477 1000000000 / pixclock, &m, &n, &r, info->node); 477 1000000000 / pixclock, &m, &n, &r, info->node);
478 if (rv < 0) { 478 if (rv < 0) {
479 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); 479 fb_err(info, "cannot set requested pixclock, keeping old value\n");
480 return; 480 return;
481 } 481 }
482 482
@@ -569,7 +569,7 @@ static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
569 rv = -EINVAL; 569 rv = -EINVAL;
570 570
571 if (rv < 0) { 571 if (rv < 0) {
572 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); 572 fb_err(info, "unsupported mode requested\n");
573 return rv; 573 return rv;
574 } 574 }
575 575
@@ -587,22 +587,21 @@ static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
587 /* Check whether have enough memory */ 587 /* Check whether have enough memory */
588 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; 588 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
589 if (mem > info->screen_size) { 589 if (mem > info->screen_size) {
590 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", 590 fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n",
591 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); 591 mem >> 10, (unsigned int) (info->screen_size >> 10));
592 return -EINVAL; 592 return -EINVAL;
593 } 593 }
594 594
595 rv = svga_check_timings (&s3_timing_regs, var, info->node); 595 rv = svga_check_timings (&s3_timing_regs, var, info->node);
596 if (rv < 0) { 596 if (rv < 0) {
597 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); 597 fb_err(info, "invalid timings requested\n");
598 return rv; 598 return rv;
599 } 599 }
600 600
601 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, 601 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
602 info->node); 602 info->node);
603 if (rv < 0) { 603 if (rv < 0) {
604 printk(KERN_ERR "fb%d: invalid pixclock value requested\n", 604 fb_err(info, "invalid pixclock value requested\n");
605 info->node);
606 return rv; 605 return rv;
607 } 606 }
608 607
@@ -686,7 +685,7 @@ static int s3fb_set_par(struct fb_info *info)
686 685
687 686
688 /* Set the offset register */ 687 /* Set the offset register */
689 pr_debug("fb%d: offset register : %d\n", info->node, offset_value); 688 fb_dbg(info, "offset register : %d\n", offset_value);
690 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); 689 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
691 690
692 if (par->chip != CHIP_357_VIRGE_GX2 && 691 if (par->chip != CHIP_357_VIRGE_GX2 &&
@@ -769,7 +768,7 @@ static int s3fb_set_par(struct fb_info *info)
769 /* Set mode-specific register values */ 768 /* Set mode-specific register values */
770 switch (mode) { 769 switch (mode) {
771 case 0: 770 case 0:
772 pr_debug("fb%d: text mode\n", info->node); 771 fb_dbg(info, "text mode\n");
773 svga_set_textmode_vga_regs(par->state.vgabase); 772 svga_set_textmode_vga_regs(par->state.vgabase);
774 773
775 /* Set additional registers like in 8-bit mode */ 774 /* Set additional registers like in 8-bit mode */
@@ -780,12 +779,12 @@ static int s3fb_set_par(struct fb_info *info)
780 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); 779 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
781 780
782 if (fasttext) { 781 if (fasttext) {
783 pr_debug("fb%d: high speed text mode set\n", info->node); 782 fb_dbg(info, "high speed text mode set\n");
784 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); 783 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
785 } 784 }
786 break; 785 break;
787 case 1: 786 case 1:
788 pr_debug("fb%d: 4 bit pseudocolor\n", info->node); 787 fb_dbg(info, "4 bit pseudocolor\n");
789 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); 788 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
790 789
791 /* Set additional registers like in 8-bit mode */ 790 /* Set additional registers like in 8-bit mode */
@@ -796,7 +795,7 @@ static int s3fb_set_par(struct fb_info *info)
796 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); 795 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
797 break; 796 break;
798 case 2: 797 case 2:
799 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); 798 fb_dbg(info, "4 bit pseudocolor, planar\n");
800 799
801 /* Set additional registers like in 8-bit mode */ 800 /* Set additional registers like in 8-bit mode */
802 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); 801 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
@@ -806,7 +805,7 @@ static int s3fb_set_par(struct fb_info *info)
806 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); 805 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
807 break; 806 break;
808 case 3: 807 case 3:
809 pr_debug("fb%d: 8 bit pseudocolor\n", info->node); 808 fb_dbg(info, "8 bit pseudocolor\n");
810 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); 809 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
811 if (info->var.pixclock > 20000 || 810 if (info->var.pixclock > 20000 ||
812 par->chip == CHIP_357_VIRGE_GX2 || 811 par->chip == CHIP_357_VIRGE_GX2 ||
@@ -822,7 +821,7 @@ static int s3fb_set_par(struct fb_info *info)
822 } 821 }
823 break; 822 break;
824 case 4: 823 case 4:
825 pr_debug("fb%d: 5/5/5 truecolor\n", info->node); 824 fb_dbg(info, "5/5/5 truecolor\n");
826 if (par->chip == CHIP_988_VIRGE_VX) { 825 if (par->chip == CHIP_988_VIRGE_VX) {
827 if (info->var.pixclock > 20000) 826 if (info->var.pixclock > 20000)
828 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); 827 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
@@ -850,7 +849,7 @@ static int s3fb_set_par(struct fb_info *info)
850 } 849 }
851 break; 850 break;
852 case 5: 851 case 5:
853 pr_debug("fb%d: 5/6/5 truecolor\n", info->node); 852 fb_dbg(info, "5/6/5 truecolor\n");
854 if (par->chip == CHIP_988_VIRGE_VX) { 853 if (par->chip == CHIP_988_VIRGE_VX) {
855 if (info->var.pixclock > 20000) 854 if (info->var.pixclock > 20000)
856 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); 855 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
@@ -879,16 +878,16 @@ static int s3fb_set_par(struct fb_info *info)
879 break; 878 break;
880 case 6: 879 case 6:
881 /* VIRGE VX case */ 880 /* VIRGE VX case */
882 pr_debug("fb%d: 8/8/8 truecolor\n", info->node); 881 fb_dbg(info, "8/8/8 truecolor\n");
883 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); 882 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
884 break; 883 break;
885 case 7: 884 case 7:
886 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); 885 fb_dbg(info, "8/8/8/8 truecolor\n");
887 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); 886 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
888 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); 887 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
889 break; 888 break;
890 default: 889 default:
891 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); 890 fb_err(info, "unsupported mode - bug\n");
892 return -EINVAL; 891 return -EINVAL;
893 } 892 }
894 893
@@ -991,27 +990,27 @@ static int s3fb_blank(int blank_mode, struct fb_info *info)
991 990
992 switch (blank_mode) { 991 switch (blank_mode) {
993 case FB_BLANK_UNBLANK: 992 case FB_BLANK_UNBLANK:
994 pr_debug("fb%d: unblank\n", info->node); 993 fb_dbg(info, "unblank\n");
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); 994 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 995 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
997 break; 996 break;
998 case FB_BLANK_NORMAL: 997 case FB_BLANK_NORMAL:
999 pr_debug("fb%d: blank\n", info->node); 998 fb_dbg(info, "blank\n");
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); 999 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 1000 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1002 break; 1001 break;
1003 case FB_BLANK_HSYNC_SUSPEND: 1002 case FB_BLANK_HSYNC_SUSPEND:
1004 pr_debug("fb%d: hsync\n", info->node); 1003 fb_dbg(info, "hsync\n");
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); 1004 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 1005 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1007 break; 1006 break;
1008 case FB_BLANK_VSYNC_SUSPEND: 1007 case FB_BLANK_VSYNC_SUSPEND:
1009 pr_debug("fb%d: vsync\n", info->node); 1008 fb_dbg(info, "vsync\n");
1010 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); 1009 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
1011 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 1010 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1012 break; 1011 break;
1013 case FB_BLANK_POWERDOWN: 1012 case FB_BLANK_POWERDOWN:
1014 pr_debug("fb%d: sync down\n", info->node); 1013 fb_dbg(info, "sync down\n");
1015 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); 1014 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
1016 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 1015 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1017 break; 1016 break;
@@ -1359,13 +1358,16 @@ static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1359 goto err_reg_fb; 1358 goto err_reg_fb;
1360 } 1359 }
1361 1360
1362 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, 1361 fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n",
1363 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); 1362 info->fix.id, pci_name(dev),
1363 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1364 1364
1365 if (par->chip == CHIP_UNKNOWN) 1365 if (par->chip == CHIP_UNKNOWN)
1366 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", 1366 fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
1367 info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), 1367 vga_rcrt(par->state.vgabase, 0x2d),
1368 vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); 1368 vga_rcrt(par->state.vgabase, 0x2e),
1369 vga_rcrt(par->state.vgabase, 0x2f),
1370 vga_rcrt(par->state.vgabase, 0x30));
1369 1371
1370 /* Record a reference to the driver data */ 1372 /* Record a reference to the driver data */
1371 pci_set_drvdata(dev, info); 1373 pci_set_drvdata(dev, info);