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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/riva/riva_hw.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/video/riva/riva_hw.h')
-rw-r--r--drivers/video/riva/riva_hw.h548
1 files changed, 548 insertions, 0 deletions
diff --git a/drivers/video/riva/riva_hw.h b/drivers/video/riva/riva_hw.h
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index 000000000000..a1e71a626df2
--- /dev/null
+++ b/drivers/video/riva/riva_hw.h
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1/***************************************************************************\
2|* *|
3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38\***************************************************************************/
39
40/*
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45 */
46
47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
48#ifndef __RIVA_HW_H__
49#define __RIVA_HW_H__
50#define RIVA_SW_VERSION 0x00010003
51
52#ifndef Bool
53typedef int Bool;
54#endif
55
56#ifndef TRUE
57#define TRUE 1
58#endif
59#ifndef FALSE
60#define FALSE 0
61#endif
62#ifndef NULL
63#define NULL 0
64#endif
65
66/*
67 * Typedefs to force certain sized values.
68 */
69typedef unsigned char U008;
70typedef unsigned short U016;
71typedef unsigned int U032;
72
73/*
74 * HW access macros.
75 */
76#include <asm/io.h>
77
78#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
79#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
80#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
81#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
82#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
83#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
84
85#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
86#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
87
88/*
89 * Define different architectures.
90 */
91#define NV_ARCH_03 0x03
92#define NV_ARCH_04 0x04
93#define NV_ARCH_10 0x10
94#define NV_ARCH_20 0x20
95#define NV_ARCH_30 0x30
96#define NV_ARCH_40 0x40
97
98/***************************************************************************\
99* *
100* FIFO registers. *
101* *
102\***************************************************************************/
103
104/*
105 * Raster OPeration. Windows style ROP3.
106 */
107typedef volatile struct
108{
109 U032 reserved00[4];
110#ifdef __BIG_ENDIAN
111 U032 FifoFree;
112#else
113 U016 FifoFree;
114 U016 Nop;
115#endif
116 U032 reserved01[0x0BB];
117 U032 Rop3;
118} RivaRop;
119/*
120 * 8X8 Monochrome pattern.
121 */
122typedef volatile struct
123{
124 U032 reserved00[4];
125#ifdef __BIG_ENDIAN
126 U032 FifoFree;
127#else
128 U016 FifoFree;
129 U016 Nop;
130#endif
131 U032 reserved01[0x0BD];
132 U032 Shape;
133 U032 reserved03[0x001];
134 U032 Color0;
135 U032 Color1;
136 U032 Monochrome[2];
137} RivaPattern;
138/*
139 * Scissor clip rectangle.
140 */
141typedef volatile struct
142{
143 U032 reserved00[4];
144#ifdef __BIG_ENDIAN
145 U032 FifoFree;
146#else
147 U016 FifoFree;
148 U016 Nop;
149#endif
150 U032 reserved01[0x0BB];
151 U032 TopLeft;
152 U032 WidthHeight;
153} RivaClip;
154/*
155 * 2D filled rectangle.
156 */
157typedef volatile struct
158{
159 U032 reserved00[4];
160#ifdef __BIG_ENDIAN
161 U032 FifoFree;
162#else
163 U016 FifoFree;
164 U016 Nop[1];
165#endif
166 U032 reserved01[0x0BC];
167 U032 Color;
168 U032 reserved03[0x03E];
169 U032 TopLeft;
170 U032 WidthHeight;
171} RivaRectangle;
172/*
173 * 2D screen-screen BLT.
174 */
175typedef volatile struct
176{
177 U032 reserved00[4];
178#ifdef __BIG_ENDIAN
179 U032 FifoFree;
180#else
181 U016 FifoFree;
182 U016 Nop;
183#endif
184 U032 reserved01[0x0BB];
185 U032 TopLeftSrc;
186 U032 TopLeftDst;
187 U032 WidthHeight;
188} RivaScreenBlt;
189/*
190 * 2D pixel BLT.
191 */
192typedef volatile struct
193{
194 U032 reserved00[4];
195#ifdef __BIG_ENDIAN
196 U032 FifoFree;
197#else
198 U016 FifoFree;
199 U016 Nop[1];
200#endif
201 U032 reserved01[0x0BC];
202 U032 TopLeft;
203 U032 WidthHeight;
204 U032 WidthHeightIn;
205 U032 reserved02[0x03C];
206 U032 Pixels;
207} RivaPixmap;
208/*
209 * Filled rectangle combined with monochrome expand. Useful for glyphs.
210 */
211typedef volatile struct
212{
213 U032 reserved00[4];
214#ifdef __BIG_ENDIAN
215 U032 FifoFree;
216#else
217 U016 FifoFree;
218 U016 Nop;
219#endif
220 U032 reserved01[0x0BB];
221 U032 reserved03[(0x040)-1];
222 U032 Color1A;
223 struct
224 {
225 U032 TopLeft;
226 U032 WidthHeight;
227 } UnclippedRectangle[64];
228 U032 reserved04[(0x080)-3];
229 struct
230 {
231 U032 TopLeft;
232 U032 BottomRight;
233 } ClipB;
234 U032 Color1B;
235 struct
236 {
237 U032 TopLeft;
238 U032 BottomRight;
239 } ClippedRectangle[64];
240 U032 reserved05[(0x080)-5];
241 struct
242 {
243 U032 TopLeft;
244 U032 BottomRight;
245 } ClipC;
246 U032 Color1C;
247 U032 WidthHeightC;
248 U032 PointC;
249 U032 MonochromeData1C;
250 U032 reserved06[(0x080)+121];
251 struct
252 {
253 U032 TopLeft;
254 U032 BottomRight;
255 } ClipD;
256 U032 Color1D;
257 U032 WidthHeightInD;
258 U032 WidthHeightOutD;
259 U032 PointD;
260 U032 MonochromeData1D;
261 U032 reserved07[(0x080)+120];
262 struct
263 {
264 U032 TopLeft;
265 U032 BottomRight;
266 } ClipE;
267 U032 Color0E;
268 U032 Color1E;
269 U032 WidthHeightInE;
270 U032 WidthHeightOutE;
271 U032 PointE;
272 U032 MonochromeData01E;
273} RivaBitmap;
274/*
275 * 3D textured, Z buffered triangle.
276 */
277typedef volatile struct
278{
279 U032 reserved00[4];
280#ifdef __BIG_ENDIAN
281 U032 FifoFree;
282#else
283 U016 FifoFree;
284 U016 Nop;
285#endif
286 U032 reserved01[0x0BC];
287 U032 TextureOffset;
288 U032 TextureFormat;
289 U032 TextureFilter;
290 U032 FogColor;
291/* This is a problem on LynxOS */
292#ifdef Control
293#undef Control
294#endif
295 U032 Control;
296 U032 AlphaTest;
297 U032 reserved02[0x339];
298 U032 FogAndIndex;
299 U032 Color;
300 float ScreenX;
301 float ScreenY;
302 float ScreenZ;
303 float EyeM;
304 float TextureS;
305 float TextureT;
306} RivaTexturedTriangle03;
307typedef volatile struct
308{
309 U032 reserved00[4];
310#ifdef __BIG_ENDIAN
311 U032 FifoFree;
312#else
313 U016 FifoFree;
314 U016 Nop;
315#endif
316 U032 reserved01[0x0BB];
317 U032 ColorKey;
318 U032 TextureOffset;
319 U032 TextureFormat;
320 U032 TextureFilter;
321 U032 Blend;
322/* This is a problem on LynxOS */
323#ifdef Control
324#undef Control
325#endif
326 U032 Control;
327 U032 FogColor;
328 U032 reserved02[0x39];
329 struct
330 {
331 float ScreenX;
332 float ScreenY;
333 float ScreenZ;
334 float EyeM;
335 U032 Color;
336 U032 Specular;
337 float TextureS;
338 float TextureT;
339 } Vertex[16];
340 U032 DrawTriangle3D;
341} RivaTexturedTriangle05;
342/*
343 * 2D line.
344 */
345typedef volatile struct
346{
347 U032 reserved00[4];
348#ifdef __BIG_ENDIAN
349 U032 FifoFree;
350#else
351 U016 FifoFree;
352 U016 Nop[1];
353#endif
354 U032 reserved01[0x0BC];
355 U032 Color; /* source color 0304-0307*/
356 U032 Reserved02[0x03e];
357 struct { /* start aliased methods in array 0400- */
358 U032 point0; /* y_x S16_S16 in pixels 0- 3*/
359 U032 point1; /* y_x S16_S16 in pixels 4- 7*/
360 } Lin[16]; /* end of aliased methods in array -047f*/
361 struct { /* start aliased methods in array 0480- */
362 U032 point0X; /* in pixels, 0 at left 0- 3*/
363 U032 point0Y; /* in pixels, 0 at top 4- 7*/
364 U032 point1X; /* in pixels, 0 at left 8- b*/
365 U032 point1Y; /* in pixels, 0 at top c- f*/
366 } Lin32[8]; /* end of aliased methods in array -04ff*/
367 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
368 struct { /* start aliased methods in array 0580- */
369 U032 x; /* in pixels, 0 at left 0- 3*/
370 U032 y; /* in pixels, 0 at top 4- 7*/
371 } PolyLin32[16]; /* end of aliased methods in array -05ff*/
372 struct { /* start aliased methods in array 0600- */
373 U032 color; /* source color 0- 3*/
374 U032 point; /* y_x S16_S16 in pixels 4- 7*/
375 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/
376} RivaLine;
377/*
378 * 2D/3D surfaces
379 */
380typedef volatile struct
381{
382 U032 reserved00[4];
383#ifdef __BIG_ENDIAN
384 U032 FifoFree;
385#else
386 U016 FifoFree;
387 U016 Nop;
388#endif
389 U032 reserved01[0x0BE];
390 U032 Offset;
391} RivaSurface;
392typedef volatile struct
393{
394 U032 reserved00[4];
395#ifdef __BIG_ENDIAN
396 U032 FifoFree;
397#else
398 U016 FifoFree;
399 U016 Nop;
400#endif
401 U032 reserved01[0x0BD];
402 U032 Pitch;
403 U032 RenderBufferOffset;
404 U032 ZBufferOffset;
405} RivaSurface3D;
406
407/***************************************************************************\
408* *
409* Virtualized RIVA H/W interface. *
410* *
411\***************************************************************************/
412
413#define FP_ENABLE 1
414#define FP_DITHER 2
415
416struct _riva_hw_inst;
417struct _riva_hw_state;
418/*
419 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
420 */
421typedef struct _riva_hw_inst
422{
423 /*
424 * Chip specific settings.
425 */
426 U032 Architecture;
427 U032 Version;
428 U032 Chipset;
429 U032 CrystalFreqKHz;
430 U032 RamAmountKBytes;
431 U032 MaxVClockFreqKHz;
432 U032 RamBandwidthKBytesPerSec;
433 U032 EnableIRQ;
434 U032 IO;
435 U032 VBlankBit;
436 U032 FifoFreeCount;
437 U032 FifoEmptyCount;
438 U032 CursorStart;
439 U032 flatPanel;
440 Bool twoHeads;
441 /*
442 * Non-FIFO registers.
443 */
444 volatile U032 __iomem *PCRTC0;
445 volatile U032 __iomem *PCRTC;
446 volatile U032 __iomem *PRAMDAC0;
447 volatile U032 __iomem *PFB;
448 volatile U032 __iomem *PFIFO;
449 volatile U032 __iomem *PGRAPH;
450 volatile U032 __iomem *PEXTDEV;
451 volatile U032 __iomem *PTIMER;
452 volatile U032 __iomem *PMC;
453 volatile U032 __iomem *PRAMIN;
454 volatile U032 __iomem *FIFO;
455 volatile U032 __iomem *CURSOR;
456 volatile U008 __iomem *PCIO0;
457 volatile U008 __iomem *PCIO;
458 volatile U008 __iomem *PVIO;
459 volatile U008 __iomem *PDIO0;
460 volatile U008 __iomem *PDIO;
461 volatile U032 __iomem *PRAMDAC;
462 /*
463 * Common chip functions.
464 */
465 int (*Busy)(struct _riva_hw_inst *);
466 void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int);
467 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
468 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
469 void (*SetStartAddress)(struct _riva_hw_inst *,U032);
470 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
471 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
472 int (*ShowHideCursor)(struct _riva_hw_inst *,int);
473 void (*LockUnlock)(struct _riva_hw_inst *, int);
474 /*
475 * Current extended mode settings.
476 */
477 struct _riva_hw_state *CurrentState;
478 /*
479 * FIFO registers.
480 */
481 RivaRop __iomem *Rop;
482 RivaPattern __iomem *Patt;
483 RivaClip __iomem *Clip;
484 RivaPixmap __iomem *Pixmap;
485 RivaScreenBlt __iomem *Blt;
486 RivaBitmap __iomem *Bitmap;
487 RivaLine __iomem *Line;
488 RivaTexturedTriangle03 __iomem *Tri03;
489 RivaTexturedTriangle05 __iomem *Tri05;
490} RIVA_HW_INST;
491/*
492 * Extended mode state information.
493 */
494typedef struct _riva_hw_state
495{
496 U032 bpp;
497 U032 width;
498 U032 height;
499 U032 interlace;
500 U032 repaint0;
501 U032 repaint1;
502 U032 screen;
503 U032 scale;
504 U032 dither;
505 U032 extra;
506 U032 pixel;
507 U032 horiz;
508 U032 arbitration0;
509 U032 arbitration1;
510 U032 vpll;
511 U032 vpll2;
512 U032 pllsel;
513 U032 general;
514 U032 crtcOwner;
515 U032 head;
516 U032 head2;
517 U032 config;
518 U032 cursorConfig;
519 U032 cursor0;
520 U032 cursor1;
521 U032 cursor2;
522 U032 offset0;
523 U032 offset1;
524 U032 offset2;
525 U032 offset3;
526 U032 pitch0;
527 U032 pitch1;
528 U032 pitch2;
529 U032 pitch3;
530} RIVA_HW_STATE;
531/*
532 * External routines.
533 */
534int RivaGetConfig(RIVA_HW_INST *, unsigned int);
535/*
536 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
537 */
538
539#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \
540{ \
541 while ((hwinst).FifoFreeCount < (cnt)) { \
542 mb();mb(); \
543 (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
544 } \
545 (hwinst).FifoFreeCount -= (cnt); \
546}
547#endif /* __RIVA_HW_H__ */
548
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