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authorAlan Cox <alan@redhat.com>2007-05-08 03:39:28 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-08 14:15:32 -0400
commitd37363409bacd1142c6e49edfb3e1f8b153d47dc (patch)
tree2aa26a4e06020b714192f746a11c0be4c7b7c5fb /drivers/video/riva/riva_hw.c
parentdbe7e429fedb3fbc93b496cc1c3eb4fc28333ac0 (diff)
nvidiafb/rivafb: switch to pci_get refcounting
Switch to pci_get refcounting APIs [adaplas] Fix a long-standing bug where the return value of pci_find_slot()/pci_get_bus_and_slot() is ignored. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/riva/riva_hw.c')
-rw-r--r--drivers/video/riva/riva_hw.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c
index e0b8c521cc9c..70bfd78eca81 100644
--- a/drivers/video/riva/riva_hw.c
+++ b/drivers/video/riva/riva_hw.c
@@ -1118,8 +1118,9 @@ static void nForceUpdateArbitrationSettings
1118 unsigned int uMClkPostDiv; 1118 unsigned int uMClkPostDiv;
1119 struct pci_dev *dev; 1119 struct pci_dev *dev;
1120 1120
1121 dev = pci_find_slot(0, 3); 1121 dev = pci_get_bus_and_slot(0, 3);
1122 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); 1122 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
1123 pci_dev_put(dev);
1123 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; 1124 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
1124 1125
1125 if(!uMClkPostDiv) uMClkPostDiv = 4; 1126 if(!uMClkPostDiv) uMClkPostDiv = 4;
@@ -1132,8 +1133,9 @@ static void nForceUpdateArbitrationSettings
1132 sim_data.enable_video = 0; 1133 sim_data.enable_video = 0;
1133 sim_data.enable_mp = 0; 1134 sim_data.enable_mp = 0;
1134 1135
1135 dev = pci_find_slot(0, 1); 1136 dev = pci_get_bus_and_slot(0, 1);
1136 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); 1137 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
1138 pci_dev_put(dev);
1137 sim_data.memory_type = (sim_data.memory_type >> 12) & 1; 1139 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
1138 1140
1139 sim_data.memory_width = 64; 1141 sim_data.memory_width = 64;
@@ -2112,12 +2114,14 @@ static void nv10GetConfig
2112 * Fill in chip configuration. 2114 * Fill in chip configuration.
2113 */ 2115 */
2114 if(chipset == NV_CHIP_IGEFORCE2) { 2116 if(chipset == NV_CHIP_IGEFORCE2) {
2115 dev = pci_find_slot(0, 1); 2117 dev = pci_get_bus_and_slot(0, 1);
2116 pci_read_config_dword(dev, 0x7C, &amt); 2118 pci_read_config_dword(dev, 0x7C, &amt);
2119 pci_dev_put(dev);
2117 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; 2120 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2118 } else if(chipset == NV_CHIP_0x01F0) { 2121 } else if(chipset == NV_CHIP_0x01F0) {
2119 dev = pci_find_slot(0, 1); 2122 dev = pci_get_bus_and_slot(0, 1);
2120 pci_read_config_dword(dev, 0x84, &amt); 2123 pci_read_config_dword(dev, 0x84, &amt);
2124 pci_dev_put(dev);
2121 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; 2125 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2122 } else { 2126 } else {
2123 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) 2127 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)