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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-11-07 11:17:35 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-12-07 10:06:00 -0500
commit348be69d306260c9bcb62662c4cf04196a2b9f53 (patch)
treeb3e7be219c7170901bea2c3508895f7ff0505004 /drivers/video/omap2
parenteda34273631a9c4bae65eb49394549f6007f2fb8 (diff)
OMAPDSS: export dispc functions
Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2')
-rw-r--r--drivers/video/omap2/dss/dispc.c23
-rw-r--r--drivers/video/omap2/dss/dss.h36
2 files changed, 24 insertions, 35 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 67548839ff51..fedbd2c8e97a 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -494,6 +494,7 @@ int dispc_runtime_get(void)
494 WARN_ON(r < 0); 494 WARN_ON(r < 0);
495 return r < 0 ? r : 0; 495 return r < 0 ? r : 0;
496} 496}
497EXPORT_SYMBOL(dispc_runtime_get);
497 498
498void dispc_runtime_put(void) 499void dispc_runtime_put(void)
499{ 500{
@@ -504,11 +505,13 @@ void dispc_runtime_put(void)
504 r = pm_runtime_put_sync(&dispc.pdev->dev); 505 r = pm_runtime_put_sync(&dispc.pdev->dev);
505 WARN_ON(r < 0 && r != -ENOSYS); 506 WARN_ON(r < 0 && r != -ENOSYS);
506} 507}
508EXPORT_SYMBOL(dispc_runtime_put);
507 509
508u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) 510u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
509{ 511{
510 return mgr_desc[channel].vsync_irq; 512 return mgr_desc[channel].vsync_irq;
511} 513}
514EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
512 515
513u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) 516u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
514{ 517{
@@ -517,11 +520,13 @@ u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
517 520
518 return mgr_desc[channel].framedone_irq; 521 return mgr_desc[channel].framedone_irq;
519} 522}
523EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
520 524
521u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) 525u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
522{ 526{
523 return mgr_desc[channel].sync_lost_irq; 527 return mgr_desc[channel].sync_lost_irq;
524} 528}
529EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
525 530
526u32 dispc_wb_get_framedone_irq(void) 531u32 dispc_wb_get_framedone_irq(void)
527{ 532{
@@ -532,6 +537,7 @@ bool dispc_mgr_go_busy(enum omap_channel channel)
532{ 537{
533 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; 538 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
534} 539}
540EXPORT_SYMBOL(dispc_mgr_go_busy);
535 541
536void dispc_mgr_go(enum omap_channel channel) 542void dispc_mgr_go(enum omap_channel channel)
537{ 543{
@@ -542,6 +548,7 @@ void dispc_mgr_go(enum omap_channel channel)
542 548
543 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); 549 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
544} 550}
551EXPORT_SYMBOL(dispc_mgr_go);
545 552
546bool dispc_wb_go_busy(void) 553bool dispc_wb_go_busy(void)
547{ 554{
@@ -945,6 +952,7 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
945 } 952 }
946 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 953 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
947} 954}
955EXPORT_SYMBOL(dispc_ovl_set_channel_out);
948 956
949static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) 957static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
950{ 958{
@@ -2359,6 +2367,7 @@ int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2359 &five_taps, x_predecim, y_predecim, pos_x, 2367 &five_taps, x_predecim, y_predecim, pos_x,
2360 oi->rotation_type, false); 2368 oi->rotation_type, false);
2361} 2369}
2370EXPORT_SYMBOL(dispc_ovl_check);
2362 2371
2363static int dispc_ovl_setup_common(enum omap_plane plane, 2372static int dispc_ovl_setup_common(enum omap_plane plane,
2364 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, 2373 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
@@ -2539,6 +2548,7 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2539 2548
2540 return r; 2549 return r;
2541} 2550}
2551EXPORT_SYMBOL(dispc_ovl_setup);
2542 2552
2543int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 2553int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2544 bool mem_to_mem, const struct omap_video_timings *mgr_timings) 2554 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
@@ -2599,11 +2609,13 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable)
2599 2609
2600 return 0; 2610 return 0;
2601} 2611}
2612EXPORT_SYMBOL(dispc_ovl_enable);
2602 2613
2603bool dispc_ovl_enabled(enum omap_plane plane) 2614bool dispc_ovl_enabled(enum omap_plane plane)
2604{ 2615{
2605 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); 2616 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2606} 2617}
2618EXPORT_SYMBOL(dispc_ovl_enabled);
2607 2619
2608void dispc_mgr_enable(enum omap_channel channel, bool enable) 2620void dispc_mgr_enable(enum omap_channel channel, bool enable)
2609{ 2621{
@@ -2611,11 +2623,13 @@ void dispc_mgr_enable(enum omap_channel channel, bool enable)
2611 /* flush posted write */ 2623 /* flush posted write */
2612 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 2624 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2613} 2625}
2626EXPORT_SYMBOL(dispc_mgr_enable);
2614 2627
2615bool dispc_mgr_is_enabled(enum omap_channel channel) 2628bool dispc_mgr_is_enabled(enum omap_channel channel)
2616{ 2629{
2617 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 2630 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2618} 2631}
2632EXPORT_SYMBOL(dispc_mgr_is_enabled);
2619 2633
2620void dispc_wb_enable(bool enable) 2634void dispc_wb_enable(bool enable)
2621{ 2635{
@@ -2712,6 +2726,7 @@ void dispc_mgr_setup(enum omap_channel channel,
2712 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); 2726 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2713 } 2727 }
2714} 2728}
2729EXPORT_SYMBOL(dispc_mgr_setup);
2715 2730
2716static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) 2731static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2717{ 2732{
@@ -2788,6 +2803,7 @@ void dispc_mgr_set_lcd_config(enum omap_channel channel,
2788 2803
2789 dispc_mgr_set_lcd_type_tft(channel); 2804 dispc_mgr_set_lcd_type_tft(channel);
2790} 2805}
2806EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2791 2807
2792static bool _dispc_mgr_size_ok(u16 width, u16 height) 2808static bool _dispc_mgr_size_ok(u16 width, u16 height)
2793{ 2809{
@@ -2926,6 +2942,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
2926 2942
2927 dispc_mgr_set_size(channel, t.x_res, t.y_res); 2943 dispc_mgr_set_size(channel, t.x_res, t.y_res);
2928} 2944}
2945EXPORT_SYMBOL(dispc_mgr_set_timings);
2929 2946
2930static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, 2947static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2931 u16 pck_div) 2948 u16 pck_div)
@@ -3389,16 +3406,19 @@ u32 dispc_read_irqstatus(void)
3389{ 3406{
3390 return dispc_read_reg(DISPC_IRQSTATUS); 3407 return dispc_read_reg(DISPC_IRQSTATUS);
3391} 3408}
3409EXPORT_SYMBOL(dispc_read_irqstatus);
3392 3410
3393void dispc_clear_irqstatus(u32 mask) 3411void dispc_clear_irqstatus(u32 mask)
3394{ 3412{
3395 dispc_write_reg(DISPC_IRQSTATUS, mask); 3413 dispc_write_reg(DISPC_IRQSTATUS, mask);
3396} 3414}
3415EXPORT_SYMBOL(dispc_clear_irqstatus);
3397 3416
3398u32 dispc_read_irqenable(void) 3417u32 dispc_read_irqenable(void)
3399{ 3418{
3400 return dispc_read_reg(DISPC_IRQENABLE); 3419 return dispc_read_reg(DISPC_IRQENABLE);
3401} 3420}
3421EXPORT_SYMBOL(dispc_read_irqenable);
3402 3422
3403void dispc_write_irqenable(u32 mask) 3423void dispc_write_irqenable(u32 mask)
3404{ 3424{
@@ -3409,6 +3429,7 @@ void dispc_write_irqenable(u32 mask)
3409 3429
3410 dispc_write_reg(DISPC_IRQENABLE, mask); 3430 dispc_write_reg(DISPC_IRQENABLE, mask);
3411} 3431}
3432EXPORT_SYMBOL(dispc_write_irqenable);
3412 3433
3413void dispc_enable_sidle(void) 3434void dispc_enable_sidle(void)
3414{ 3435{
@@ -3584,11 +3605,13 @@ int dispc_request_irq(irq_handler_t handler, void *dev_id)
3584 return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler, 3605 return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
3585 IRQF_SHARED, "OMAP DISPC", dev_id); 3606 IRQF_SHARED, "OMAP DISPC", dev_id);
3586} 3607}
3608EXPORT_SYMBOL(dispc_request_irq);
3587 3609
3588void dispc_free_irq(void *dev_id) 3610void dispc_free_irq(void *dev_id)
3589{ 3611{
3590 devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id); 3612 devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
3591} 3613}
3614EXPORT_SYMBOL(dispc_free_irq);
3592 3615
3593/* DISPC HW IP initialisation */ 3616/* DISPC HW IP initialisation */
3594static int __init omap_dispchw_probe(struct platform_device *pdev) 3617static int __init omap_dispchw_probe(struct platform_device *pdev)
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 1d8483cbe395..ebe9e08b2a91 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -365,16 +365,6 @@ void dpi_uninit_platform_driver(void) __exit;
365int dispc_init_platform_driver(void) __init; 365int dispc_init_platform_driver(void) __init;
366void dispc_uninit_platform_driver(void) __exit; 366void dispc_uninit_platform_driver(void) __exit;
367void dispc_dump_clocks(struct seq_file *s); 367void dispc_dump_clocks(struct seq_file *s);
368u32 dispc_read_irqstatus(void);
369void dispc_clear_irqstatus(u32 mask);
370u32 dispc_read_irqenable(void);
371void dispc_write_irqenable(u32 mask);
372
373int dispc_request_irq(irq_handler_t handler, void *dev_id);
374void dispc_free_irq(void *dev_id);
375
376int dispc_runtime_get(void);
377void dispc_runtime_put(void);
378 368
379void dispc_enable_sidle(void); 369void dispc_enable_sidle(void);
380void dispc_disable_sidle(void); 370void dispc_disable_sidle(void);
@@ -398,29 +388,7 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
398void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, 388void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
399 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 389 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
400 bool manual_update); 390 bool manual_update);
401int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 391
402 bool replication, const struct omap_video_timings *mgr_timings,
403 bool mem_to_mem);
404int dispc_ovl_enable(enum omap_plane plane, bool enable);
405bool dispc_ovl_enabled(enum omap_plane plane);
406void dispc_ovl_set_channel_out(enum omap_plane plane,
407 enum omap_channel channel);
408int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
409 const struct omap_overlay_info *oi,
410 const struct omap_video_timings *timings,
411 int *x_predecim, int *y_predecim);
412
413u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
414u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
415u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
416bool dispc_mgr_go_busy(enum omap_channel channel);
417void dispc_mgr_go(enum omap_channel channel);
418void dispc_mgr_enable(enum omap_channel channel, bool enable);
419bool dispc_mgr_is_enabled(enum omap_channel channel);
420void dispc_mgr_set_lcd_config(enum omap_channel channel,
421 const struct dss_lcd_mgr_config *config);
422void dispc_mgr_set_timings(enum omap_channel channel,
423 const struct omap_video_timings *timings);
424unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 392unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
425unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 393unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
426unsigned long dispc_core_clk_rate(void); 394unsigned long dispc_core_clk_rate(void);
@@ -428,8 +396,6 @@ void dispc_mgr_set_clock_div(enum omap_channel channel,
428 const struct dispc_clock_info *cinfo); 396 const struct dispc_clock_info *cinfo);
429int dispc_mgr_get_clock_div(enum omap_channel channel, 397int dispc_mgr_get_clock_div(enum omap_channel channel,
430 struct dispc_clock_info *cinfo); 398 struct dispc_clock_info *cinfo);
431void dispc_mgr_setup(enum omap_channel channel,
432 const struct omap_overlay_manager_info *info);
433 399
434u32 dispc_wb_get_framedone_irq(void); 400u32 dispc_wb_get_framedone_irq(void);
435bool dispc_wb_go_busy(void); 401bool dispc_wb_go_busy(void);