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authorArchit Taneja <archit@ti.com>2011-04-12 04:22:23 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-05-11 07:19:27 -0400
commit89a35e5170fc579e4fc3a1f3444c5dc1aa36904d (patch)
tree92e23633ac8b048ec8e8ae076457519e439cc066 /drivers/video/omap2/dss/dss.h
parent14e4d78485a50312be72a42fd42a28b5b34264dc (diff)
OMAP2PLUS: DSS2: Change enum "dss_clk_source" to "omap_dss_clk_source"
Change enum dss_clk_source to omap_dss_clock_source and move it to 'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning. These changes are done in order to specify the clock sources for DSS in the board file. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.h')
-rw-r--r--drivers/video/omap2/dss/dss.h23
1 files changed, 7 insertions, 16 deletions
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index c2f582bb19c0..d3b5697134e1 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -117,15 +117,6 @@ enum dss_clock {
117 DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/ 117 DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/
118}; 118};
119 119
120enum dss_clk_source {
121 DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
122 * OMAP4: PLL1_CLK1 */
123 DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
124 * OMAP4: PLL1_CLK2 */
125 DSS_CLK_SRC_FCK, /* OMAP2/3: DSS1_ALWON_FCLK
126 * OMAP4: DSS_FCLK */
127};
128
129enum dss_hdmi_venc_clk_source_select { 120enum dss_hdmi_venc_clk_source_select {
130 DSS_VENC_TV_CLK = 0, 121 DSS_VENC_TV_CLK = 0,
131 DSS_HDMI_M_PCLK = 1, 122 DSS_HDMI_M_PCLK = 1,
@@ -236,7 +227,7 @@ void dss_clk_enable(enum dss_clock clks);
236void dss_clk_disable(enum dss_clock clks); 227void dss_clk_disable(enum dss_clock clks);
237unsigned long dss_clk_get_rate(enum dss_clock clk); 228unsigned long dss_clk_get_rate(enum dss_clock clk);
238int dss_need_ctx_restore(void); 229int dss_need_ctx_restore(void);
239const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src); 230const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
240void dss_dump_clocks(struct seq_file *s); 231void dss_dump_clocks(struct seq_file *s);
241 232
242void dss_dump_regs(struct seq_file *s); 233void dss_dump_regs(struct seq_file *s);
@@ -248,13 +239,13 @@ void dss_sdi_init(u8 datapairs);
248int dss_sdi_enable(void); 239int dss_sdi_enable(void);
249void dss_sdi_disable(void); 240void dss_sdi_disable(void);
250 241
251void dss_select_dispc_clk_source(enum dss_clk_source clk_src); 242void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
252void dss_select_dsi_clk_source(enum dss_clk_source clk_src); 243void dss_select_dsi_clk_source(enum omap_dss_clk_source clk_src);
253void dss_select_lcd_clk_source(enum omap_channel channel, 244void dss_select_lcd_clk_source(enum omap_channel channel,
254 enum dss_clk_source clk_src); 245 enum omap_dss_clk_source clk_src);
255enum dss_clk_source dss_get_dispc_clk_source(void); 246enum omap_dss_clk_source dss_get_dispc_clk_source(void);
256enum dss_clk_source dss_get_dsi_clk_source(void); 247enum omap_dss_clk_source dss_get_dsi_clk_source(void);
257enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 248enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
258 249
259void dss_set_venc_output(enum omap_dss_venc_type type); 250void dss_set_venc_output(enum omap_dss_venc_type type);
260void dss_set_dac_pwrdn_bgz(bool enable); 251void dss_set_dac_pwrdn_bgz(bool enable);