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authorArchit Taneja <archit@ti.com>2011-02-24 03:47:30 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-03-11 08:46:27 -0500
commit1bb478350670fadf708d3cbd6137c32dfbe3fd5f (patch)
tree387ed4990280ad1bbfd17f763d9249c66a2d750c /drivers/video/omap2/dss/dss.c
parent067a57e48e302863eb2d5ac0900ae9ae65dbc8c3 (diff)
OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming
DSI PLL output clock names have been made more generic. The clock name describes what the source of the clock and what clock is used for. Some of DSI PLL parameters like dividers and DSI PLL source have also been made more generic. dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named regm_dispc and regm_dsi instead of regm3 and regm4. Functions and macros named on the basis of these clock names have also been made generic. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
-rw-r--r--drivers/video/omap2/dss/dss.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index d049598bb412..5c6805b3362d 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -299,7 +299,7 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
299 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; 299 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
300 300
301 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC) 301 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
302 dsi_wait_dsi1_pll_active(); 302 dsi_wait_pll_hsdiv_dispc_active();
303 303
304 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ 304 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
305 305
@@ -316,7 +316,7 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
316 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; 316 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
317 317
318 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI) 318 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
319 dsi_wait_dsi2_pll_active(); 319 dsi_wait_pll_hsdiv_dsi_active();
320 320
321 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ 321 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
322 322