aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/omap2/dss/dss.c
diff options
context:
space:
mode:
authorArchit Taneja <archit@ti.com>2011-01-06 00:14:10 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-03-11 08:46:27 -0500
commit88134fa138b90518819b750891ffecc13f5f4886 (patch)
tree3a07a522cc2764bcb81dc2b4d83b8468e84295f4 /drivers/video/omap2/dss/dss.c
parent819d807c59af10cce1dcbb13539c2fb100953fcd (diff)
OMAP2PLUS: DSS2: Make members of dss_clk_source generic
The enum members of 'dss_clk_source' have clock source names specific to OMAP2/3. Change the names to more generic terms such that they now describe where the clocks come from and what they are used for. Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC" for more clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
-rw-r--r--drivers/video/omap2/dss/dss.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 01be82a4f42f..998c188c8823 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -278,12 +278,12 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
278{ 278{
279 int b; 279 int b;
280 280
281 BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && 281 BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC &&
282 clk_src != DSS_SRC_DSS1_ALWON_FCLK); 282 clk_src != DSS_CLK_SRC_FCK);
283 283
284 b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; 284 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
285 285
286 if (clk_src == DSS_SRC_DSI1_PLL_FCLK) 286 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
287 dsi_wait_dsi1_pll_active(); 287 dsi_wait_dsi1_pll_active();
288 288
289 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ 289 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
@@ -295,12 +295,12 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
295{ 295{
296 int b; 296 int b;
297 297
298 BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && 298 BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI &&
299 clk_src != DSS_SRC_DSS1_ALWON_FCLK); 299 clk_src != DSS_CLK_SRC_FCK);
300 300
301 b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; 301 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
302 302
303 if (clk_src == DSS_SRC_DSI2_PLL_FCLK) 303 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
304 dsi_wait_dsi2_pll_active(); 304 dsi_wait_dsi2_pll_active();
305 305
306 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ 306 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
@@ -601,8 +601,8 @@ static int dss_init(bool skip_init)
601 } 601 }
602 } 602 }
603 603
604 dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; 604 dss.dsi_clk_source = DSS_CLK_SRC_FCK;
605 dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; 605 dss.dispc_clk_source = DSS_CLK_SRC_FCK;
606 606
607 dss_save_context(); 607 dss_save_context();
608 608