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authorTomi Valkeinen <tomi.valkeinen@ti.com>2013-03-12 04:26:45 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2013-03-12 09:46:52 -0400
commit06a3307975aac2d5b5a0e0f2e05d23e769f176b4 (patch)
treeb4cc6d14e14523c2380c254d6ac102ec9d4d9647 /drivers/video/of_display_timing.c
parenta38884f681a4d044befd30d9f3d19a0821bae63a (diff)
videomode: combine videomode dmt_flags and data_flags
Both videomode and display_timing contain flags describing the modes. These are stored in dmt_flags and data_flags. There's no need to separate these flags, and having separate fields just makes the flags more difficult to use. This patch combines the fields and renames VESA_DMT_* flags to DISPLAY_FLAGS_*. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Diffstat (limited to 'drivers/video/of_display_timing.c')
-rw-r--r--drivers/video/of_display_timing.c19
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/video/of_display_timing.c b/drivers/video/of_display_timing.c
index 13ecd9897010..56009bc02b02 100644
--- a/drivers/video/of_display_timing.c
+++ b/drivers/video/of_display_timing.c
@@ -79,25 +79,24 @@ static struct display_timing *of_get_display_timing(struct device_node *np)
79 ret |= parse_timing_property(np, "vsync-len", &dt->vsync_len); 79 ret |= parse_timing_property(np, "vsync-len", &dt->vsync_len);
80 ret |= parse_timing_property(np, "clock-frequency", &dt->pixelclock); 80 ret |= parse_timing_property(np, "clock-frequency", &dt->pixelclock);
81 81
82 dt->dmt_flags = 0; 82 dt->flags = 0;
83 dt->data_flags = 0;
84 if (!of_property_read_u32(np, "vsync-active", &val)) 83 if (!of_property_read_u32(np, "vsync-active", &val))
85 dt->dmt_flags |= val ? VESA_DMT_VSYNC_HIGH : 84 dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH :
86 VESA_DMT_VSYNC_LOW; 85 DISPLAY_FLAGS_VSYNC_LOW;
87 if (!of_property_read_u32(np, "hsync-active", &val)) 86 if (!of_property_read_u32(np, "hsync-active", &val))
88 dt->dmt_flags |= val ? VESA_DMT_HSYNC_HIGH : 87 dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH :
89 VESA_DMT_HSYNC_LOW; 88 DISPLAY_FLAGS_HSYNC_LOW;
90 if (!of_property_read_u32(np, "de-active", &val)) 89 if (!of_property_read_u32(np, "de-active", &val))
91 dt->data_flags |= val ? DISPLAY_FLAGS_DE_HIGH : 90 dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH :
92 DISPLAY_FLAGS_DE_LOW; 91 DISPLAY_FLAGS_DE_LOW;
93 if (!of_property_read_u32(np, "pixelclk-active", &val)) 92 if (!of_property_read_u32(np, "pixelclk-active", &val))
94 dt->data_flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE : 93 dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE :
95 DISPLAY_FLAGS_PIXDATA_NEGEDGE; 94 DISPLAY_FLAGS_PIXDATA_NEGEDGE;
96 95
97 if (of_property_read_bool(np, "interlaced")) 96 if (of_property_read_bool(np, "interlaced"))
98 dt->data_flags |= DISPLAY_FLAGS_INTERLACED; 97 dt->flags |= DISPLAY_FLAGS_INTERLACED;
99 if (of_property_read_bool(np, "doublescan")) 98 if (of_property_read_bool(np, "doublescan"))
100 dt->data_flags |= DISPLAY_FLAGS_DOUBLESCAN; 99 dt->flags |= DISPLAY_FLAGS_DOUBLESCAN;
101 100
102 if (ret) { 101 if (ret) {
103 pr_err("%s: error reading timing properties\n", 102 pr_err("%s: error reading timing properties\n",