diff options
| author | Antonino A. Daplas <adaplas@gmail.com> | 2007-05-08 03:38:24 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-08 14:15:28 -0400 |
| commit | e296927bcc910ffa9e171c0108a4bf74c0836553 (patch) | |
| tree | c04286baf04ab728249c96c868d0b1779da3c5fa /drivers/video/nvidia/nv_i2c.c | |
| parent | b9b2696de920e7366e2ce0cdc3b3b7fc11e44e99 (diff) | |
nvidiafb: access CRT registers safely
Use Read/WriteCrtc() to access CRTC registers in nv_i2c.c. These are safer
because it uses the correct CRTC base (0x3bx or 0x3dx).
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/nvidia/nv_i2c.c')
| -rw-r--r-- | drivers/video/nvidia/nv_i2c.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/video/nvidia/nv_i2c.c b/drivers/video/nvidia/nv_i2c.c index 4fc7118397fe..afe4567e1ff4 100644 --- a/drivers/video/nvidia/nv_i2c.c +++ b/drivers/video/nvidia/nv_i2c.c | |||
| @@ -30,16 +30,14 @@ static void nvidia_gpio_setscl(void *data, int state) | |||
| 30 | struct nvidia_par *par = chan->par; | 30 | struct nvidia_par *par = chan->par; |
| 31 | u32 val; | 31 | u32 val; |
| 32 | 32 | ||
| 33 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 33 | val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; |
| 34 | val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0; | ||
| 35 | 34 | ||
| 36 | if (state) | 35 | if (state) |
| 37 | val |= 0x20; | 36 | val |= 0x20; |
| 38 | else | 37 | else |
| 39 | val &= ~0x20; | 38 | val &= ~0x20; |
| 40 | 39 | ||
| 41 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 40 | NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); |
| 42 | VGA_WR08(par->PCIO, 0x3d5, val | 0x1); | ||
| 43 | } | 41 | } |
| 44 | 42 | ||
| 45 | static void nvidia_gpio_setsda(void *data, int state) | 43 | static void nvidia_gpio_setsda(void *data, int state) |
| @@ -48,16 +46,14 @@ static void nvidia_gpio_setsda(void *data, int state) | |||
| 48 | struct nvidia_par *par = chan->par; | 46 | struct nvidia_par *par = chan->par; |
| 49 | u32 val; | 47 | u32 val; |
| 50 | 48 | ||
| 51 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 49 | val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; |
| 52 | val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0; | ||
| 53 | 50 | ||
| 54 | if (state) | 51 | if (state) |
| 55 | val |= 0x10; | 52 | val |= 0x10; |
| 56 | else | 53 | else |
| 57 | val &= ~0x10; | 54 | val &= ~0x10; |
| 58 | 55 | ||
| 59 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1); | 56 | NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); |
| 60 | VGA_WR08(par->PCIO, 0x3d5, val | 0x1); | ||
| 61 | } | 57 | } |
| 62 | 58 | ||
| 63 | static int nvidia_gpio_getscl(void *data) | 59 | static int nvidia_gpio_getscl(void *data) |
| @@ -66,8 +62,7 @@ static int nvidia_gpio_getscl(void *data) | |||
| 66 | struct nvidia_par *par = chan->par; | 62 | struct nvidia_par *par = chan->par; |
| 67 | u32 val = 0; | 63 | u32 val = 0; |
| 68 | 64 | ||
| 69 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base); | 65 | if (NVReadCrtc(par, chan->ddc_base) & 0x04) |
| 70 | if (VGA_RD08(par->PCIO, 0x3d5) & 0x04) | ||
| 71 | val = 1; | 66 | val = 1; |
| 72 | 67 | ||
| 73 | return val; | 68 | return val; |
| @@ -79,8 +74,7 @@ static int nvidia_gpio_getsda(void *data) | |||
| 79 | struct nvidia_par *par = chan->par; | 74 | struct nvidia_par *par = chan->par; |
| 80 | u32 val = 0; | 75 | u32 val = 0; |
| 81 | 76 | ||
| 82 | VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base); | 77 | if (NVReadCrtc(par, chan->ddc_base) & 0x08) |
| 83 | if (VGA_RD08(par->PCIO, 0x3d5) & 0x08) | ||
| 84 | val = 1; | 78 | val = 1; |
| 85 | 79 | ||
| 86 | return val; | 80 | return val; |