diff options
author | Antonino A. Daplas <adaplas@gmail.com> | 2006-06-26 03:26:38 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-26 12:58:30 -0400 |
commit | fe610671d7a88e363e8cebcb7e2f32078b0151ce (patch) | |
tree | bc32cb0616a2a0a2e940e69dc5f0b230bb422e9f /drivers/video/nvidia/nv_hw.c | |
parent | ba70710e59c701734aad524bc441b3400700e94b (diff) |
[PATCH] nvidiafb: Add support for Geforce 6100 and related chipsets
Add support for Geforce 6100 and related chipsets (PCI device id 0x024x)
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/video/nvidia/nv_hw.c')
-rw-r--r-- | drivers/video/nvidia/nv_hw.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c index 99c3a8e6a237..9ed640d35728 100644 --- a/drivers/video/nvidia/nv_hw.c +++ b/drivers/video/nvidia/nv_hw.c | |||
@@ -886,7 +886,10 @@ void NVCalcStateExt(struct nvidia_par *par, | |||
886 | case NV_ARCH_20: | 886 | case NV_ARCH_20: |
887 | case NV_ARCH_30: | 887 | case NV_ARCH_30: |
888 | default: | 888 | default: |
889 | if (((par->Chipset & 0xffff) == 0x01A0) || | 889 | if ((par->Chipset & 0xfff0) == 0x0240) { |
890 | state->arbitration0 = 256; | ||
891 | state->arbitration1 = 0x0480; | ||
892 | } else if (((par->Chipset & 0xffff) == 0x01A0) || | ||
890 | ((par->Chipset & 0xffff) == 0x01f0)) { | 893 | ((par->Chipset & 0xffff) == 0x01f0)) { |
891 | nForceUpdateArbitrationSettings(VClk, | 894 | nForceUpdateArbitrationSettings(VClk, |
892 | pixelDepth * 8, | 895 | pixelDepth * 8, |
@@ -1235,6 +1238,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
1235 | break; | 1238 | break; |
1236 | case 0x0160: | 1239 | case 0x0160: |
1237 | case 0x01D0: | 1240 | case 0x01D0: |
1241 | case 0x0240: | ||
1238 | NV_WR32(par->PMC, 0x1700, | 1242 | NV_WR32(par->PMC, 0x1700, |
1239 | NV_RD32(par->PFB, 0x020C)); | 1243 | NV_RD32(par->PFB, 0x020C)); |
1240 | NV_WR32(par->PMC, 0x1704, 0); | 1244 | NV_WR32(par->PMC, 0x1704, 0); |
@@ -1359,7 +1363,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
1359 | if(((par->Chipset & 0xfff0) | 1363 | if(((par->Chipset & 0xfff0) |
1360 | != 0x0160) && | 1364 | != 0x0160) && |
1361 | ((par->Chipset & 0xfff0) | 1365 | ((par->Chipset & 0xfff0) |
1362 | != 0x0220)) | 1366 | != 0x0220) && |
1367 | ((par->Chipset & 0xfff0) | ||
1368 | != 0x240)) | ||
1363 | NV_WR32(par->PGRAPH, | 1369 | NV_WR32(par->PGRAPH, |
1364 | 0x6900 + i*4, | 1370 | 0x6900 + i*4, |
1365 | NV_RD32(par->PFB, | 1371 | NV_RD32(par->PFB, |