diff options
author | Michal Piotrowski <michal.k.k.piotrowski@gmail.com> | 2007-05-09 05:35:34 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-09 15:30:57 -0400 |
commit | bc0ca06e24545117b69c94b1219dbe19392a0c5a (patch) | |
tree | f7d2bdd1e205884280413e01c66ebfefab3f9af8 /drivers/video/nvidia/nv_hw.c | |
parent | 880169dd2edc4297b7811a0542be9766ca6945bc (diff) |
frame buffer: geforce 7300 gt
My geforce isn't supported by nvidia frame buffer.
/sbin/lspci
01:00.0 VGA compatible controller: nVidia Corporation Unknown device 02e2 (rev a2)
/usr/sbin/fbset -i
mode "1024x768-60"
# D: 65.003 MHz, H: 48.365 kHz, V: 60.006 Hz
geometry 1024 768 1024 32767 8
timings 15384 160 24 29 3 136 6
accel true
rgba 8/0,8/0,8/0,0/0
endmode
Frame buffer device information:
Name : NV2e
Address : 0xe0000000
Size : 134217728
Type : PACKED PIXELS
Visual : PSEUDOCOLOR
XPanStep : 8
YPanStep : 1
YWrapStep : 0
LineLength : 1024
MMIO Address: 0xf6000000
MMIO Size : 16777216
Accelerator : Unknown (46)
Here is a patch for this problem.
Signed-off-by: Michal Piotrowski <michal.k.k.piotrowski@gmail.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/nvidia/nv_hw.c')
-rw-r--r-- | drivers/video/nvidia/nv_hw.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c index f297c7b14a41..c627955aa124 100644 --- a/drivers/video/nvidia/nv_hw.c +++ b/drivers/video/nvidia/nv_hw.c | |||
@@ -149,8 +149,7 @@ static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk, | |||
149 | pll = NV_RD32(par->PMC, 0x4024); | 149 | pll = NV_RD32(par->PMC, 0x4024); |
150 | M = pll & 0xFF; | 150 | M = pll & 0xFF; |
151 | N = (pll >> 8) & 0xFF; | 151 | N = (pll >> 8) & 0xFF; |
152 | if (((par->Chipset & 0xfff0) == 0x0290) || | 152 | if (((par->Chipset & 0xfff0) == 0x0290) || ((par->Chipset & 0xfff0) == 0x0390) || ((par->Chipset & 0xfff0) == 0x02E0)) { |
153 | ((par->Chipset & 0xfff0) == 0x0390)) { | ||
154 | MB = 1; | 153 | MB = 1; |
155 | NB = 1; | 154 | NB = 1; |
156 | } else { | 155 | } else { |
@@ -963,6 +962,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
963 | 962 | ||
964 | if (((par->Chipset & 0xfff0) == 0x0090) || | 963 | if (((par->Chipset & 0xfff0) == 0x0090) || |
965 | ((par->Chipset & 0xfff0) == 0x01D0) || | 964 | ((par->Chipset & 0xfff0) == 0x01D0) || |
965 | ((par->Chipset & 0xfff0) == 0x02E0) || | ||
966 | ((par->Chipset & 0xfff0) == 0x0290)) | 966 | ((par->Chipset & 0xfff0) == 0x0290)) |
967 | regions = 15; | 967 | regions = 15; |
968 | for(i = 0; i < regions; i++) { | 968 | for(i = 0; i < regions; i++) { |
@@ -1275,6 +1275,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
1275 | 0x00100000); | 1275 | 0x00100000); |
1276 | break; | 1276 | break; |
1277 | case 0x0090: | 1277 | case 0x0090: |
1278 | case 0x02E0: | ||
1278 | case 0x0290: | 1279 | case 0x0290: |
1279 | NV_WR32(par->PRAMDAC, 0x0608, | 1280 | NV_WR32(par->PRAMDAC, 0x0608, |
1280 | NV_RD32(par->PRAMDAC, 0x0608) | | 1281 | NV_RD32(par->PRAMDAC, 0x0608) | |
@@ -1352,6 +1353,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
1352 | } else { | 1353 | } else { |
1353 | if (((par->Chipset & 0xfff0) == 0x0090) || | 1354 | if (((par->Chipset & 0xfff0) == 0x0090) || |
1354 | ((par->Chipset & 0xfff0) == 0x01D0) || | 1355 | ((par->Chipset & 0xfff0) == 0x01D0) || |
1356 | ((par->Chipset & 0xfff0) == 0x02E0) || | ||
1355 | ((par->Chipset & 0xfff0) == 0x0290)) { | 1357 | ((par->Chipset & 0xfff0) == 0x0290)) { |
1356 | for (i = 0; i < 60; i++) { | 1358 | for (i = 0; i < 60; i++) { |
1357 | NV_WR32(par->PGRAPH, | 1359 | NV_WR32(par->PGRAPH, |
@@ -1403,6 +1405,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
1403 | } else { | 1405 | } else { |
1404 | if ((par->Chipset & 0xfff0) == 0x0090 || | 1406 | if ((par->Chipset & 0xfff0) == 0x0090 || |
1405 | (par->Chipset & 0xfff0) == 0x01D0 || | 1407 | (par->Chipset & 0xfff0) == 0x01D0 || |
1408 | (par->Chipset & 0xfff0) == 0x02E0 || | ||
1406 | (par->Chipset & 0xfff0) == 0x0290) { | 1409 | (par->Chipset & 0xfff0) == 0x0290) { |
1407 | NV_WR32(par->PGRAPH, 0x0DF0, | 1410 | NV_WR32(par->PGRAPH, 0x0DF0, |
1408 | NV_RD32(par->PFB, 0x0200)); | 1411 | NV_RD32(par->PFB, 0x0200)); |