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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-02-13 08:31:38 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-04-17 01:10:19 -0400
commitf7018c21350204c4cf628462f229d44d03545254 (patch)
tree408787177164cf51cc06f7aabdb04fcff8d2b6aa /drivers/video/mbx
parentc26ef3eb3c11274bad1b64498d0a134f85755250 (diff)
video: move fbdev to drivers/video/fbdev
The drivers/video directory is a mess. It contains generic video related files, directories for backlight, console, linux logo, lots of fbdev device drivers, fbdev framework files. Make some order into the chaos by creating drivers/video/fbdev directory, and move all fbdev related files there. No functionality is changed, although I guess it is possible that some subtle Makefile build order related issue could be created by this patch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Clark <robdclark@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/video/mbx')
-rw-r--r--drivers/video/mbx/Makefile4
-rw-r--r--drivers/video/mbx/mbxdebugfs.c251
-rw-r--r--drivers/video/mbx/mbxfb.c1053
-rw-r--r--drivers/video/mbx/reg_bits.h613
-rw-r--r--drivers/video/mbx/regs.h195
5 files changed, 0 insertions, 2116 deletions
diff --git a/drivers/video/mbx/Makefile b/drivers/video/mbx/Makefile
deleted file mode 100644
index 16c1165cf9c7..000000000000
--- a/drivers/video/mbx/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
1# Makefile for the 2700G controller driver.
2
3obj-$(CONFIG_FB_MBX) += mbxfb.o
4obj-$(CONFIG_FB_MBX_DEBUG) += mbxfbdebugfs.o
diff --git a/drivers/video/mbx/mbxdebugfs.c b/drivers/video/mbx/mbxdebugfs.c
deleted file mode 100644
index 4449f249b0e7..000000000000
--- a/drivers/video/mbx/mbxdebugfs.c
+++ /dev/null
@@ -1,251 +0,0 @@
1#include <linux/debugfs.h>
2#include <linux/slab.h>
3
4#define BIG_BUFFER_SIZE (1024)
5
6static char big_buffer[BIG_BUFFER_SIZE];
7
8struct mbxfb_debugfs_data {
9 struct dentry *dir;
10 struct dentry *sysconf;
11 struct dentry *clock;
12 struct dentry *display;
13 struct dentry *gsctl;
14 struct dentry *sdram;
15 struct dentry *misc;
16};
17
18static int open_file_generic(struct inode *inode, struct file *file)
19{
20 file->private_data = inode->u.generic_ip;
21 return 0;
22}
23
24static ssize_t write_file_dummy(struct file *file, const char __user *buf,
25 size_t count, loff_t *ppos)
26{
27 return count;
28}
29
30static ssize_t sysconf_read_file(struct file *file, char __user *userbuf,
31 size_t count, loff_t *ppos)
32{
33 char * s = big_buffer;
34
35 s += sprintf(s, "SYSCFG = %08x\n", readl(SYSCFG));
36 s += sprintf(s, "PFBASE = %08x\n", readl(PFBASE));
37 s += sprintf(s, "PFCEIL = %08x\n", readl(PFCEIL));
38 s += sprintf(s, "POLLFLAG = %08x\n", readl(POLLFLAG));
39 s += sprintf(s, "SYSRST = %08x\n", readl(SYSRST));
40
41 return simple_read_from_buffer(userbuf, count, ppos,
42 big_buffer, s-big_buffer);
43}
44
45
46static ssize_t gsctl_read_file(struct file *file, char __user *userbuf,
47 size_t count, loff_t *ppos)
48{
49 char * s = big_buffer;
50
51 s += sprintf(s, "GSCTRL = %08x\n", readl(GSCTRL));
52 s += sprintf(s, "VSCTRL = %08x\n", readl(VSCTRL));
53 s += sprintf(s, "GBBASE = %08x\n", readl(GBBASE));
54 s += sprintf(s, "VBBASE = %08x\n", readl(VBBASE));
55 s += sprintf(s, "GDRCTRL = %08x\n", readl(GDRCTRL));
56 s += sprintf(s, "VCMSK = %08x\n", readl(VCMSK));
57 s += sprintf(s, "GSCADR = %08x\n", readl(GSCADR));
58 s += sprintf(s, "VSCADR = %08x\n", readl(VSCADR));
59 s += sprintf(s, "VUBASE = %08x\n", readl(VUBASE));
60 s += sprintf(s, "VVBASE = %08x\n", readl(VVBASE));
61 s += sprintf(s, "GSADR = %08x\n", readl(GSADR));
62 s += sprintf(s, "VSADR = %08x\n", readl(VSADR));
63 s += sprintf(s, "HCCTRL = %08x\n", readl(HCCTRL));
64 s += sprintf(s, "HCSIZE = %08x\n", readl(HCSIZE));
65 s += sprintf(s, "HCPOS = %08x\n", readl(HCPOS));
66 s += sprintf(s, "HCBADR = %08x\n", readl(HCBADR));
67 s += sprintf(s, "HCCKMSK = %08x\n", readl(HCCKMSK));
68 s += sprintf(s, "GPLUT = %08x\n", readl(GPLUT));
69
70 return simple_read_from_buffer(userbuf, count, ppos,
71 big_buffer, s-big_buffer);
72}
73
74static ssize_t display_read_file(struct file *file, char __user *userbuf,
75 size_t count, loff_t *ppos)
76{
77 char * s = big_buffer;
78
79 s += sprintf(s, "DSCTRL = %08x\n", readl(DSCTRL));
80 s += sprintf(s, "DHT01 = %08x\n", readl(DHT01));
81 s += sprintf(s, "DHT02 = %08x\n", readl(DHT02));
82 s += sprintf(s, "DHT03 = %08x\n", readl(DHT03));
83 s += sprintf(s, "DVT01 = %08x\n", readl(DVT01));
84 s += sprintf(s, "DVT02 = %08x\n", readl(DVT02));
85 s += sprintf(s, "DVT03 = %08x\n", readl(DVT03));
86 s += sprintf(s, "DBCOL = %08x\n", readl(DBCOL));
87 s += sprintf(s, "BGCOLOR = %08x\n", readl(BGCOLOR));
88 s += sprintf(s, "DINTRS = %08x\n", readl(DINTRS));
89 s += sprintf(s, "DINTRE = %08x\n", readl(DINTRE));
90 s += sprintf(s, "DINTRCNT = %08x\n", readl(DINTRCNT));
91 s += sprintf(s, "DSIG = %08x\n", readl(DSIG));
92 s += sprintf(s, "DMCTRL = %08x\n", readl(DMCTRL));
93 s += sprintf(s, "CLIPCTRL = %08x\n", readl(CLIPCTRL));
94 s += sprintf(s, "SPOCTRL = %08x\n", readl(SPOCTRL));
95 s += sprintf(s, "SVCTRL = %08x\n", readl(SVCTRL));
96 s += sprintf(s, "DLSTS = %08x\n", readl(DLSTS));
97 s += sprintf(s, "DLLCTRL = %08x\n", readl(DLLCTRL));
98 s += sprintf(s, "DVLNUM = %08x\n", readl(DVLNUM));
99 s += sprintf(s, "DUCTRL = %08x\n", readl(DUCTRL));
100 s += sprintf(s, "DVECTRL = %08x\n", readl(DVECTRL));
101 s += sprintf(s, "DHDET = %08x\n", readl(DHDET));
102 s += sprintf(s, "DVDET = %08x\n", readl(DVDET));
103 s += sprintf(s, "DODMSK = %08x\n", readl(DODMSK));
104 s += sprintf(s, "CSC01 = %08x\n", readl(CSC01));
105 s += sprintf(s, "CSC02 = %08x\n", readl(CSC02));
106 s += sprintf(s, "CSC03 = %08x\n", readl(CSC03));
107 s += sprintf(s, "CSC04 = %08x\n", readl(CSC04));
108 s += sprintf(s, "CSC05 = %08x\n", readl(CSC05));
109
110 return simple_read_from_buffer(userbuf, count, ppos,
111 big_buffer, s-big_buffer);
112}
113
114static ssize_t clock_read_file(struct file *file, char __user *userbuf,
115 size_t count, loff_t *ppos)
116{
117 char * s = big_buffer;
118
119 s += sprintf(s, "SYSCLKSRC = %08x\n", readl(SYSCLKSRC));
120 s += sprintf(s, "PIXCLKSRC = %08x\n", readl(PIXCLKSRC));
121 s += sprintf(s, "CLKSLEEP = %08x\n", readl(CLKSLEEP));
122 s += sprintf(s, "COREPLL = %08x\n", readl(COREPLL));
123 s += sprintf(s, "DISPPLL = %08x\n", readl(DISPPLL));
124 s += sprintf(s, "PLLSTAT = %08x\n", readl(PLLSTAT));
125 s += sprintf(s, "VOVRCLK = %08x\n", readl(VOVRCLK));
126 s += sprintf(s, "PIXCLK = %08x\n", readl(PIXCLK));
127 s += sprintf(s, "MEMCLK = %08x\n", readl(MEMCLK));
128 s += sprintf(s, "M24CLK = %08x\n", readl(M24CLK));
129 s += sprintf(s, "MBXCLK = %08x\n", readl(MBXCLK));
130 s += sprintf(s, "SDCLK = %08x\n", readl(SDCLK));
131 s += sprintf(s, "PIXCLKDIV = %08x\n", readl(PIXCLKDIV));
132
133 return simple_read_from_buffer(userbuf, count, ppos,
134 big_buffer, s-big_buffer);
135}
136
137static ssize_t sdram_read_file(struct file *file, char __user *userbuf,
138 size_t count, loff_t *ppos)
139{
140 char * s = big_buffer;
141
142 s += sprintf(s, "LMRST = %08x\n", readl(LMRST));
143 s += sprintf(s, "LMCFG = %08x\n", readl(LMCFG));
144 s += sprintf(s, "LMPWR = %08x\n", readl(LMPWR));
145 s += sprintf(s, "LMPWRSTAT = %08x\n", readl(LMPWRSTAT));
146 s += sprintf(s, "LMCEMR = %08x\n", readl(LMCEMR));
147 s += sprintf(s, "LMTYPE = %08x\n", readl(LMTYPE));
148 s += sprintf(s, "LMTIM = %08x\n", readl(LMTIM));
149 s += sprintf(s, "LMREFRESH = %08x\n", readl(LMREFRESH));
150 s += sprintf(s, "LMPROTMIN = %08x\n", readl(LMPROTMIN));
151 s += sprintf(s, "LMPROTMAX = %08x\n", readl(LMPROTMAX));
152 s += sprintf(s, "LMPROTCFG = %08x\n", readl(LMPROTCFG));
153 s += sprintf(s, "LMPROTERR = %08x\n", readl(LMPROTERR));
154
155 return simple_read_from_buffer(userbuf, count, ppos,
156 big_buffer, s-big_buffer);
157}
158
159static ssize_t misc_read_file(struct file *file, char __user *userbuf,
160 size_t count, loff_t *ppos)
161{
162 char * s = big_buffer;
163
164 s += sprintf(s, "LCD_CONFIG = %08x\n", readl(LCD_CONFIG));
165 s += sprintf(s, "ODFBPWR = %08x\n", readl(ODFBPWR));
166 s += sprintf(s, "ODFBSTAT = %08x\n", readl(ODFBSTAT));
167 s += sprintf(s, "ID = %08x\n", readl(ID));
168
169 return simple_read_from_buffer(userbuf, count, ppos,
170 big_buffer, s-big_buffer);
171}
172
173
174static const struct file_operations sysconf_fops = {
175 .read = sysconf_read_file,
176 .write = write_file_dummy,
177 .open = open_file_generic,
178 .llseek = default_llseek,
179};
180
181static const struct file_operations clock_fops = {
182 .read = clock_read_file,
183 .write = write_file_dummy,
184 .open = open_file_generic,
185 .llseek = default_llseek,
186};
187
188static const struct file_operations display_fops = {
189 .read = display_read_file,
190 .write = write_file_dummy,
191 .open = open_file_generic,
192 .llseek = default_llseek,
193};
194
195static const struct file_operations gsctl_fops = {
196 .read = gsctl_read_file,
197 .write = write_file_dummy,
198 .open = open_file_generic,
199 .llseek = default_llseek,
200};
201
202static const struct file_operations sdram_fops = {
203 .read = sdram_read_file,
204 .write = write_file_dummy,
205 .open = open_file_generic,
206 .llseek = default_llseek,
207};
208
209static const struct file_operations misc_fops = {
210 .read = misc_read_file,
211 .write = write_file_dummy,
212 .open = open_file_generic,
213 .llseek = default_llseek,
214};
215
216static void mbxfb_debugfs_init(struct fb_info *fbi)
217{
218 struct mbxfb_info *mfbi = fbi->par;
219 struct mbxfb_debugfs_data *dbg;
220
221 dbg = kzalloc(sizeof(struct mbxfb_debugfs_data), GFP_KERNEL);
222 mfbi->debugfs_data = dbg;
223
224 dbg->dir = debugfs_create_dir("mbxfb", NULL);
225 dbg->sysconf = debugfs_create_file("sysconf", 0444, dbg->dir,
226 fbi, &sysconf_fops);
227 dbg->clock = debugfs_create_file("clock", 0444, dbg->dir,
228 fbi, &clock_fops);
229 dbg->display = debugfs_create_file("display", 0444, dbg->dir,
230 fbi, &display_fops);
231 dbg->gsctl = debugfs_create_file("gsctl", 0444, dbg->dir,
232 fbi, &gsctl_fops);
233 dbg->sdram = debugfs_create_file("sdram", 0444, dbg->dir,
234 fbi, &sdram_fops);
235 dbg->misc = debugfs_create_file("misc", 0444, dbg->dir,
236 fbi, &misc_fops);
237}
238
239static void mbxfb_debugfs_remove(struct fb_info *fbi)
240{
241 struct mbxfb_info *mfbi = fbi->par;
242 struct mbxfb_debugfs_data *dbg = mfbi->debugfs_data;
243
244 debugfs_remove(dbg->misc);
245 debugfs_remove(dbg->sdram);
246 debugfs_remove(dbg->gsctl);
247 debugfs_remove(dbg->display);
248 debugfs_remove(dbg->clock);
249 debugfs_remove(dbg->sysconf);
250 debugfs_remove(dbg->dir);
251}
diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
deleted file mode 100644
index f0a5392f5fd3..000000000000
--- a/drivers/video/mbx/mbxfb.c
+++ /dev/null
@@ -1,1053 +0,0 @@
1/*
2 * linux/drivers/video/mbx/mbxfb.c
3 *
4 * Copyright (C) 2006-2007 8D Technologies inc
5 * Raphael Assenat <raph@8d.com>
6 * - Added video overlay support
7 * - Various improvements
8 *
9 * Copyright (C) 2006 Compulab, Ltd.
10 * Mike Rapoport <mike@compulab.co.il>
11 * - Creation of driver
12 *
13 * Based on pxafb.c
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file COPYING in the main directory of this archive for
17 * more details.
18 *
19 * Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
20 *
21 */
22
23#include <linux/delay.h>
24#include <linux/fb.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/uaccess.h>
29#include <linux/io.h>
30
31#include <video/mbxfb.h>
32
33#include "regs.h"
34#include "reg_bits.h"
35
36static void __iomem *virt_base_2700;
37
38#define write_reg(val, reg) do { writel((val), (reg)); } while(0)
39
40/* Without this delay, the graphics appears somehow scaled and
41 * there is a lot of jitter in scanlines. This delay is probably
42 * needed only after setting some specific register(s) somewhere,
43 * not all over the place... */
44#define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0)
45
46#define MIN_XRES 16
47#define MIN_YRES 16
48#define MAX_XRES 2048
49#define MAX_YRES 2048
50
51#define MAX_PALETTES 16
52
53/* FIXME: take care of different chip revisions with different sizes
54 of ODFB */
55#define MEMORY_OFFSET 0x60000
56
57struct mbxfb_info {
58 struct device *dev;
59
60 struct resource *fb_res;
61 struct resource *fb_req;
62
63 struct resource *reg_res;
64 struct resource *reg_req;
65
66 void __iomem *fb_virt_addr;
67 unsigned long fb_phys_addr;
68
69 void __iomem *reg_virt_addr;
70 unsigned long reg_phys_addr;
71
72 int (*platform_probe) (struct fb_info * fb);
73 int (*platform_remove) (struct fb_info * fb);
74
75 u32 pseudo_palette[MAX_PALETTES];
76#ifdef CONFIG_FB_MBX_DEBUG
77 void *debugfs_data;
78#endif
79
80};
81
82static struct fb_var_screeninfo mbxfb_default = {
83 .xres = 640,
84 .yres = 480,
85 .xres_virtual = 640,
86 .yres_virtual = 480,
87 .bits_per_pixel = 16,
88 .red = {11, 5, 0},
89 .green = {5, 6, 0},
90 .blue = {0, 5, 0},
91 .activate = FB_ACTIVATE_TEST,
92 .height = -1,
93 .width = -1,
94 .pixclock = 40000,
95 .left_margin = 48,
96 .right_margin = 16,
97 .upper_margin = 33,
98 .lower_margin = 10,
99 .hsync_len = 96,
100 .vsync_len = 2,
101 .vmode = FB_VMODE_NONINTERLACED,
102 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
103};
104
105static struct fb_fix_screeninfo mbxfb_fix = {
106 .id = "MBX",
107 .type = FB_TYPE_PACKED_PIXELS,
108 .visual = FB_VISUAL_TRUECOLOR,
109 .xpanstep = 0,
110 .ypanstep = 0,
111 .ywrapstep = 0,
112 .accel = FB_ACCEL_NONE,
113};
114
115struct pixclock_div {
116 u8 m;
117 u8 n;
118 u8 p;
119};
120
121static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps,
122 struct pixclock_div *div)
123{
124 u8 m, n, p;
125 unsigned int err = 0;
126 unsigned int min_err = ~0x0;
127 unsigned int clk;
128 unsigned int best_clk = 0;
129 unsigned int ref_clk = 13000; /* FIXME: take from platform data */
130 unsigned int pixclock;
131
132 /* convert pixclock to KHz */
133 pixclock = PICOS2KHZ(pixclock_ps);
134
135 /* PLL output freq = (ref_clk * M) / (N * 2^P)
136 *
137 * M: 1 to 63
138 * N: 1 to 7
139 * P: 0 to 7
140 */
141
142 /* RAPH: When N==1, the resulting pixel clock appears to
143 * get divided by 2. Preventing N=1 by starting the following
144 * loop at 2 prevents this. Is this a bug with my chip
145 * revision or something I dont understand? */
146 for (m = 1; m < 64; m++) {
147 for (n = 2; n < 8; n++) {
148 for (p = 0; p < 8; p++) {
149 clk = (ref_clk * m) / (n * (1 << p));
150 err = (clk > pixclock) ? (clk - pixclock) :
151 (pixclock - clk);
152 if (err < min_err) {
153 min_err = err;
154 best_clk = clk;
155 div->m = m;
156 div->n = n;
157 div->p = p;
158 }
159 }
160 }
161 }
162 return KHZ2PICOS(best_clk);
163}
164
165static int mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
166 u_int trans, struct fb_info *info)
167{
168 u32 val, ret = 1;
169
170 if (regno < MAX_PALETTES) {
171 u32 *pal = info->pseudo_palette;
172
173 val = (red & 0xf800) | ((green & 0xfc00) >> 5) |
174 ((blue & 0xf800) >> 11);
175 pal[regno] = val;
176 ret = 0;
177 }
178
179 return ret;
180}
181
182static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
183{
184 struct pixclock_div div;
185
186 var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
187
188 if (var->xres < MIN_XRES)
189 var->xres = MIN_XRES;
190 if (var->yres < MIN_YRES)
191 var->yres = MIN_YRES;
192 if (var->xres > MAX_XRES)
193 return -EINVAL;
194 if (var->yres > MAX_YRES)
195 return -EINVAL;
196 var->xres_virtual = max(var->xres_virtual, var->xres);
197 var->yres_virtual = max(var->yres_virtual, var->yres);
198
199 switch (var->bits_per_pixel) {
200 /* 8 bits-per-pixel is not supported yet */
201 case 8:
202 return -EINVAL;
203 case 16:
204 var->green.length = (var->green.length == 5) ? 5 : 6;
205 var->red.length = 5;
206 var->blue.length = 5;
207 var->transp.length = 6 - var->green.length;
208 var->blue.offset = 0;
209 var->green.offset = 5;
210 var->red.offset = 5 + var->green.length;
211 var->transp.offset = (5 + var->red.offset) & 15;
212 break;
213 case 24: /* RGB 888 */
214 case 32: /* RGBA 8888 */
215 var->red.offset = 16;
216 var->red.length = 8;
217 var->green.offset = 8;
218 var->green.length = 8;
219 var->blue.offset = 0;
220 var->blue.length = 8;
221 var->transp.length = var->bits_per_pixel - 24;
222 var->transp.offset = (var->transp.length) ? 24 : 0;
223 break;
224 }
225 var->red.msb_right = 0;
226 var->green.msb_right = 0;
227 var->blue.msb_right = 0;
228 var->transp.msb_right = 0;
229
230 return 0;
231}
232
233static int mbxfb_set_par(struct fb_info *info)
234{
235 struct fb_var_screeninfo *var = &info->var;
236 struct pixclock_div div;
237 ushort hbps, ht, hfps, has;
238 ushort vbps, vt, vfps, vas;
239 u32 gsctrl = readl(GSCTRL);
240 u32 gsadr = readl(GSADR);
241
242 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
243
244 /* setup color mode */
245 gsctrl &= ~(FMsk(GSCTRL_GPIXFMT));
246 /* FIXME: add *WORKING* support for 8-bits per color */
247 if (info->var.bits_per_pixel == 8) {
248 return -EINVAL;
249 } else {
250 fb_dealloc_cmap(&info->cmap);
251 gsctrl &= ~GSCTRL_LUT_EN;
252
253 info->fix.visual = FB_VISUAL_TRUECOLOR;
254 switch (info->var.bits_per_pixel) {
255 case 16:
256 if (info->var.green.length == 5)
257 gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
258 else
259 gsctrl |= GSCTRL_GPIXFMT_RGB565;
260 break;
261 case 24:
262 gsctrl |= GSCTRL_GPIXFMT_RGB888;
263 break;
264 case 32:
265 gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
266 break;
267 }
268 }
269
270 /* setup resolution */
271 gsctrl &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
272 gsctrl |= Gsctrl_Width(info->var.xres) |
273 Gsctrl_Height(info->var.yres);
274 write_reg_dly(gsctrl, GSCTRL);
275
276 gsadr &= ~(FMsk(GSADR_SRCSTRIDE));
277 gsadr |= Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel /
278 (8 * 16) - 1);
279 write_reg_dly(gsadr, GSADR);
280
281 /* setup timings */
282 var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
283
284 write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |
285 Disp_Pll_P(div.p) | DISP_PLL_EN), DISPPLL);
286
287 hbps = var->hsync_len;
288 has = hbps + var->left_margin;
289 hfps = has + var->xres;
290 ht = hfps + var->right_margin;
291
292 vbps = var->vsync_len;
293 vas = vbps + var->upper_margin;
294 vfps = vas + var->yres;
295 vt = vfps + var->lower_margin;
296
297 write_reg_dly((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);
298 write_reg_dly((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);
299 write_reg_dly((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);
300 write_reg_dly((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);
301
302 write_reg_dly((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);
303 write_reg_dly((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);
304 write_reg_dly((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);
305 write_reg_dly((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);
306 write_reg_dly((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);
307
308 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
309
310 write_reg_dly(DINTRE_VEVENT0_EN, DINTRE);
311
312 return 0;
313}
314
315static int mbxfb_blank(int blank, struct fb_info *info)
316{
317 switch (blank) {
318 case FB_BLANK_POWERDOWN:
319 case FB_BLANK_VSYNC_SUSPEND:
320 case FB_BLANK_HSYNC_SUSPEND:
321 case FB_BLANK_NORMAL:
322 write_reg_dly((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);
323 write_reg_dly((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);
324 write_reg_dly((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);
325 break;
326 case FB_BLANK_UNBLANK:
327 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
328 write_reg_dly((readl(PIXCLK) | PIXCLK_EN), PIXCLK);
329 break;
330 }
331 return 0;
332}
333
334static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
335{
336 u32 vsctrl, vscadr, vsadr;
337 u32 sssize, spoctrl, shctrl;
338 u32 vubase, vvbase;
339 u32 vovrclk;
340
341 if (set->scaled_width==0 || set->scaled_height==0)
342 return -EINVAL;
343
344 /* read registers which have reserved bits
345 * so we can write them back as-is. */
346 vovrclk = readl(VOVRCLK);
347 vsctrl = readl(VSCTRL);
348 vscadr = readl(VSCADR);
349 vubase = readl(VUBASE);
350 vvbase = readl(VVBASE);
351 shctrl = readl(SHCTRL);
352
353 spoctrl = readl(SPOCTRL);
354 sssize = readl(SSSIZE);
355
356 vsctrl &= ~( FMsk(VSCTRL_VSWIDTH) |
357 FMsk(VSCTRL_VSHEIGHT) |
358 FMsk(VSCTRL_VPIXFMT) |
359 VSCTRL_GAMMA_EN | VSCTRL_CSC_EN |
360 VSCTRL_COSITED );
361 vsctrl |= Vsctrl_Width(set->width) | Vsctrl_Height(set->height) |
362 VSCTRL_CSC_EN;
363
364 vscadr &= ~(VSCADR_STR_EN | FMsk(VSCADR_VBASE_ADR) );
365 vubase &= ~(VUBASE_UVHALFSTR | FMsk(VUBASE_UBASE_ADR));
366 vvbase &= ~(FMsk(VVBASE_VBASE_ADR));
367
368 switch (set->fmt) {
369 case MBXFB_FMT_YUV16:
370 vsctrl |= VSCTRL_VPIXFMT_YUV12;
371
372 set->Y_stride = ((set->width) + 0xf ) & ~0xf;
373 break;
374 case MBXFB_FMT_YUV12:
375 vsctrl |= VSCTRL_VPIXFMT_YUV12;
376
377 set->Y_stride = ((set->width) + 0xf ) & ~0xf;
378 vubase |= VUBASE_UVHALFSTR;
379
380 break;
381 case MBXFB_FMT_UY0VY1:
382 vsctrl |= VSCTRL_VPIXFMT_UY0VY1;
383 set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
384 break;
385 case MBXFB_FMT_VY0UY1:
386 vsctrl |= VSCTRL_VPIXFMT_VY0UY1;
387 set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
388 break;
389 case MBXFB_FMT_Y0UY1V:
390 vsctrl |= VSCTRL_VPIXFMT_Y0UY1V;
391 set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
392 break;
393 case MBXFB_FMT_Y0VY1U:
394 vsctrl |= VSCTRL_VPIXFMT_Y0VY1U;
395 set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
396 break;
397 default:
398 return -EINVAL;
399 }
400
401 /* VSCTRL has the bits which sets the Video Pixel Format.
402 * When passing from a packed to planar format,
403 * if we write VSCTRL first, VVBASE and VUBASE would
404 * be zero if we would not set them here. (And then,
405 * the chips hangs and only a reset seems to fix it).
406 *
407 * If course, the values calculated here have no meaning
408 * for packed formats.
409 */
410 set->UV_stride = ((set->width/2) + 0x7 ) & ~0x7;
411 set->U_offset = set->height * set->Y_stride;
412 set->V_offset = set->U_offset +
413 set->height * set->UV_stride;
414 vubase |= Vubase_Ubase_Adr(
415 (0x60000 + set->mem_offset + set->U_offset)>>3);
416 vvbase |= Vvbase_Vbase_Adr(
417 (0x60000 + set->mem_offset + set->V_offset)>>3);
418
419
420 vscadr |= Vscadr_Vbase_Adr((0x60000 + set->mem_offset)>>4);
421
422 if (set->enable)
423 vscadr |= VSCADR_STR_EN;
424
425
426 vsadr = Vsadr_Srcstride((set->Y_stride)/16-1) |
427 Vsadr_Xstart(set->x) | Vsadr_Ystart(set->y);
428
429 sssize &= ~(FMsk(SSSIZE_SC_WIDTH) | FMsk(SSSIZE_SC_HEIGHT));
430 sssize = Sssize_Sc_Width(set->scaled_width-1) |
431 Sssize_Sc_Height(set->scaled_height-1);
432
433 spoctrl &= ~(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP |
434 SPOCTRL_HV_SC_OR | SPOCTRL_VS_UR_C |
435 FMsk(SPOCTRL_VPITCH));
436 spoctrl |= Spoctrl_Vpitch((set->height<<11)/set->scaled_height);
437
438 /* Bypass horiz/vert scaler when same size */
439 if (set->scaled_width == set->width)
440 spoctrl |= SPOCTRL_H_SC_BP;
441 if (set->scaled_height == set->height)
442 spoctrl |= SPOCTRL_V_SC_BP;
443
444 shctrl &= ~(FMsk(SHCTRL_HPITCH) | SHCTRL_HDECIM);
445 shctrl |= Shctrl_Hpitch((set->width<<11)/set->scaled_width);
446
447 /* Video plane registers */
448 write_reg(vsctrl, VSCTRL);
449 write_reg(vscadr, VSCADR);
450 write_reg(vubase, VUBASE);
451 write_reg(vvbase, VVBASE);
452 write_reg(vsadr, VSADR);
453
454 /* Video scaler registers */
455 write_reg(sssize, SSSIZE);
456 write_reg(spoctrl, SPOCTRL);
457 write_reg(shctrl, SHCTRL);
458
459 /* Clock */
460 if (set->enable)
461 vovrclk |= 1;
462 else
463 vovrclk &= ~1;
464
465 write_reg(vovrclk, VOVRCLK);
466
467 return 0;
468}
469
470static int mbxfb_ioctl_planeorder(struct mbxfb_planeorder *porder)
471{
472 unsigned long gscadr, vscadr;
473
474 if (porder->bottom == porder->top)
475 return -EINVAL;
476
477 gscadr = readl(GSCADR);
478 vscadr = readl(VSCADR);
479
480 gscadr &= ~(FMsk(GSCADR_BLEND_POS));
481 vscadr &= ~(FMsk(VSCADR_BLEND_POS));
482
483 switch (porder->bottom) {
484 case MBXFB_PLANE_GRAPHICS:
485 gscadr |= GSCADR_BLEND_GFX;
486 break;
487 case MBXFB_PLANE_VIDEO:
488 vscadr |= VSCADR_BLEND_GFX;
489 break;
490 default:
491 return -EINVAL;
492 }
493
494 switch (porder->top) {
495 case MBXFB_PLANE_GRAPHICS:
496 gscadr |= GSCADR_BLEND_VID;
497 break;
498 case MBXFB_PLANE_VIDEO:
499 vscadr |= GSCADR_BLEND_VID;
500 break;
501 default:
502 return -EINVAL;
503 }
504
505 write_reg_dly(vscadr, VSCADR);
506 write_reg_dly(gscadr, GSCADR);
507
508 return 0;
509
510}
511
512static int mbxfb_ioctl_alphactl(struct mbxfb_alphaCtl *alpha)
513{
514 unsigned long vscadr, vbbase, vcmsk;
515 unsigned long gscadr, gbbase, gdrctrl;
516
517 vbbase = Vbbase_Glalpha(alpha->overlay_global_alpha) |
518 Vbbase_Colkey(alpha->overlay_colorkey);
519
520 gbbase = Gbbase_Glalpha(alpha->graphics_global_alpha) |
521 Gbbase_Colkey(alpha->graphics_colorkey);
522
523 vcmsk = readl(VCMSK);
524 vcmsk &= ~(FMsk(VCMSK_COLKEY_M));
525 vcmsk |= Vcmsk_colkey_m(alpha->overlay_colorkey_mask);
526
527 gdrctrl = readl(GDRCTRL);
528 gdrctrl &= ~(FMsk(GDRCTRL_COLKEYM));
529 gdrctrl |= Gdrctrl_Colkeym(alpha->graphics_colorkey_mask);
530
531 vscadr = readl(VSCADR);
532 vscadr &= ~(FMsk(VSCADR_BLEND_M) | VSCADR_COLKEYSRC | VSCADR_COLKEY_EN);
533
534 gscadr = readl(GSCADR);
535 gscadr &= ~(FMsk(GSCADR_BLEND_M) | GSCADR_COLKEY_EN | GSCADR_COLKEYSRC);
536
537 switch (alpha->overlay_colorkey_mode) {
538 case MBXFB_COLORKEY_DISABLED:
539 break;
540 case MBXFB_COLORKEY_PREVIOUS:
541 vscadr |= VSCADR_COLKEY_EN;
542 break;
543 case MBXFB_COLORKEY_CURRENT:
544 vscadr |= VSCADR_COLKEY_EN | VSCADR_COLKEYSRC;
545 break;
546 default:
547 return -EINVAL;
548 }
549
550 switch (alpha->overlay_blend_mode) {
551 case MBXFB_ALPHABLEND_NONE:
552 vscadr |= VSCADR_BLEND_NONE;
553 break;
554 case MBXFB_ALPHABLEND_GLOBAL:
555 vscadr |= VSCADR_BLEND_GLOB;
556 break;
557 case MBXFB_ALPHABLEND_PIXEL:
558 vscadr |= VSCADR_BLEND_PIX;
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 switch (alpha->graphics_colorkey_mode) {
565 case MBXFB_COLORKEY_DISABLED:
566 break;
567 case MBXFB_COLORKEY_PREVIOUS:
568 gscadr |= GSCADR_COLKEY_EN;
569 break;
570 case MBXFB_COLORKEY_CURRENT:
571 gscadr |= GSCADR_COLKEY_EN | GSCADR_COLKEYSRC;
572 break;
573 default:
574 return -EINVAL;
575 }
576
577 switch (alpha->graphics_blend_mode) {
578 case MBXFB_ALPHABLEND_NONE:
579 gscadr |= GSCADR_BLEND_NONE;
580 break;
581 case MBXFB_ALPHABLEND_GLOBAL:
582 gscadr |= GSCADR_BLEND_GLOB;
583 break;
584 case MBXFB_ALPHABLEND_PIXEL:
585 gscadr |= GSCADR_BLEND_PIX;
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 write_reg_dly(vbbase, VBBASE);
592 write_reg_dly(gbbase, GBBASE);
593 write_reg_dly(vcmsk, VCMSK);
594 write_reg_dly(gdrctrl, GDRCTRL);
595 write_reg_dly(gscadr, GSCADR);
596 write_reg_dly(vscadr, VSCADR);
597
598 return 0;
599}
600
601static int mbxfb_ioctl(struct fb_info *info, unsigned int cmd,
602 unsigned long arg)
603{
604 struct mbxfb_overlaySetup setup;
605 struct mbxfb_planeorder porder;
606 struct mbxfb_alphaCtl alpha;
607 struct mbxfb_reg reg;
608 int res;
609 __u32 tmp;
610
611 switch (cmd)
612 {
613 case MBXFB_IOCX_OVERLAY:
614 if (copy_from_user(&setup, (void __user*)arg,
615 sizeof(struct mbxfb_overlaySetup)))
616 return -EFAULT;
617
618 res = mbxfb_setupOverlay(&setup);
619 if (res)
620 return res;
621
622 if (copy_to_user((void __user*)arg, &setup,
623 sizeof(struct mbxfb_overlaySetup)))
624 return -EFAULT;
625
626 return 0;
627
628 case MBXFB_IOCS_PLANEORDER:
629 if (copy_from_user(&porder, (void __user*)arg,
630 sizeof(struct mbxfb_planeorder)))
631 return -EFAULT;
632
633 return mbxfb_ioctl_planeorder(&porder);
634
635 case MBXFB_IOCS_ALPHA:
636 if (copy_from_user(&alpha, (void __user*)arg,
637 sizeof(struct mbxfb_alphaCtl)))
638 return -EFAULT;
639
640 return mbxfb_ioctl_alphactl(&alpha);
641
642 case MBXFB_IOCS_REG:
643 if (copy_from_user(&reg, (void __user*)arg,
644 sizeof(struct mbxfb_reg)))
645 return -EFAULT;
646
647 if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */
648 return -EINVAL;
649
650 tmp = readl(virt_base_2700 + reg.addr);
651 tmp &= ~reg.mask;
652 tmp |= reg.val & reg.mask;
653 writel(tmp, virt_base_2700 + reg.addr);
654
655 return 0;
656 case MBXFB_IOCX_REG:
657 if (copy_from_user(&reg, (void __user*)arg,
658 sizeof(struct mbxfb_reg)))
659 return -EFAULT;
660
661 if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */
662 return -EINVAL;
663 reg.val = readl(virt_base_2700 + reg.addr);
664
665 if (copy_to_user((void __user*)arg, &reg,
666 sizeof(struct mbxfb_reg)))
667 return -EFAULT;
668
669 return 0;
670 }
671 return -EINVAL;
672}
673
674static struct fb_ops mbxfb_ops = {
675 .owner = THIS_MODULE,
676 .fb_check_var = mbxfb_check_var,
677 .fb_set_par = mbxfb_set_par,
678 .fb_setcolreg = mbxfb_setcolreg,
679 .fb_fillrect = cfb_fillrect,
680 .fb_copyarea = cfb_copyarea,
681 .fb_imageblit = cfb_imageblit,
682 .fb_blank = mbxfb_blank,
683 .fb_ioctl = mbxfb_ioctl,
684};
685
686/*
687 Enable external SDRAM controller. Assume that all clocks are active
688 by now.
689*/
690static void setup_memc(struct fb_info *fbi)
691{
692 unsigned long tmp;
693 int i;
694
695 /* FIXME: use platform specific parameters */
696 /* setup SDRAM controller */
697 write_reg_dly((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |
698 LMCFG_LMA_TS),
699 LMCFG);
700
701 write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
702
703 /* setup SDRAM timings */
704 write_reg_dly((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |
705 Lmtim_Trc(9) | Lmtim_Tdpl(2)),
706 LMTIM);
707 /* setup SDRAM refresh rate */
708 write_reg_dly(0xc2b, LMREFRESH);
709 /* setup SDRAM type parameters */
710 write_reg_dly((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
711 LMTYPE_COLSZ_8),
712 LMTYPE);
713 /* enable memory controller */
714 write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
715 /* perform dummy reads */
716 for ( i = 0; i < 16; i++ ) {
717 tmp = readl(fbi->screen_base);
718 }
719}
720
721static void enable_clocks(struct fb_info *fbi)
722{
723 /* enable clocks */
724 write_reg_dly(SYSCLKSRC_PLL_2, SYSCLKSRC);
725 write_reg_dly(PIXCLKSRC_PLL_1, PIXCLKSRC);
726 write_reg_dly(0x00000000, CLKSLEEP);
727
728 /* PLL output = (Frefclk * M) / (N * 2^P )
729 *
730 * M: 0x17, N: 0x3, P: 0x0 == 100 Mhz!
731 * M: 0xb, N: 0x1, P: 0x1 == 71 Mhz
732 * */
733 write_reg_dly((Core_Pll_M(0xb) | Core_Pll_N(0x1) | Core_Pll_P(0x1) |
734 CORE_PLL_EN),
735 COREPLL);
736
737 write_reg_dly((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |
738 DISP_PLL_EN),
739 DISPPLL);
740
741 write_reg_dly(0x00000000, VOVRCLK);
742 write_reg_dly(PIXCLK_EN, PIXCLK);
743 write_reg_dly(MEMCLK_EN, MEMCLK);
744 write_reg_dly(0x00000001, M24CLK);
745 write_reg_dly(0x00000001, MBXCLK);
746 write_reg_dly(SDCLK_EN, SDCLK);
747 write_reg_dly(0x00000001, PIXCLKDIV);
748}
749
750static void setup_graphics(struct fb_info *fbi)
751{
752 unsigned long gsctrl;
753 unsigned long vscadr;
754
755 gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres) |
756 Gsctrl_Height(fbi->var.yres);
757 switch (fbi->var.bits_per_pixel) {
758 case 16:
759 if (fbi->var.green.length == 5)
760 gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
761 else
762 gsctrl |= GSCTRL_GPIXFMT_RGB565;
763 break;
764 case 24:
765 gsctrl |= GSCTRL_GPIXFMT_RGB888;
766 break;
767 case 32:
768 gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
769 break;
770 }
771
772 write_reg_dly(gsctrl, GSCTRL);
773 write_reg_dly(0x00000000, GBBASE);
774 write_reg_dly(0x00ffffff, GDRCTRL);
775 write_reg_dly((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
776 write_reg_dly(0x00000000, GPLUT);
777
778 vscadr = readl(VSCADR);
779 vscadr &= ~(FMsk(VSCADR_BLEND_POS) | FMsk(VSCADR_BLEND_M));
780 vscadr |= VSCADR_BLEND_VID | VSCADR_BLEND_NONE;
781 write_reg_dly(vscadr, VSCADR);
782}
783
784static void setup_display(struct fb_info *fbi)
785{
786 unsigned long dsctrl = 0;
787
788 dsctrl = DSCTRL_BLNK_POL;
789 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
790 dsctrl |= DSCTRL_HS_POL;
791 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
792 dsctrl |= DSCTRL_VS_POL;
793 write_reg_dly(dsctrl, DSCTRL);
794 write_reg_dly(0xd0303010, DMCTRL);
795 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
796}
797
798static void enable_controller(struct fb_info *fbi)
799{
800 u32 svctrl, shctrl;
801
802 write_reg_dly(SYSRST_RST, SYSRST);
803
804 /* setup a timeout, raise drive strength */
805 write_reg_dly(0xffffff0c, SYSCFG);
806
807 enable_clocks(fbi);
808 setup_memc(fbi);
809 setup_graphics(fbi);
810 setup_display(fbi);
811
812 shctrl = readl(SHCTRL);
813 shctrl &= ~(FMsk(SHCTRL_HINITIAL));
814 shctrl |= Shctrl_Hinitial(4<<11);
815 writel(shctrl, SHCTRL);
816
817 svctrl = Svctrl_Initial1(1<<10) | Svctrl_Initial2(1<<10);
818 writel(svctrl, SVCTRL);
819
820 writel(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP | SPOCTRL_VORDER_4TAP
821 , SPOCTRL);
822
823 /* Those coefficients are good for scaling up. For scaling
824 * down, the application has to calculate them. */
825 write_reg(0xff000100, VSCOEFF0);
826 write_reg(0xfdfcfdfe, VSCOEFF1);
827 write_reg(0x170d0500, VSCOEFF2);
828 write_reg(0x3d372d22, VSCOEFF3);
829 write_reg(0x00000040, VSCOEFF4);
830
831 write_reg(0xff010100, HSCOEFF0);
832 write_reg(0x00000000, HSCOEFF1);
833 write_reg(0x02010000, HSCOEFF2);
834 write_reg(0x01020302, HSCOEFF3);
835 write_reg(0xf9fbfe00, HSCOEFF4);
836 write_reg(0xfbf7f6f7, HSCOEFF5);
837 write_reg(0x1c110700, HSCOEFF6);
838 write_reg(0x3e393127, HSCOEFF7);
839 write_reg(0x00000040, HSCOEFF8);
840
841}
842
843#ifdef CONFIG_PM
844/*
845 * Power management hooks. Note that we won't be called from IRQ context,
846 * unlike the blank functions above, so we may sleep.
847 */
848static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
849{
850 /* make frame buffer memory enter self-refresh mode */
851 write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR);
852 while (readl(LMPWRSTAT) != LMPWRSTAT_MC_PWR_SRM)
853 ; /* empty statement */
854
855 /* reset the device, since it's initial state is 'mostly sleeping' */
856 write_reg_dly(SYSRST_RST, SYSRST);
857 return 0;
858}
859
860static int mbxfb_resume(struct platform_device *dev)
861{
862 struct fb_info *fbi = platform_get_drvdata(dev);
863
864 enable_clocks(fbi);
865/* setup_graphics(fbi); */
866/* setup_display(fbi); */
867
868 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
869 return 0;
870}
871#else
872#define mbxfb_suspend NULL
873#define mbxfb_resume NULL
874#endif
875
876/* debugfs entries */
877#ifndef CONFIG_FB_MBX_DEBUG
878#define mbxfb_debugfs_init(x) do {} while(0)
879#define mbxfb_debugfs_remove(x) do {} while(0)
880#endif
881
882#define res_size(_r) (((_r)->end - (_r)->start) + 1)
883
884static int mbxfb_probe(struct platform_device *dev)
885{
886 int ret;
887 struct fb_info *fbi;
888 struct mbxfb_info *mfbi;
889 struct mbxfb_platform_data *pdata;
890
891 dev_dbg(&dev->dev, "mbxfb_probe\n");
892
893 pdata = dev_get_platdata(&dev->dev);
894 if (!pdata) {
895 dev_err(&dev->dev, "platform data is required\n");
896 return -EINVAL;
897 }
898
899 fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
900 if (fbi == NULL) {
901 dev_err(&dev->dev, "framebuffer_alloc failed\n");
902 return -ENOMEM;
903 }
904
905 mfbi = fbi->par;
906 fbi->pseudo_palette = mfbi->pseudo_palette;
907
908
909 if (pdata->probe)
910 mfbi->platform_probe = pdata->probe;
911 if (pdata->remove)
912 mfbi->platform_remove = pdata->remove;
913
914 mfbi->fb_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
915 mfbi->reg_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
916
917 if (!mfbi->fb_res || !mfbi->reg_res) {
918 dev_err(&dev->dev, "no resources found\n");
919 ret = -ENODEV;
920 goto err1;
921 }
922
923 mfbi->fb_req = request_mem_region(mfbi->fb_res->start,
924 res_size(mfbi->fb_res), dev->name);
925 if (mfbi->fb_req == NULL) {
926 dev_err(&dev->dev, "failed to claim framebuffer memory\n");
927 ret = -EINVAL;
928 goto err1;
929 }
930 mfbi->fb_phys_addr = mfbi->fb_res->start;
931
932 mfbi->reg_req = request_mem_region(mfbi->reg_res->start,
933 res_size(mfbi->reg_res), dev->name);
934 if (mfbi->reg_req == NULL) {
935 dev_err(&dev->dev, "failed to claim Marathon registers\n");
936 ret = -EINVAL;
937 goto err2;
938 }
939 mfbi->reg_phys_addr = mfbi->reg_res->start;
940
941 mfbi->reg_virt_addr = devm_ioremap_nocache(&dev->dev,
942 mfbi->reg_phys_addr,
943 res_size(mfbi->reg_req));
944 if (!mfbi->reg_virt_addr) {
945 dev_err(&dev->dev, "failed to ioremap Marathon registers\n");
946 ret = -EINVAL;
947 goto err3;
948 }
949 virt_base_2700 = mfbi->reg_virt_addr;
950
951 mfbi->fb_virt_addr = devm_ioremap_nocache(&dev->dev, mfbi->fb_phys_addr,
952 res_size(mfbi->fb_req));
953 if (!mfbi->fb_virt_addr) {
954 dev_err(&dev->dev, "failed to ioremap frame buffer\n");
955 ret = -EINVAL;
956 goto err3;
957 }
958
959 fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000);
960 fbi->screen_size = pdata->memsize;
961 fbi->fbops = &mbxfb_ops;
962
963 fbi->var = mbxfb_default;
964 fbi->fix = mbxfb_fix;
965 fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
966 fbi->fix.smem_len = pdata->memsize;
967 fbi->fix.line_length = mbxfb_default.xres_virtual *
968 mbxfb_default.bits_per_pixel / 8;
969
970 ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
971 if (ret < 0) {
972 dev_err(&dev->dev, "fb_alloc_cmap failed\n");
973 ret = -EINVAL;
974 goto err3;
975 }
976
977 platform_set_drvdata(dev, fbi);
978
979 fb_info(fbi, "mbx frame buffer device\n");
980
981 if (mfbi->platform_probe)
982 mfbi->platform_probe(fbi);
983
984 enable_controller(fbi);
985
986 mbxfb_debugfs_init(fbi);
987
988 ret = register_framebuffer(fbi);
989 if (ret < 0) {
990 dev_err(&dev->dev, "register_framebuffer failed\n");
991 ret = -EINVAL;
992 goto err6;
993 }
994
995 return 0;
996
997err6:
998 fb_dealloc_cmap(&fbi->cmap);
999err3:
1000 release_mem_region(mfbi->reg_res->start, res_size(mfbi->reg_res));
1001err2:
1002 release_mem_region(mfbi->fb_res->start, res_size(mfbi->fb_res));
1003err1:
1004 framebuffer_release(fbi);
1005
1006 return ret;
1007}
1008
1009static int mbxfb_remove(struct platform_device *dev)
1010{
1011 struct fb_info *fbi = platform_get_drvdata(dev);
1012
1013 write_reg_dly(SYSRST_RST, SYSRST);
1014
1015 mbxfb_debugfs_remove(fbi);
1016
1017 if (fbi) {
1018 struct mbxfb_info *mfbi = fbi->par;
1019
1020 unregister_framebuffer(fbi);
1021 if (mfbi) {
1022 if (mfbi->platform_remove)
1023 mfbi->platform_remove(fbi);
1024
1025
1026 if (mfbi->reg_req)
1027 release_mem_region(mfbi->reg_req->start,
1028 res_size(mfbi->reg_req));
1029 if (mfbi->fb_req)
1030 release_mem_region(mfbi->fb_req->start,
1031 res_size(mfbi->fb_req));
1032 }
1033 framebuffer_release(fbi);
1034 }
1035
1036 return 0;
1037}
1038
1039static struct platform_driver mbxfb_driver = {
1040 .probe = mbxfb_probe,
1041 .remove = mbxfb_remove,
1042 .suspend = mbxfb_suspend,
1043 .resume = mbxfb_resume,
1044 .driver = {
1045 .name = "mbx-fb",
1046 },
1047};
1048
1049module_platform_driver(mbxfb_driver);
1050
1051MODULE_DESCRIPTION("loadable framebuffer driver for Marathon device");
1052MODULE_AUTHOR("Mike Rapoport, Compulab");
1053MODULE_LICENSE("GPL");
diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h
deleted file mode 100644
index 5f14b4befd71..000000000000
--- a/drivers/video/mbx/reg_bits.h
+++ /dev/null
@@ -1,613 +0,0 @@
1#ifndef __REG_BITS_2700G_
2#define __REG_BITS_2700G_
3
4/* use defines from asm-arm/arch-pxa/bitfields.h for bit fields access */
5#define UData(Data) ((unsigned long) (Data))
6#define Fld(Size, Shft) (((Size) << 16) + (Shft))
7#define FSize(Field) ((Field) >> 16)
8#define FShft(Field) ((Field) & 0x0000FFFF)
9#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
10#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
11#define F1stBit(Field) (UData (1) << FShft (Field))
12
13#define SYSRST_RST (1 << 0)
14
15/* SYSCLKSRC - SYSCLK Source Control Register */
16#define SYSCLKSRC_SEL Fld(2,0)
17#define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
18#define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
19#define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
20
21/* PIXCLKSRC - PIXCLK Source Control Register */
22#define PIXCLKSRC_SEL Fld(2,0)
23#define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
24#define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
25#define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
26
27/* Clock Disable Register */
28#define CLKSLEEP_SLP (1 << 0)
29
30/* Core PLL Control Register */
31#define CORE_PLL_M Fld(6,7)
32#define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
33#define CORE_PLL_N Fld(3,4)
34#define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
35#define CORE_PLL_P Fld(3,1)
36#define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
37#define CORE_PLL_EN (1 << 0)
38
39/* Display PLL Control Register */
40#define DISP_PLL_M Fld(6,7)
41#define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
42#define DISP_PLL_N Fld(3,4)
43#define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
44#define DISP_PLL_P Fld(3,1)
45#define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
46#define DISP_PLL_EN (1 << 0)
47
48/* PLL status register */
49#define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
50#define PLLSTAT_CORE_PLL_LSTS (1 << 2)
51#define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
52#define PLLSTAT_DISP_PLL_LSTS (1 << 0)
53
54/* Video and scale clock control register */
55#define VOVRCLK_EN (1 << 0)
56
57/* Pixel clock control register */
58#define PIXCLK_EN (1 << 0)
59
60/* Memory clock control register */
61#define MEMCLK_EN (1 << 0)
62
63/* MBX clock control register */
64#define MBXCLK_DIV Fld(2,2)
65#define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
66#define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
67#define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
68#define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
69#define MBXCLK_EN Fld(2,0)
70#define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
71#define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
72#define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
73
74/* M24 clock control register */
75#define M24CLK_DIV Fld(2,1)
76#define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
77#define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
78#define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
79#define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
80#define M24CLK_EN (1 << 0)
81
82/* SDRAM clock control register */
83#define SDCLK_EN (1 << 0)
84
85/* PixClk Divisor Register */
86#define PIXCLKDIV_PD Fld(9,0)
87#define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
88
89/* LCD Config control register */
90#define LCDCFG_IN_FMT Fld(3,28)
91#define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
92#define LCDCFG_LCD1DEN_POL (1 << 27)
93#define LCDCFG_LCD1FCLK_POL (1 << 26)
94#define LCDCFG_LCD1LCLK_POL (1 << 25)
95#define LCDCFG_LCD1D_POL (1 << 24)
96#define LCDCFG_LCD2DEN_POL (1 << 23)
97#define LCDCFG_LCD2FCLK_POL (1 << 22)
98#define LCDCFG_LCD2LCLK_POL (1 << 21)
99#define LCDCFG_LCD2D_POL (1 << 20)
100#define LCDCFG_LCD1_TS (1 << 19)
101#define LCDCFG_LCD1D_DS (1 << 18)
102#define LCDCFG_LCD1C_DS (1 << 17)
103#define LCDCFG_LCD1_IS_IN (1 << 16)
104#define LCDCFG_LCD2_TS (1 << 3)
105#define LCDCFG_LCD2D_DS (1 << 2)
106#define LCDCFG_LCD2C_DS (1 << 1)
107#define LCDCFG_LCD2_IS_IN (1 << 0)
108
109/* On-Die Frame Buffer Power Control Register */
110#define ODFBPWR_SLOW (1 << 2)
111#define ODFBPWR_MODE Fld(2,0)
112#define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
113#define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
114#define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
115#define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
116
117/* On-Die Frame Buffer Power State Status Register */
118#define ODFBSTAT_ACT (1 << 2)
119#define ODFBSTAT_SLP (1 << 1)
120#define ODFBSTAT_SDN (1 << 0)
121
122/* LMRST - Local Memory (SDRAM) Reset */
123#define LMRST_MC_RST (1 << 0)
124
125/* LMCFG - Local Memory (SDRAM) Configuration Register */
126#define LMCFG_LMC_DS (1 << 5)
127#define LMCFG_LMD_DS (1 << 4)
128#define LMCFG_LMA_DS (1 << 3)
129#define LMCFG_LMC_TS (1 << 2)
130#define LMCFG_LMD_TS (1 << 1)
131#define LMCFG_LMA_TS (1 << 0)
132
133/* LMPWR - Local Memory (SDRAM) Power Control Register */
134#define LMPWR_MC_PWR_CNT Fld(2,0)
135#define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
136#define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
137#define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
138
139/* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
140#define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
141#define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
142#define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
143#define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
144
145/* LMTYPE - Local Memory (SDRAM) Type Register */
146#define LMTYPE_CASLAT Fld(3,10)
147#define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
148#define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
149#define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
150#define LMTYPE_BKSZ Fld(2,8)
151#define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
152#define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
153#define LMTYPE_ROWSZ Fld(4,4)
154#define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
155#define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
156#define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
157#define LMTYPE_COLSZ Fld(4,0)
158#define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
159#define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
160#define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
161#define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
162#define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
163#define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
164
165/* LMTIM - Local Memory (SDRAM) Timing Register */
166#define LMTIM_TRAS Fld(4,16)
167#define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
168#define LMTIM_TRP Fld(4,12)
169#define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
170#define LMTIM_TRCD Fld(4,8)
171#define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
172#define LMTIM_TRC Fld(4,4)
173#define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
174#define LMTIM_TDPL Fld(4,0)
175#define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
176
177/* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
178#define LMREFRESH_TREF Fld(2,0)
179#define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
180
181/* GSCTRL - Graphics surface control register */
182#define GSCTRL_LUT_EN (1 << 31)
183#define GSCTRL_GPIXFMT Fld(4,27)
184#define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
185#define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
186#define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
187#define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
188#define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
189#define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
190#define GSCTRL_GAMMA_EN (1 << 26)
191
192#define GSCTRL_GSWIDTH Fld(11,11)
193#define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
194 (((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
195
196#define GSCTRL_GSHEIGHT Fld(11,0)
197#define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
198 (((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
199
200/* GBBASE fileds */
201#define GBBASE_GLALPHA Fld(8,24)
202#define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
203
204#define GBBASE_COLKEY Fld(24,0)
205#define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
206
207/* GDRCTRL fields */
208#define GDRCTRL_PIXDBL (1 << 31)
209#define GDRCTRL_PIXHLV (1 << 30)
210#define GDRCTRL_LNDBL (1 << 29)
211#define GDRCTRL_LNHLV (1 << 28)
212#define GDRCTRL_COLKEYM Fld(24,0)
213#define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
214
215/* GSCADR graphics stream control address register fields */
216#define GSCADR_STR_EN (1 << 31)
217#define GSCADR_COLKEY_EN (1 << 30)
218#define GSCADR_COLKEYSRC (1 << 29)
219#define GSCADR_BLEND_M Fld(2,27)
220#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
221#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
222#define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
223#define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
224#define GSCADR_BLEND_POS Fld(2,24)
225#define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
226#define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
227#define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
228#define GSCADR_GBASE_ADR Fld(23,0)
229#define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
230
231/* GSADR graphics stride address register fields */
232#define GSADR_SRCSTRIDE Fld(10,22)
233#define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
234#define GSADR_XSTART Fld(11,11)
235#define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
236#define GSADR_YSTART Fld(11,0)
237#define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
238
239/* GPLUT graphics palette register fields */
240#define GPLUT_LUTADR Fld(8,24)
241#define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
242#define GPLUT_LUTDATA Fld(24,0)
243#define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
244
245/* VSCTRL - Video Surface Control Register */
246#define VSCTRL_VPIXFMT Fld(4,27)
247#define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
248#define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
249#define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
250#define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
251#define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
252#define VSCTRL_GAMMA_EN (1 << 26)
253#define VSCTRL_CSC_EN (1 << 25)
254#define VSCTRL_COSITED (1 << 22)
255#define VSCTRL_VSWIDTH Fld(11,11)
256#define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
257 (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
258#define VSCTRL_VSHEIGHT Fld(11,0)
259#define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
260 (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
261
262/* VBBASE - Video Blending Base Register */
263#define VBBASE_GLALPHA Fld(8,24)
264#define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
265
266#define VBBASE_COLKEY Fld(24,0)
267#define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
268
269/* VCMSK - Video Color Key Mask Register */
270#define VCMSK_COLKEY_M Fld(24,0)
271#define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
272
273/* VSCADR - Video Stream Control Rddress Register */
274#define VSCADR_STR_EN (1 << 31)
275#define VSCADR_COLKEY_EN (1 << 30)
276#define VSCADR_COLKEYSRC (1 << 29)
277#define VSCADR_BLEND_M Fld(2,27)
278#define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
279#define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
280#define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
281#define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
282#define VSCADR_BLEND_POS Fld(2,24)
283#define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
284#define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
285#define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
286#define VSCADR_VBASE_ADR Fld(23,0)
287#define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
288
289/* VUBASE - Video U Base Register */
290#define VUBASE_UVHALFSTR (1 << 31)
291#define VUBASE_UBASE_ADR Fld(24,0)
292#define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
293
294/* VVBASE - Video V Base Register */
295#define VVBASE_VBASE_ADR Fld(24,0)
296#define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
297
298/* VSADR - Video Stride Address Register */
299#define VSADR_SRCSTRIDE Fld(10,22)
300#define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
301#define VSADR_XSTART Fld(11,11)
302#define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
303#define VSADR_YSTART Fld(11,0)
304#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
305
306/* VSCTRL - Video Surface Control Register */
307#define VSCTRL_VPIXFMT Fld(4,27)
308#define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
309#define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
310#define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
311#define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
312#define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
313#define VSCTRL_GAMMA_EN (1 << 26)
314#define VSCTRL_CSC_EN (1 << 25)
315#define VSCTRL_COSITED (1 << 22)
316#define VSCTRL_VSWIDTH Fld(11,11)
317#define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
318 (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
319#define VSCTRL_VSHEIGHT Fld(11,0)
320#define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
321 (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
322
323/* VBBASE - Video Blending Base Register */
324#define VBBASE_GLALPHA Fld(8,24)
325#define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
326
327#define VBBASE_COLKEY Fld(24,0)
328#define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
329
330/* VCMSK - Video Color Key Mask Register */
331#define VCMSK_COLKEY_M Fld(24,0)
332#define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
333
334/* VSCADR - Video Stream Control Rddress Register */
335#define VSCADR_STR_EN (1 << 31)
336#define VSCADR_COLKEY_EN (1 << 30)
337#define VSCADR_COLKEYSRC (1 << 29)
338#define VSCADR_BLEND_M Fld(2,27)
339#define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
340#define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
341#define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
342#define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
343#define VSCADR_BLEND_POS Fld(2,24)
344#define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
345#define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
346#define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
347#define VSCADR_VBASE_ADR Fld(23,0)
348#define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
349
350/* VUBASE - Video U Base Register */
351#define VUBASE_UVHALFSTR (1 << 31)
352#define VUBASE_UBASE_ADR Fld(24,0)
353#define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
354
355/* VVBASE - Video V Base Register */
356#define VVBASE_VBASE_ADR Fld(24,0)
357#define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
358
359/* VSADR - Video Stride Address Register */
360#define VSADR_SRCSTRIDE Fld(10,22)
361#define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
362#define VSADR_XSTART Fld(11,11)
363#define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
364#define VSADR_YSTART Fld(11,0)
365#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
366
367/* HCCTRL - Hardware Cursor Register fields */
368#define HCCTRL_CUR_EN (1 << 31)
369#define HCCTRL_COLKEY_EN (1 << 29)
370#define HCCTRL_COLKEYSRC (1 << 28)
371#define HCCTRL_BLEND_M Fld(2,26)
372#define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
373#define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
374#define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
375#define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
376#define HCCTRL_CPIXFMT Fld(3,23)
377#define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
378#define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
379#define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
380#define HCCTRL_CBASE_ADR Fld(23,0)
381#define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
382
383/* HCSIZE Hardware Cursor Size Register fields */
384#define HCSIZE_BLEND_POS Fld(2,29)
385#define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
386#define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
387#define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
388#define HCSIZE_CWIDTH Fld(3,16)
389#define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
390#define HCSIZE_CHEIGHT Fld(3,0)
391#define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
392
393/* HCPOS Hardware Cursor Position Register fields */
394#define HCPOS_SWITCHSRC (1 << 30)
395#define HCPOS_CURBLINK Fld(6,24)
396#define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
397#define HCPOS_XSTART Fld(12,12)
398#define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
399#define HCPOS_YSTART Fld(12,0)
400#define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
401
402/* HCBADR Hardware Cursor Blend Address Register */
403#define HCBADR_GLALPHA Fld(8,24)
404#define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
405#define HCBADR_COLKEY Fld(24,0)
406#define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
407
408/* HCCKMSK - Hardware Cursor Color Key Mask Register */
409#define HCCKMSK_COLKEY_M Fld(24,0)
410#define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
411
412/* DSCTRL - Display sync control register */
413#define DSCTRL_SYNCGEN_EN (1 << 31)
414#define DSCTRL_DPL_RST (1 << 29)
415#define DSCTRL_PWRDN_M (1 << 28)
416#define DSCTRL_UPDSYNCCNT (1 << 26)
417#define DSCTRL_UPDINTCNT (1 << 25)
418#define DSCTRL_UPDCNT (1 << 24)
419#define DSCTRL_UPDWAIT Fld(4,16)
420#define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
421#define DSCTRL_CLKPOL (1 << 11)
422#define DSCTRL_CSYNC_EN (1 << 10)
423#define DSCTRL_VS_SLAVE (1 << 7)
424#define DSCTRL_HS_SLAVE (1 << 6)
425#define DSCTRL_BLNK_POL (1 << 5)
426#define DSCTRL_BLNK_DIS (1 << 4)
427#define DSCTRL_VS_POL (1 << 3)
428#define DSCTRL_VS_DIS (1 << 2)
429#define DSCTRL_HS_POL (1 << 1)
430#define DSCTRL_HS_DIS (1 << 0)
431
432/* DHT01 - Display horizontal timing register 01 */
433#define DHT01_HBPS Fld(12,16)
434#define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
435#define DHT01_HT Fld(12,0)
436#define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
437
438/* DHT02 - Display horizontal timing register 02 */
439#define DHT02_HAS Fld(12,16)
440#define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
441#define DHT02_HLBS Fld(12,0)
442#define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
443
444/* DHT03 - Display horizontal timing register 03 */
445#define DHT03_HFPS Fld(12,16)
446#define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
447#define DHT03_HRBS Fld(12,0)
448#define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
449
450/* DVT01 - Display vertical timing register 01 */
451#define DVT01_VBPS Fld(12,16)
452#define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
453#define DVT01_VT Fld(12,0)
454#define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
455
456/* DVT02 - Display vertical timing register 02 */
457#define DVT02_VAS Fld(12,16)
458#define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
459#define DVT02_VTBS Fld(12,0)
460#define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
461
462/* DVT03 - Display vertical timing register 03 */
463#define DVT03_VFPS Fld(12,16)
464#define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
465#define DVT03_VBBS Fld(12,0)
466#define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
467
468/* DVECTRL - display vertical event control register */
469#define DVECTRL_VEVENT Fld(12,16)
470#define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
471#define DVECTRL_VFETCH Fld(12,0)
472#define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
473
474/* DHDET - display horizontal DE timing register */
475#define DHDET_HDES Fld(12,16)
476#define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
477#define DHDET_HDEF Fld(12,0)
478#define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
479
480/* DVDET - display vertical DE timing register */
481#define DVDET_VDES Fld(12,16)
482#define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
483#define DVDET_VDEF Fld(12,0)
484#define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
485
486/* DODMSK - display output data mask register */
487#define DODMSK_MASK_LVL (1 << 31)
488#define DODMSK_BLNK_LVL (1 << 30)
489#define DODMSK_MASK_B Fld(8,16)
490#define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
491#define DODMSK_MASK_G Fld(8,8)
492#define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
493#define DODMSK_MASK_R Fld(8,0)
494#define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
495
496/* DBCOL - display border color control register */
497#define DBCOL_BORDCOL Fld(24,0)
498#define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
499
500/* DVLNUM - display vertical line number register */
501#define DVLNUM_VLINE Fld(12,0)
502#define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
503
504/* DMCTRL - Display Memory Control Register */
505#define DMCTRL_MEM_REF Fld(2,30)
506#define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
507#define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
508#define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
509#define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
510#define DMCTRL_UV_THRHLD Fld(6,24)
511#define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
512#define DMCTRL_V_THRHLD Fld(7,16)
513#define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
514#define DMCTRL_D_THRHLD Fld(7,8)
515#define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
516#define DMCTRL_BURSTLEN Fld(6,0)
517#define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
518
519/* DINTRS - Display Interrupt Status Register */
520#define DINTRS_CUR_OR_S (1 << 18)
521#define DINTRS_STR2_OR_S (1 << 17)
522#define DINTRS_STR1_OR_S (1 << 16)
523#define DINTRS_CUR_UR_S (1 << 6)
524#define DINTRS_STR2_UR_S (1 << 5)
525#define DINTRS_STR1_UR_S (1 << 4)
526#define DINTRS_VEVENT1_S (1 << 3)
527#define DINTRS_VEVENT0_S (1 << 2)
528#define DINTRS_HBLNK1_S (1 << 1)
529#define DINTRS_HBLNK0_S (1 << 0)
530
531/* DINTRE - Display Interrupt Enable Register */
532#define DINTRE_CUR_OR_EN (1 << 18)
533#define DINTRE_STR2_OR_EN (1 << 17)
534#define DINTRE_STR1_OR_EN (1 << 16)
535#define DINTRE_CUR_UR_EN (1 << 6)
536#define DINTRE_STR2_UR_EN (1 << 5)
537#define DINTRE_STR1_UR_EN (1 << 4)
538#define DINTRE_VEVENT1_EN (1 << 3)
539#define DINTRE_VEVENT0_EN (1 << 2)
540#define DINTRE_HBLNK1_EN (1 << 1)
541#define DINTRE_HBLNK0_EN (1 << 0)
542
543/* DINTRS - Display Interrupt Status Register */
544#define DINTRS_CUR_OR_S (1 << 18)
545#define DINTRS_STR2_OR_S (1 << 17)
546#define DINTRS_STR1_OR_S (1 << 16)
547#define DINTRS_CUR_UR_S (1 << 6)
548#define DINTRS_STR2_UR_S (1 << 5)
549#define DINTRS_STR1_UR_S (1 << 4)
550#define DINTRS_VEVENT1_S (1 << 3)
551#define DINTRS_VEVENT0_S (1 << 2)
552#define DINTRS_HBLNK1_S (1 << 1)
553#define DINTRS_HBLNK0_S (1 << 0)
554
555/* DINTRE - Display Interrupt Enable Register */
556#define DINTRE_CUR_OR_EN (1 << 18)
557#define DINTRE_STR2_OR_EN (1 << 17)
558#define DINTRE_STR1_OR_EN (1 << 16)
559#define DINTRE_CUR_UR_EN (1 << 6)
560#define DINTRE_STR2_UR_EN (1 << 5)
561#define DINTRE_STR1_UR_EN (1 << 4)
562#define DINTRE_VEVENT1_EN (1 << 3)
563#define DINTRE_VEVENT0_EN (1 << 2)
564#define DINTRE_HBLNK1_EN (1 << 1)
565#define DINTRE_HBLNK0_EN (1 << 0)
566
567
568/* DLSTS - display load status register */
569#define DLSTS_RLD_ADONE (1 << 23)
570/* #define DLSTS_RLD_ADOUT Fld(23,0) */
571
572/* DLLCTRL - display list load control register */
573#define DLLCTRL_RLD_ADRLN Fld(8,24)
574#define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
575
576/* CLIPCTRL - Clipping Control Register */
577#define CLIPCTRL_HSKIP Fld(11,16)
578#define Clipctrl_Hskip ((x) << FShft(CLIPCTRL_HSKIP))
579#define CLIPCTRL_VSKIP Fld(11,0)
580#define Clipctrl_Vskip ((x) << FShft(CLIPCTRL_VSKIP))
581
582/* SPOCTRL - Scale Pitch/Order Control Register */
583#define SPOCTRL_H_SC_BP (1 << 31)
584#define SPOCTRL_V_SC_BP (1 << 30)
585#define SPOCTRL_HV_SC_OR (1 << 29)
586#define SPOCTRL_VS_UR_C (1 << 27)
587#define SPOCTRL_VORDER Fld(2,16)
588#define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
589#define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
590#define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
591#define SPOCTRL_VPITCH Fld(16,0)
592#define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
593
594/* SVCTRL - Scale Vertical Control Register */
595#define SVCTRL_INITIAL1 Fld(16,16)
596#define Svctrl_Initial1(x) ((x) << FShft(SVCTRL_INITIAL1))
597#define SVCTRL_INITIAL2 Fld(16,0)
598#define Svctrl_Initial2(x) ((x) << FShft(SVCTRL_INITIAL2))
599
600/* SHCTRL - Scale Horizontal Control Register */
601#define SHCTRL_HINITIAL Fld(16,16)
602#define Shctrl_Hinitial(x) ((x) << FShft(SHCTRL_HINITIAL))
603#define SHCTRL_HDECIM (1 << 15)
604#define SHCTRL_HPITCH Fld(15,0)
605#define Shctrl_Hpitch(x) ((x) << FShft(SHCTRL_HPITCH))
606
607/* SSSIZE - Scale Surface Size Register */
608#define SSSIZE_SC_WIDTH Fld(11,16)
609#define Sssize_Sc_Width(x) ((x) << FShft(SSSIZE_SC_WIDTH))
610#define SSSIZE_SC_HEIGHT Fld(11,0)
611#define Sssize_Sc_Height(x) ((x) << FShft(SSSIZE_SC_HEIGHT))
612
613#endif /* __REG_BITS_2700G_ */
diff --git a/drivers/video/mbx/regs.h b/drivers/video/mbx/regs.h
deleted file mode 100644
index 063099d48839..000000000000
--- a/drivers/video/mbx/regs.h
+++ /dev/null
@@ -1,195 +0,0 @@
1#ifndef __REGS_2700G_
2#define __REGS_2700G_
3
4/* extern unsigned long virt_base_2700; */
5/* #define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700)) */
6#define __REG_2700G(x) ((x)+virt_base_2700)
7
8/* System Configuration Registers (0x0000_0000 0x0000_0010) */
9#define SYSCFG __REG_2700G(0x00000000)
10#define PFBASE __REG_2700G(0x00000004)
11#define PFCEIL __REG_2700G(0x00000008)
12#define POLLFLAG __REG_2700G(0x0000000c)
13#define SYSRST __REG_2700G(0x00000010)
14
15/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
16#define NINTPW __REG_2700G(0x00000014)
17#define MINTENABLE __REG_2700G(0x00000018)
18#define MINTSTAT __REG_2700G(0x0000001c)
19#define SINTENABLE __REG_2700G(0x00000020)
20#define SINTSTAT __REG_2700G(0x00000024)
21#define SINTCLR __REG_2700G(0x00000028)
22
23/* Clock Control Registers (0x0000_002C 0x0000_005F) */
24#define SYSCLKSRC __REG_2700G(0x0000002c)
25#define PIXCLKSRC __REG_2700G(0x00000030)
26#define CLKSLEEP __REG_2700G(0x00000034)
27#define COREPLL __REG_2700G(0x00000038)
28#define DISPPLL __REG_2700G(0x0000003c)
29#define PLLSTAT __REG_2700G(0x00000040)
30#define VOVRCLK __REG_2700G(0x00000044)
31#define PIXCLK __REG_2700G(0x00000048)
32#define MEMCLK __REG_2700G(0x0000004c)
33#define M24CLK __REG_2700G(0x00000050)
34#define MBXCLK __REG_2700G(0x00000054)
35#define SDCLK __REG_2700G(0x00000058)
36#define PIXCLKDIV __REG_2700G(0x0000005c)
37
38/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
39#define LCD_CONFIG __REG_2700G(0x00000060)
40
41/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
42#define ODFBPWR __REG_2700G(0x00000064)
43#define ODFBSTAT __REG_2700G(0x00000068)
44
45/* GPIO Registers (0x0000_006C 0x0000_007F) */
46#define GPIOCGF __REG_2700G(0x0000006c)
47#define GPIOHI __REG_2700G(0x00000070)
48#define GPIOLO __REG_2700G(0x00000074)
49#define GPIOSTAT __REG_2700G(0x00000078)
50
51/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
52#define PWMRST __REG_2700G(0x00000200)
53#define PWMCFG __REG_2700G(0x00000204)
54#define PWM0DIV __REG_2700G(0x00000210)
55#define PWM0DUTY __REG_2700G(0x00000214)
56#define PWM0PER __REG_2700G(0x00000218)
57#define PWM1DIV __REG_2700G(0x00000220)
58#define PWM1DUTY __REG_2700G(0x00000224)
59#define PWM1PER __REG_2700G(0x00000228)
60
61/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
62#define ID __REG_2700G(0x00000FF0)
63
64/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
65#define LMRST __REG_2700G(0x00001000)
66#define LMCFG __REG_2700G(0x00001004)
67#define LMPWR __REG_2700G(0x00001008)
68#define LMPWRSTAT __REG_2700G(0x0000100c)
69#define LMCEMR __REG_2700G(0x00001010)
70#define LMTYPE __REG_2700G(0x00001014)
71#define LMTIM __REG_2700G(0x00001018)
72#define LMREFRESH __REG_2700G(0x0000101c)
73#define LMPROTMIN __REG_2700G(0x00001020)
74#define LMPROTMAX __REG_2700G(0x00001024)
75#define LMPROTCFG __REG_2700G(0x00001028)
76#define LMPROTERR __REG_2700G(0x0000102c)
77
78/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
79#define GSCTRL __REG_2700G(0x00002000)
80#define VSCTRL __REG_2700G(0x00002004)
81#define GBBASE __REG_2700G(0x00002020)
82#define VBBASE __REG_2700G(0x00002024)
83#define GDRCTRL __REG_2700G(0x00002040)
84#define VCMSK __REG_2700G(0x00002044)
85#define GSCADR __REG_2700G(0x00002060)
86#define VSCADR __REG_2700G(0x00002064)
87#define VUBASE __REG_2700G(0x00002084)
88#define VVBASE __REG_2700G(0x000020a4)
89#define GSADR __REG_2700G(0x000020c0)
90#define VSADR __REG_2700G(0x000020c4)
91#define HCCTRL __REG_2700G(0x00002100)
92#define HCSIZE __REG_2700G(0x00002110)
93#define HCPOS __REG_2700G(0x00002120)
94#define HCBADR __REG_2700G(0x00002130)
95#define HCCKMSK __REG_2700G(0x00002140)
96#define GPLUT __REG_2700G(0x00002150)
97#define DSCTRL __REG_2700G(0x00002154)
98#define DHT01 __REG_2700G(0x00002158)
99#define DHT02 __REG_2700G(0x0000215c)
100#define DHT03 __REG_2700G(0x00002160)
101#define DVT01 __REG_2700G(0x00002164)
102#define DVT02 __REG_2700G(0x00002168)
103#define DVT03 __REG_2700G(0x0000216c)
104#define DBCOL __REG_2700G(0x00002170)
105#define BGCOLOR __REG_2700G(0x00002174)
106#define DINTRS __REG_2700G(0x00002178)
107#define DINTRE __REG_2700G(0x0000217c)
108#define DINTRCNT __REG_2700G(0x00002180)
109#define DSIG __REG_2700G(0x00002184)
110#define DMCTRL __REG_2700G(0x00002188)
111#define CLIPCTRL __REG_2700G(0x0000218c)
112#define SPOCTRL __REG_2700G(0x00002190)
113#define SVCTRL __REG_2700G(0x00002194)
114
115/* 0x0000_2198 */
116/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
117#define VSCOEFF0 __REG_2700G(0x00002198)
118#define VSCOEFF1 __REG_2700G(0x0000219c)
119#define VSCOEFF2 __REG_2700G(0x000021a0)
120#define VSCOEFF3 __REG_2700G(0x000021a4)
121#define VSCOEFF4 __REG_2700G(0x000021a8)
122
123#define SHCTRL __REG_2700G(0x000021b0)
124
125/* 0x0000_21B4 */
126/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
127#define HSCOEFF0 __REG_2700G(0x000021b4)
128#define HSCOEFF1 __REG_2700G(0x000021b8)
129#define HSCOEFF2 __REG_2700G(0x000021bc)
130#define HSCOEFF3 __REG_2700G(0x000021c0)
131#define HSCOEFF4 __REG_2700G(0x000021c4)
132#define HSCOEFF5 __REG_2700G(0x000021c8)
133#define HSCOEFF6 __REG_2700G(0x000021cc)
134#define HSCOEFF7 __REG_2700G(0x000021d0)
135#define HSCOEFF8 __REG_2700G(0x000021d4)
136
137#define SSSIZE __REG_2700G(0x000021D8)
138
139/* 0x0000_2200 */
140/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
141#define VIDGAM0 __REG_2700G(0x00002200)
142#define VIDGAM1 __REG_2700G(0x00002204)
143#define VIDGAM2 __REG_2700G(0x00002208)
144#define VIDGAM3 __REG_2700G(0x0000220c)
145#define VIDGAM4 __REG_2700G(0x00002210)
146#define VIDGAM5 __REG_2700G(0x00002214)
147#define VIDGAM6 __REG_2700G(0x00002218)
148#define VIDGAM7 __REG_2700G(0x0000221c)
149#define VIDGAM8 __REG_2700G(0x00002220)
150#define VIDGAM9 __REG_2700G(0x00002224)
151#define VIDGAM10 __REG_2700G(0x00002228)
152#define VIDGAM11 __REG_2700G(0x0000222c)
153#define VIDGAM12 __REG_2700G(0x00002230)
154#define VIDGAM13 __REG_2700G(0x00002234)
155#define VIDGAM14 __REG_2700G(0x00002238)
156#define VIDGAM15 __REG_2700G(0x0000223c)
157#define VIDGAM16 __REG_2700G(0x00002240)
158
159/* 0x0000_2250 */
160/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
161#define GFXGAM0 __REG_2700G(0x00002250)
162#define GFXGAM1 __REG_2700G(0x00002254)
163#define GFXGAM2 __REG_2700G(0x00002258)
164#define GFXGAM3 __REG_2700G(0x0000225c)
165#define GFXGAM4 __REG_2700G(0x00002260)
166#define GFXGAM5 __REG_2700G(0x00002264)
167#define GFXGAM6 __REG_2700G(0x00002268)
168#define GFXGAM7 __REG_2700G(0x0000226c)
169#define GFXGAM8 __REG_2700G(0x00002270)
170#define GFXGAM9 __REG_2700G(0x00002274)
171#define GFXGAM10 __REG_2700G(0x00002278)
172#define GFXGAM11 __REG_2700G(0x0000227c)
173#define GFXGAM12 __REG_2700G(0x00002280)
174#define GFXGAM13 __REG_2700G(0x00002284)
175#define GFXGAM14 __REG_2700G(0x00002288)
176#define GFXGAM15 __REG_2700G(0x0000228c)
177#define GFXGAM16 __REG_2700G(0x00002290)
178
179#define DLSTS __REG_2700G(0x00002300)
180#define DLLCTRL __REG_2700G(0x00002304)
181#define DVLNUM __REG_2700G(0x00002308)
182#define DUCTRL __REG_2700G(0x0000230c)
183#define DVECTRL __REG_2700G(0x00002310)
184#define DHDET __REG_2700G(0x00002314)
185#define DVDET __REG_2700G(0x00002318)
186#define DODMSK __REG_2700G(0x0000231c)
187#define CSC01 __REG_2700G(0x00002330)
188#define CSC02 __REG_2700G(0x00002334)
189#define CSC03 __REG_2700G(0x00002338)
190#define CSC04 __REG_2700G(0x0000233c)
191#define CSC05 __REG_2700G(0x00002340)
192
193#define FB_MEMORY_START __REG_2700G(0x00060000)
194
195#endif /* __REGS_2700G_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 21:56:47 -0500