diff options
author | Raphael Assenat <raph@8d.com> | 2006-12-08 05:40:34 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-08 11:29:06 -0500 |
commit | fb137d5b7f2301f2717944322bba38039083c431 (patch) | |
tree | c1de4903e2da21f6e42f0e8d691be348b8db1108 /drivers/video/mbx/reg_bits.h | |
parent | ce7405fb380c097511d0a3d20db25bc167f3c5dc (diff) |
[PATCH] mbxfb: Add more registers bits access macros
This patch adds register bits access macros for chip's Video Plane, Scaling
and interrupt registers.
Signed-off-by: Raphael Assenat <raph@8d.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Acked-by: James Simmons <jsimmons@infradead.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/video/mbx/reg_bits.h')
-rw-r--r-- | drivers/video/mbx/reg_bits.h | 114 |
1 files changed, 112 insertions, 2 deletions
diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h index c226a8e45312..9a24fb0c7d48 100644 --- a/drivers/video/mbx/reg_bits.h +++ b/drivers/video/mbx/reg_bits.h | |||
@@ -242,6 +242,67 @@ | |||
242 | #define GPLUT_LUTDATA Fld(24,0) | 242 | #define GPLUT_LUTDATA Fld(24,0) |
243 | #define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA)) | 243 | #define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA)) |
244 | 244 | ||
245 | /* VSCTRL - Video Surface Control Register */ | ||
246 | #define VSCTRL_VPIXFMT Fld(4,27) | ||
247 | #define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT)) | ||
248 | #define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT)) | ||
249 | #define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT)) | ||
250 | #define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT)) | ||
251 | #define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT)) | ||
252 | #define VSCTRL_GAMMA_EN (1 << 26) | ||
253 | #define VSCTRL_CSC_EN (1 << 25) | ||
254 | #define VSCTRL_COSITED (1 << 22) | ||
255 | #define VSCTRL_VSWIDTH Fld(11,11) | ||
256 | #define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \ | ||
257 | (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH)) | ||
258 | #define VSCTRL_VSHEIGHT Fld(11,0) | ||
259 | #define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \ | ||
260 | (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT)) | ||
261 | |||
262 | /* VBBASE - Video Blending Base Register */ | ||
263 | #define VBBASE_GLALPHA Fld(8,24) | ||
264 | #define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA)) | ||
265 | |||
266 | #define VBBASE_COLKEY Fld(24,0) | ||
267 | #define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY)) | ||
268 | |||
269 | /* VCMSK - Video Color Key Mask Register */ | ||
270 | #define VCMSK_COLKEY_M Fld(24,0) | ||
271 | #define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M)) | ||
272 | |||
273 | /* VSCADR - Video Stream Control Rddress Register */ | ||
274 | #define VSCADR_STR_EN (1 << 31) | ||
275 | #define VSCADR_COLKEY_EN (1 << 30) | ||
276 | #define VSCADR_COLKEYSRC (1 << 29) | ||
277 | #define VSCADR_BLEND_M Fld(2,27) | ||
278 | #define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M)) | ||
279 | #define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M)) | ||
280 | #define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M)) | ||
281 | #define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M)) | ||
282 | #define VSCADR_BLEND_POS Fld(2,24) | ||
283 | #define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS)) | ||
284 | #define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS)) | ||
285 | #define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS)) | ||
286 | #define VSCADR_VBASE_ADR Fld(23,0) | ||
287 | #define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR)) | ||
288 | |||
289 | /* VUBASE - Video U Base Register */ | ||
290 | #define VUBASE_UVHALFSTR (1 << 31) | ||
291 | #define VUBASE_UBASE_ADR Fld(24,0) | ||
292 | #define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR)) | ||
293 | |||
294 | /* VVBASE - Video V Base Register */ | ||
295 | #define VVBASE_VBASE_ADR Fld(24,0) | ||
296 | #define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR)) | ||
297 | |||
298 | /* VSADR - Video Stride Address Register */ | ||
299 | #define VSADR_SRCSTRIDE Fld(10,22) | ||
300 | #define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE)) | ||
301 | #define VSADR_XSTART Fld(11,11) | ||
302 | #define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART)) | ||
303 | #define VSADR_YSTART Fld(11,0) | ||
304 | #define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART)) | ||
305 | |||
245 | /* HCCTRL - Hardware Cursor Register fields */ | 306 | /* HCCTRL - Hardware Cursor Register fields */ |
246 | #define HCCTRL_CUR_EN (1 << 31) | 307 | #define HCCTRL_CUR_EN (1 << 31) |
247 | #define HCCTRL_COLKEY_EN (1 << 29) | 308 | #define HCCTRL_COLKEY_EN (1 << 29) |
@@ -394,6 +455,30 @@ | |||
394 | #define DMCTRL_BURSTLEN Fld(6,0) | 455 | #define DMCTRL_BURSTLEN Fld(6,0) |
395 | #define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN)) | 456 | #define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN)) |
396 | 457 | ||
458 | /* DINTRS - Display Interrupt Status Register */ | ||
459 | #define DINTRS_CUR_OR_S (1 << 18) | ||
460 | #define DINTRS_STR2_OR_S (1 << 17) | ||
461 | #define DINTRS_STR1_OR_S (1 << 16) | ||
462 | #define DINTRS_CUR_UR_S (1 << 6) | ||
463 | #define DINTRS_STR2_UR_S (1 << 5) | ||
464 | #define DINTRS_STR1_UR_S (1 << 4) | ||
465 | #define DINTRS_VEVENT1_S (1 << 3) | ||
466 | #define DINTRS_VEVENT0_S (1 << 2) | ||
467 | #define DINTRS_HBLNK1_S (1 << 1) | ||
468 | #define DINTRS_HBLNK0_S (1 << 0) | ||
469 | |||
470 | /* DINTRE - Display Interrupt Enable Register */ | ||
471 | #define DINTRE_CUR_OR_EN (1 << 18) | ||
472 | #define DINTRE_STR2_OR_EN (1 << 17) | ||
473 | #define DINTRE_STR1_OR_EN (1 << 16) | ||
474 | #define DINTRE_CUR_UR_EN (1 << 6) | ||
475 | #define DINTRE_STR2_UR_EN (1 << 5) | ||
476 | #define DINTRE_STR1_UR_EN (1 << 4) | ||
477 | #define DINTRE_VEVENT1_EN (1 << 3) | ||
478 | #define DINTRE_VEVENT0_EN (1 << 2) | ||
479 | #define DINTRE_HBLNK1_EN (1 << 1) | ||
480 | #define DINTRE_HBLNK0_EN (1 << 0) | ||
481 | |||
397 | 482 | ||
398 | /* DLSTS - display load status register */ | 483 | /* DLSTS - display load status register */ |
399 | #define DLSTS_RLD_ADONE (1 << 23) | 484 | #define DLSTS_RLD_ADONE (1 << 23) |
@@ -403,16 +488,41 @@ | |||
403 | #define DLLCTRL_RLD_ADRLN Fld(8,24) | 488 | #define DLLCTRL_RLD_ADRLN Fld(8,24) |
404 | #define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN)) | 489 | #define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN)) |
405 | 490 | ||
491 | /* CLIPCTRL - Clipping Control Register */ | ||
492 | #define CLIPCTRL_HSKIP Fld(11,16) | ||
493 | #define Clipctrl_Hskip ((x) << FShft(CLIPCTRL_HSKIP)) | ||
494 | #define CLIPCTRL_VSKIP Fld(11,0) | ||
495 | #define Clipctrl_Vskip ((x) << FShft(CLIPCTRL_VSKIP)) | ||
496 | |||
406 | /* SPOCTRL - Scale Pitch/Order Control Register */ | 497 | /* SPOCTRL - Scale Pitch/Order Control Register */ |
407 | #define SPOCTRL_H_SC_BP (1 << 31) | 498 | #define SPOCTRL_H_SC_BP (1 << 31) |
408 | #define SPOCTRL_V_SC_BP (1 << 30) | 499 | #define SPOCTRL_V_SC_BP (1 << 30) |
409 | #define SPOCTRL_HV_SC_OR (1 << 29) | 500 | #define SPOCTRL_HV_SC_OR (1 << 29) |
410 | #define SPOCTRL_VS_UR_C (1 << 27) | 501 | #define SPOCTRL_VS_UR_C (1 << 27) |
411 | #define SPOCTRL_VORDER Fld(2,16) | 502 | #define SPOCTRL_VORDER Fld(2,16) |
412 | #define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER)) | 503 | #define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER)) |
413 | #define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER)) | 504 | #define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER)) |
414 | #define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER)) | 505 | #define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER)) |
415 | #define SPOCTRL_VPITCH Fld(16,0) | 506 | #define SPOCTRL_VPITCH Fld(16,0) |
416 | #define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH)) | 507 | #define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH)) |
417 | 508 | ||
509 | /* SVCTRL - Scale Vertical Control Register */ | ||
510 | #define SVCTRL_INITIAL1 Fld(16,16) | ||
511 | #define Svctrl_Initial1(x) ((x) << FShft(SVCTRL_INITIAL1)) | ||
512 | #define SVCTRL_INITIAL2 Fld(16,0) | ||
513 | #define Svctrl_Initial2(x) ((x) << FShft(SVCTRL_INITIAL2)) | ||
514 | |||
515 | /* SHCTRL - Scale Horizontal Control Register */ | ||
516 | #define SHCTRL_HINITIAL Fld(16,16) | ||
517 | #define Shctrl_Hinitial(x) ((x) << FShft(SHCTRL_HINITIAL)) | ||
518 | #define SHCTRL_HDECIM (1 << 15) | ||
519 | #define SHCTRL_HPITCH Fld(15,0) | ||
520 | #define Shctrl_Hpitch(x) ((x) << FShft(SHCTRL_HPITCH)) | ||
521 | |||
522 | /* SSSIZE - Scale Surface Size Register */ | ||
523 | #define SSSIZE_SC_WIDTH Fld(11,16) | ||
524 | #define Sssize_Sc_Width(x) ((x) << FShft(SSSIZE_SC_WIDTH)) | ||
525 | #define SSSIZE_SC_HEIGHT Fld(11,0) | ||
526 | #define Sssize_Sc_Height(x) ((x) << FShft(SSSIZE_SC_HEIGHT)) | ||
527 | |||
418 | #endif /* __REG_BITS_2700G_ */ | 528 | #endif /* __REG_BITS_2700G_ */ |