diff options
author | Raphael Assenat <raph@8d.com> | 2007-10-16 04:28:40 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-16 12:43:14 -0400 |
commit | ba282daa919f89c871780f344a71e5403a70b634 (patch) | |
tree | bbe7422999670f7c9fcc07b924963f9cd450840e /drivers/video/mbx/reg_bits.h | |
parent | eb78f9b3fa8532057d2a45acbe415b27ece6341b (diff) |
mbxfb: Improvements and new features
This contains the following changes:
* Overlay surface alpha is configured separately from the overlay. This
prevents display glitches (configure and fill the overlay first, set
alpha to a visible value next)
* Added an ioctl for configuring transparency of the Overlay and graphics
planes. Blend mode, colorkey mode and global alpha mode are supported.
* Added an ioctl for setting the plane order. The overlay plance can be placed
over or
under the graphics plane.
* Added an ioctl for setting and reading chip registers, with mask.
* Updated copyright for 2007
[adaplas]
* Coding style changes
Signed-off-by: Raphael Assenat <raph@8d.com>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/mbx/reg_bits.h')
-rw-r--r-- | drivers/video/mbx/reg_bits.h | 87 |
1 files changed, 86 insertions, 1 deletions
diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h index 9a24fb0c7d48..5f14b4befd71 100644 --- a/drivers/video/mbx/reg_bits.h +++ b/drivers/video/mbx/reg_bits.h | |||
@@ -215,7 +215,7 @@ | |||
215 | /* GSCADR graphics stream control address register fields */ | 215 | /* GSCADR graphics stream control address register fields */ |
216 | #define GSCADR_STR_EN (1 << 31) | 216 | #define GSCADR_STR_EN (1 << 31) |
217 | #define GSCADR_COLKEY_EN (1 << 30) | 217 | #define GSCADR_COLKEY_EN (1 << 30) |
218 | #define GSCADR_COLKEYSCR (1 << 29) | 218 | #define GSCADR_COLKEYSRC (1 << 29) |
219 | #define GSCADR_BLEND_M Fld(2,27) | 219 | #define GSCADR_BLEND_M Fld(2,27) |
220 | #define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M)) | 220 | #define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M)) |
221 | #define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M)) | 221 | #define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M)) |
@@ -303,6 +303,67 @@ | |||
303 | #define VSADR_YSTART Fld(11,0) | 303 | #define VSADR_YSTART Fld(11,0) |
304 | #define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART)) | 304 | #define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART)) |
305 | 305 | ||
306 | /* VSCTRL - Video Surface Control Register */ | ||
307 | #define VSCTRL_VPIXFMT Fld(4,27) | ||
308 | #define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT)) | ||
309 | #define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT)) | ||
310 | #define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT)) | ||
311 | #define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT)) | ||
312 | #define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT)) | ||
313 | #define VSCTRL_GAMMA_EN (1 << 26) | ||
314 | #define VSCTRL_CSC_EN (1 << 25) | ||
315 | #define VSCTRL_COSITED (1 << 22) | ||
316 | #define VSCTRL_VSWIDTH Fld(11,11) | ||
317 | #define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \ | ||
318 | (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH)) | ||
319 | #define VSCTRL_VSHEIGHT Fld(11,0) | ||
320 | #define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \ | ||
321 | (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT)) | ||
322 | |||
323 | /* VBBASE - Video Blending Base Register */ | ||
324 | #define VBBASE_GLALPHA Fld(8,24) | ||
325 | #define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA)) | ||
326 | |||
327 | #define VBBASE_COLKEY Fld(24,0) | ||
328 | #define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY)) | ||
329 | |||
330 | /* VCMSK - Video Color Key Mask Register */ | ||
331 | #define VCMSK_COLKEY_M Fld(24,0) | ||
332 | #define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M)) | ||
333 | |||
334 | /* VSCADR - Video Stream Control Rddress Register */ | ||
335 | #define VSCADR_STR_EN (1 << 31) | ||
336 | #define VSCADR_COLKEY_EN (1 << 30) | ||
337 | #define VSCADR_COLKEYSRC (1 << 29) | ||
338 | #define VSCADR_BLEND_M Fld(2,27) | ||
339 | #define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M)) | ||
340 | #define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M)) | ||
341 | #define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M)) | ||
342 | #define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M)) | ||
343 | #define VSCADR_BLEND_POS Fld(2,24) | ||
344 | #define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS)) | ||
345 | #define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS)) | ||
346 | #define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS)) | ||
347 | #define VSCADR_VBASE_ADR Fld(23,0) | ||
348 | #define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR)) | ||
349 | |||
350 | /* VUBASE - Video U Base Register */ | ||
351 | #define VUBASE_UVHALFSTR (1 << 31) | ||
352 | #define VUBASE_UBASE_ADR Fld(24,0) | ||
353 | #define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR)) | ||
354 | |||
355 | /* VVBASE - Video V Base Register */ | ||
356 | #define VVBASE_VBASE_ADR Fld(24,0) | ||
357 | #define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR)) | ||
358 | |||
359 | /* VSADR - Video Stride Address Register */ | ||
360 | #define VSADR_SRCSTRIDE Fld(10,22) | ||
361 | #define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE)) | ||
362 | #define VSADR_XSTART Fld(11,11) | ||
363 | #define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART)) | ||
364 | #define VSADR_YSTART Fld(11,0) | ||
365 | #define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART)) | ||
366 | |||
306 | /* HCCTRL - Hardware Cursor Register fields */ | 367 | /* HCCTRL - Hardware Cursor Register fields */ |
307 | #define HCCTRL_CUR_EN (1 << 31) | 368 | #define HCCTRL_CUR_EN (1 << 31) |
308 | #define HCCTRL_COLKEY_EN (1 << 29) | 369 | #define HCCTRL_COLKEY_EN (1 << 29) |
@@ -479,6 +540,30 @@ | |||
479 | #define DINTRE_HBLNK1_EN (1 << 1) | 540 | #define DINTRE_HBLNK1_EN (1 << 1) |
480 | #define DINTRE_HBLNK0_EN (1 << 0) | 541 | #define DINTRE_HBLNK0_EN (1 << 0) |
481 | 542 | ||
543 | /* DINTRS - Display Interrupt Status Register */ | ||
544 | #define DINTRS_CUR_OR_S (1 << 18) | ||
545 | #define DINTRS_STR2_OR_S (1 << 17) | ||
546 | #define DINTRS_STR1_OR_S (1 << 16) | ||
547 | #define DINTRS_CUR_UR_S (1 << 6) | ||
548 | #define DINTRS_STR2_UR_S (1 << 5) | ||
549 | #define DINTRS_STR1_UR_S (1 << 4) | ||
550 | #define DINTRS_VEVENT1_S (1 << 3) | ||
551 | #define DINTRS_VEVENT0_S (1 << 2) | ||
552 | #define DINTRS_HBLNK1_S (1 << 1) | ||
553 | #define DINTRS_HBLNK0_S (1 << 0) | ||
554 | |||
555 | /* DINTRE - Display Interrupt Enable Register */ | ||
556 | #define DINTRE_CUR_OR_EN (1 << 18) | ||
557 | #define DINTRE_STR2_OR_EN (1 << 17) | ||
558 | #define DINTRE_STR1_OR_EN (1 << 16) | ||
559 | #define DINTRE_CUR_UR_EN (1 << 6) | ||
560 | #define DINTRE_STR2_UR_EN (1 << 5) | ||
561 | #define DINTRE_STR1_UR_EN (1 << 4) | ||
562 | #define DINTRE_VEVENT1_EN (1 << 3) | ||
563 | #define DINTRE_VEVENT0_EN (1 << 2) | ||
564 | #define DINTRE_HBLNK1_EN (1 << 1) | ||
565 | #define DINTRE_HBLNK0_EN (1 << 0) | ||
566 | |||
482 | 567 | ||
483 | /* DLSTS - display load status register */ | 568 | /* DLSTS - display load status register */ |
484 | #define DLSTS_RLD_ADONE (1 << 23) | 569 | #define DLSTS_RLD_ADONE (1 << 23) |