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authorPaul A. Clarke <pc@us.ibm.com>2007-08-10 16:00:49 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-08-11 18:47:40 -0400
commite798bd95b61918e653f3d28f9176237236f2d103 (patch)
tree139853ab30618fdab1b0329cfbc68b3d01d7e117 /drivers/video/matrox/matroxfb_DAC1064.h
parentacb73865328bd6211a1452f39a4f660d26658918 (diff)
matroxfb: rectify jitter (G450/G550)
This builds upon my previous attempts to resolve some jitter problems seen with the Matrox G450 and G550 -based cards, including odd disparities observed between x86 and Power -based machines in a somewhat less hackish way (removing the hacked ifdefs). Apparently, preference should be given to use the DVI PLL when frequencies permit, the Standard PLL otherwise. The max pixel clock for the panellink interface is extracted from the PInS information on the card and used as a limit to determine which PLL to use. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Acked-by: Petr Vandrovec <petr@vandrovec.name> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/matrox/matroxfb_DAC1064.h')
-rw-r--r--drivers/video/matrox/matroxfb_DAC1064.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/video/matrox/matroxfb_DAC1064.h b/drivers/video/matrox/matroxfb_DAC1064.h
index df39c3193735..7a98ce8043d7 100644
--- a/drivers/video/matrox/matroxfb_DAC1064.h
+++ b/drivers/video/matrox/matroxfb_DAC1064.h
@@ -33,6 +33,21 @@ void DAC1064_global_restore(WPMINFO2);
33#define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */ 33#define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
34#define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */ 34#define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
35#define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */ 35#define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
36 /* drive DVI by standard(0)/DVI(1) PLL */
37 /* if set(1), C?DVICLKEN and C?DVICLKSEL must be set(1) */
38#define M1064_XDVICLKCTRL_DVIDATAPATHSEL 0x01
39 /* drive CRTC1 by standard(0)/DVI(1) PLL */
40#define M1064_XDVICLKCTRL_C1DVICLKSEL 0x02
41 /* drive CRTC2 by standard(0)/DVI(1) PLL */
42#define M1064_XDVICLKCTRL_C2DVICLKSEL 0x04
43 /* pixel clock allowed to(0)/blocked from(1) driving CRTC1 */
44#define M1064_XDVICLKCTRL_C1DVICLKEN 0x08
45 /* DVI PLL loop filter bandwidth selection bits */
46#define M1064_XDVICLKCTRL_DVILOOPCTL 0x30
47 /* CRTC2 pixel clock allowed to(0)/blocked from(1) driving CRTC2 */
48#define M1064_XDVICLKCTRL_C2DVICLKEN 0x40
49 /* P1PLL loop filter bandwith selection */
50#define M1064_XDVICLKCTRL_P1LOOPBWDTCTL 0x80
36#define M1064_XCURCOL0RED 0x08 51#define M1064_XCURCOL0RED 0x08
37#define M1064_XCURCOL0GREEN 0x09 52#define M1064_XCURCOL0GREEN 0x09
38#define M1064_XCURCOL0BLUE 0x0A 53#define M1064_XCURCOL0BLUE 0x0A