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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/intelfb/intelfbhw.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/video/intelfb/intelfbhw.h')
-rw-r--r--drivers/video/intelfb/intelfbhw.h570
1 files changed, 570 insertions, 0 deletions
diff --git a/drivers/video/intelfb/intelfbhw.h b/drivers/video/intelfb/intelfbhw.h
new file mode 100644
index 000000000000..ba1920159f52
--- /dev/null
+++ b/drivers/video/intelfb/intelfbhw.h
@@ -0,0 +1,570 @@
1#ifndef _INTELFBHW_H
2#define _INTELFBHW_H
3
4/* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */
5
6
7/*** HW-specific data ***/
8
9/* Information about the 852GM/855GM variants */
10#define INTEL_85X_CAPID 0x44
11#define INTEL_85X_VARIANT_MASK 0x7
12#define INTEL_85X_VARIANT_SHIFT 5
13#define INTEL_VAR_855GME 0x0
14#define INTEL_VAR_855GM 0x4
15#define INTEL_VAR_852GME 0x2
16#define INTEL_VAR_852GM 0x5
17
18/* Information about DVO/LVDS Ports */
19#define DVOA_PORT 0x1
20#define DVOB_PORT 0x2
21#define DVOC_PORT 0x4
22#define LVDS_PORT 0x8
23
24/*
25 * The Bridge device's PCI config space has information about the
26 * fb aperture size and the amount of pre-reserved memory.
27 */
28#define INTEL_GMCH_CTRL 0x52
29#define INTEL_GMCH_ENABLED 0x4
30#define INTEL_GMCH_MEM_MASK 0x1
31#define INTEL_GMCH_MEM_64M 0x1
32#define INTEL_GMCH_MEM_128M 0
33
34#define INTEL_830_GMCH_GMS_MASK (0x7 << 4)
35#define INTEL_830_GMCH_GMS_DISABLED (0x0 << 4)
36#define INTEL_830_GMCH_GMS_LOCAL (0x1 << 4)
37#define INTEL_830_GMCH_GMS_STOLEN_512 (0x2 << 4)
38#define INTEL_830_GMCH_GMS_STOLEN_1024 (0x3 << 4)
39#define INTEL_830_GMCH_GMS_STOLEN_8192 (0x4 << 4)
40
41#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
42#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
43#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
44#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
45#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
46#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
47#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
48
49#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
50#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
51
52/* HW registers */
53
54/* Fence registers */
55#define FENCE 0x2000
56#define FENCE_NUM 8
57
58/* Primary ring buffer */
59#define PRI_RING_TAIL 0x2030
60#define RING_TAIL_MASK 0x001ffff8
61#define RING_INUSE 0x1
62
63#define PRI_RING_HEAD 0x2034
64#define RING_HEAD_WRAP_MASK 0x7ff
65#define RING_HEAD_WRAP_SHIFT 21
66#define RING_HEAD_MASK 0x001ffffc
67
68#define PRI_RING_START 0x2038
69#define RING_START_MASK 0xfffff000
70
71#define PRI_RING_LENGTH 0x203c
72#define RING_LENGTH_MASK 0x001ff000
73#define RING_REPORT_MASK (0x3 << 1)
74#define RING_NO_REPORT (0x0 << 1)
75#define RING_REPORT_64K (0x1 << 1)
76#define RING_REPORT_4K (0x2 << 1)
77#define RING_REPORT_128K (0x3 << 1)
78#define RING_ENABLE 0x1
79
80/*
81 * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head,
82 * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP
83 */
84#define RING_MIN_FREE 64
85
86#define IPEHR 0x2088
87
88#define INSTDONE 0x2090
89#define PRI_RING_EMPTY 1
90
91#define INSTPM 0x20c0
92#define SYNC_FLUSH_ENABLE (1 << 5)
93
94#define INSTPS 0x20c4
95
96#define MEM_MODE 0x20cc
97
98#define MASK_SHIFT 16
99
100#define FW_BLC_0 0x20d8
101#define FW_DISPA_WM_SHIFT 0
102#define FW_DISPA_WM_MASK 0x3f
103#define FW_DISPA_BL_SHIFT 8
104#define FW_DISPA_BL_MASK 0xf
105#define FW_DISPB_WM_SHIFT 16
106#define FW_DISPB_WM_MASK 0x1f
107#define FW_DISPB_BL_SHIFT 24
108#define FW_DISPB_BL_MASK 0x7
109
110#define FW_BLC_1 0x20dc
111#define FW_DISPC_WM_SHIFT 0
112#define FW_DISPC_WM_MASK 0x1f
113#define FW_DISPC_BL_SHIFT 8
114#define FW_DISPC_BL_MASK 0x7
115
116
117/* PLL registers */
118#define VGA0_DIVISOR 0x06000
119#define VGA1_DIVISOR 0x06004
120#define VGAPD 0x06010
121#define VGAPD_0_P1_SHIFT 0
122#define VGAPD_0_P1_FORCE_DIV2 (1 << 5)
123#define VGAPD_0_P2_SHIFT 7
124#define VGAPD_1_P1_SHIFT 8
125#define VGAPD_1_P1_FORCE_DIV2 (1 << 13)
126#define VGAPD_1_P2_SHIFT 15
127
128#define DPLL_A 0x06014
129#define DPLL_B 0x06018
130#define DPLL_VCO_ENABLE (1 << 31)
131#define DPLL_2X_CLOCK_ENABLE (1 << 30)
132#define DPLL_SYNCLOCK_ENABLE (1 << 29)
133#define DPLL_VGA_MODE_DISABLE (1 << 28)
134#define DPLL_P2_MASK 1
135#define DPLL_P2_SHIFT 23
136#define DPLL_P1_FORCE_DIV2 (1 << 21)
137#define DPLL_P1_MASK 0x1f
138#define DPLL_P1_SHIFT 16
139#define DPLL_REFERENCE_SELECT_MASK (0x3 << 13)
140#define DPLL_REFERENCE_DEFAULT (0x0 << 13)
141#define DPLL_REFERENCE_TVCLK (0x2 << 13)
142#define DPLL_RATE_SELECT_MASK (1 << 8)
143#define DPLL_RATE_SELECT_FP0 (0 << 8)
144#define DPLL_RATE_SELECT_FP1 (1 << 8)
145
146#define FPA0 0x06040
147#define FPA1 0x06044
148#define FPB0 0x06048
149#define FPB1 0x0604c
150#define FP_DIVISOR_MASK 0x3f
151#define FP_N_DIVISOR_SHIFT 16
152#define FP_M1_DIVISOR_SHIFT 8
153#define FP_M2_DIVISOR_SHIFT 0
154
155/* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
156/* Clock values are in units of kHz */
157#define PLL_REFCLK 48000
158#define MIN_VCO_FREQ 930000
159#define MAX_VCO_FREQ 1400000
160#define MIN_CLOCK 25000
161#define MAX_CLOCK 350000
162#define P_TRANSITION_CLOCK 165000
163#define MIN_M 108
164#define MAX_M 140
165#define MIN_M1 18
166#define MAX_M1 26
167#define MIN_M2 6
168#define MAX_M2 16
169#define MIN_P 4
170#define MAX_P 128
171#define MIN_P1 0
172#define MAX_P1 31
173#define MIN_N 3
174#define MAX_N 16
175
176#define CALC_VCLOCK(m1, m2, n, p1, p2) \
177 ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \
178 (((p1) + 2) * (1 << (p2 + 1))))
179
180#define CALC_VCLOCK3(m, n, p) ((PLL_REFCLK * (m) / (n)) / (p))
181
182/* Two pipes */
183#define PIPE_A 0
184#define PIPE_B 1
185#define PIPE_MASK 1
186
187/* palette registers */
188#define PALETTE_A 0x0a000
189#define PALETTE_B 0x0a800
190#ifndef PALETTE_8_ENTRIES
191#define PALETTE_8_ENTRIES 256
192#endif
193#define PALETTE_8_SIZE (PALETTE_8_ENTRIES * 4)
194#define PALETTE_10_ENTRIES 128
195#define PALETTE_10_SIZE (PALETTE_10_ENTRIES * 8)
196#define PALETTE_8_MASK 0xff
197#define PALETTE_8_RED_SHIFT 16
198#define PALETTE_8_GREEN_SHIFT 8
199#define PALETTE_8_BLUE_SHIFT 0
200
201/* CRTC registers */
202#define HTOTAL_A 0x60000
203#define HBLANK_A 0x60004
204#define HSYNC_A 0x60008
205#define VTOTAL_A 0x6000c
206#define VBLANK_A 0x60010
207#define VSYNC_A 0x60014
208#define SRC_SIZE_A 0x6001c
209#define BCLRPAT_A 0x60020
210
211#define HTOTAL_B 0x61000
212#define HBLANK_B 0x61004
213#define HSYNC_B 0x61008
214#define VTOTAL_B 0x6100c
215#define VBLANK_B 0x61010
216#define VSYNC_B 0x61014
217#define SRC_SIZE_B 0x6101c
218#define BCLRPAT_B 0x61020
219
220#define HTOTAL_MASK 0xfff
221#define HTOTAL_SHIFT 16
222#define HACTIVE_MASK 0x7ff
223#define HACTIVE_SHIFT 0
224#define HBLANKEND_MASK 0xfff
225#define HBLANKEND_SHIFT 16
226#define HBLANKSTART_MASK 0xfff
227#define HBLANKSTART_SHIFT 0
228#define HSYNCEND_MASK 0xfff
229#define HSYNCEND_SHIFT 16
230#define HSYNCSTART_MASK 0xfff
231#define HSYNCSTART_SHIFT 0
232#define VTOTAL_MASK 0xfff
233#define VTOTAL_SHIFT 16
234#define VACTIVE_MASK 0x7ff
235#define VACTIVE_SHIFT 0
236#define VBLANKEND_MASK 0xfff
237#define VBLANKEND_SHIFT 16
238#define VBLANKSTART_MASK 0xfff
239#define VBLANKSTART_SHIFT 0
240#define VSYNCEND_MASK 0xfff
241#define VSYNCEND_SHIFT 16
242#define VSYNCSTART_MASK 0xfff
243#define VSYNCSTART_SHIFT 0
244#define SRC_SIZE_HORIZ_MASK 0x7ff
245#define SRC_SIZE_HORIZ_SHIFT 16
246#define SRC_SIZE_VERT_MASK 0x7ff
247#define SRC_SIZE_VERT_SHIFT 0
248
249#define ADPA 0x61100
250#define ADPA_DAC_ENABLE (1 << 31)
251#define ADPA_DAC_DISABLE 0
252#define ADPA_PIPE_SELECT_SHIFT 30
253#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
254#define ADPA_SETS_HVPOLARITY 0
255#define ADPA_DPMS_CONTROL_MASK (0x3 << 10)
256#define ADPA_DPMS_D0 (0x0 << 10)
257#define ADPA_DPMS_D2 (0x1 << 10)
258#define ADPA_DPMS_D1 (0x2 << 10)
259#define ADPA_DPMS_D3 (0x3 << 10)
260#define ADPA_VSYNC_ACTIVE_SHIFT 4
261#define ADPA_HSYNC_ACTIVE_SHIFT 3
262#define ADPA_SYNC_ACTIVE_MASK 1
263#define ADPA_SYNC_ACTIVE_HIGH 1
264#define ADPA_SYNC_ACTIVE_LOW 0
265
266#define DVOA 0x61120
267#define DVOB 0x61140
268#define DVOC 0x61160
269#define LVDS 0x61180
270#define PORT_ENABLE (1 << 31)
271#define PORT_PIPE_SELECT_SHIFT 30
272#define PORT_TV_FLAGS_MASK 0xFF
273#define PORT_TV_FLAGS 0xC4 // ripped from my BIOS
274 // to understand and correct
275
276#define DVOA_SRCDIM 0x61124
277#define DVOB_SRCDIM 0x61144
278#define DVOC_SRCDIM 0x61164
279
280#define PIPEACONF 0x70008
281#define PIPEBCONF 0x71008
282#define PIPECONF_ENABLE (1 << 31)
283#define PIPECONF_DISABLE 0
284#define PIPECONF_DOUBLE_WIDE (1 << 30)
285#define PIPECONF_SINGLE_WIDE 0
286#define PIPECONF_LOCKED (1 << 25)
287#define PIPECONF_UNLOCKED 0
288#define PIPECONF_GAMMA (1 << 24)
289#define PIPECONF_PALETTE 0
290
291#define DISPARB 0x70030
292#define DISPARB_AEND_MASK 0x1ff
293#define DISPARB_AEND_SHIFT 0
294#define DISPARB_BEND_MASK 0x3ff
295#define DISPARB_BEND_SHIFT 9
296
297/* Desktop HW cursor */
298#define CURSOR_CONTROL 0x70080
299#define CURSOR_ENABLE (1 << 31)
300#define CURSOR_GAMMA_ENABLE (1 << 30)
301#define CURSOR_STRIDE_MASK (0x3 << 28)
302#define CURSOR_STRIDE_256 (0x0 << 28)
303#define CURSOR_STRIDE_512 (0x1 << 28)
304#define CURSOR_STRIDE_1K (0x2 << 28)
305#define CURSOR_STRIDE_2K (0x3 << 28)
306#define CURSOR_FORMAT_MASK (0x7 << 24)
307#define CURSOR_FORMAT_2C (0x0 << 24)
308#define CURSOR_FORMAT_3C (0x1 << 24)
309#define CURSOR_FORMAT_4C (0x2 << 24)
310#define CURSOR_FORMAT_ARGB (0x4 << 24)
311#define CURSOR_FORMAT_XRGB (0x5 << 24)
312
313/* Mobile HW cursor (and i810) */
314#define CURSOR_A_CONTROL CURSOR_CONTROL
315#define CURSOR_B_CONTROL 0x700c0
316#define CURSOR_MODE_MASK 0x27
317#define CURSOR_MODE_DISABLE 0
318#define CURSOR_MODE_64_3C 0x04
319#define CURSOR_MODE_64_4C_AX 0x05
320#define CURSOR_MODE_64_4C 0x06
321#define CURSOR_MODE_64_32B_AX 0x07
322#define CURSOR_MODE_64_ARGB_AX 0x27
323#define CURSOR_PIPE_SELECT_SHIFT 28
324#define CURSOR_MOBILE_GAMMA_ENABLE (1 << 26)
325#define CURSOR_MEM_TYPE_LOCAL (1 << 25)
326
327/* All platforms (desktop has no pipe B) */
328#define CURSOR_A_BASEADDR 0x70084
329#define CURSOR_B_BASEADDR 0x700c4
330#define CURSOR_BASE_MASK 0xffffff00
331
332#define CURSOR_A_POSITION 0x70088
333#define CURSOR_B_POSITION 0x700c8
334#define CURSOR_POS_SIGN (1 << 15)
335#define CURSOR_POS_MASK 0x7ff
336#define CURSOR_X_SHIFT 0
337#define CURSOR_Y_SHIFT 16
338
339#define CURSOR_A_PALETTE0 0x70090
340#define CURSOR_A_PALETTE1 0x70094
341#define CURSOR_A_PALETTE2 0x70098
342#define CURSOR_A_PALETTE3 0x7009c
343#define CURSOR_B_PALETTE0 0x700d0
344#define CURSOR_B_PALETTE1 0x700d4
345#define CURSOR_B_PALETTE2 0x700d8
346#define CURSOR_B_PALETTE3 0x700dc
347#define CURSOR_COLOR_MASK 0xff
348#define CURSOR_RED_SHIFT 16
349#define CURSOR_GREEN_SHIFT 8
350#define CURSOR_BLUE_SHIFT 0
351#define CURSOR_PALETTE_MASK 0xffffff
352
353/* Desktop only */
354#define CURSOR_SIZE 0x700a0
355#define CURSOR_SIZE_MASK 0x3ff
356#define CURSOR_SIZE_H_SHIFT 0
357#define CURSOR_SIZE_V_SHIFT 12
358
359#define DSPACNTR 0x70180
360#define DSPBCNTR 0x71180
361#define DISPPLANE_PLANE_ENABLE (1 << 31)
362#define DISPPLANE_PLANE_DISABLE 0
363#define DISPPLANE_GAMMA_ENABLE (1<<30)
364#define DISPPLANE_GAMMA_DISABLE 0
365#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
366#define DISPPLANE_8BPP (0x2<<26)
367#define DISPPLANE_15_16BPP (0x4<<26)
368#define DISPPLANE_16BPP (0x5<<26)
369#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
370#define DISPPLANE_32BPP (0x7<<26)
371#define DISPPLANE_STEREO_ENABLE (1<<25)
372#define DISPPLANE_STEREO_DISABLE 0
373#define DISPPLANE_SEL_PIPE_SHIFT 24
374#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
375#define DISPPLANE_SRC_KEY_DISABLE 0
376#define DISPPLANE_LINE_DOUBLE (1<<20)
377#define DISPPLANE_NO_LINE_DOUBLE 0
378#define DISPPLANE_STEREO_POLARITY_FIRST 0
379#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
380/* plane B only */
381#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
382#define DISPPLANE_ALPHA_TRANS_DISABLE 0
383#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
384#define DISPPLANE_SPRITE_ABOVE_OVERLAY 1
385
386#define DSPABASE 0x70184
387#define DSPASTRIDE 0x70188
388
389#define DSPBBASE 0x71184
390#define DSPBSTRIDE 0x71188
391
392#define VGACNTRL 0x71400
393#define VGA_DISABLE (1 << 31)
394#define VGA_ENABLE 0
395#define VGA_PIPE_SELECT_SHIFT 29
396#define VGA_PALETTE_READ_SELECT 23
397#define VGA_PALETTE_A_WRITE_DISABLE (1 << 22)
398#define VGA_PALETTE_B_WRITE_DISABLE (1 << 21)
399#define VGA_LEGACY_PALETTE (1 << 20)
400#define VGA_6BIT_DAC 0
401#define VGA_8BIT_DAC (1 << 20)
402
403#define ADD_ID 0x71408
404#define ADD_ID_MASK 0xff
405
406/* BIOS scratch area registers (830M and 845G). */
407#define SWF0 0x71410
408#define SWF1 0x71414
409#define SWF2 0x71418
410#define SWF3 0x7141c
411#define SWF4 0x71420
412#define SWF5 0x71424
413#define SWF6 0x71428
414
415/* BIOS scratch area registers (852GM, 855GM, 865G). */
416#define SWF00 0x70410
417#define SWF01 0x70414
418#define SWF02 0x70418
419#define SWF03 0x7041c
420#define SWF04 0x70420
421#define SWF05 0x70424
422#define SWF06 0x70428
423
424#define SWF10 SWF0
425#define SWF11 SWF1
426#define SWF12 SWF2
427#define SWF13 SWF3
428#define SWF14 SWF4
429#define SWF15 SWF5
430#define SWF16 SWF6
431
432#define SWF30 0x72414
433#define SWF31 0x72418
434#define SWF32 0x7241c
435
436/* Memory Commands */
437#define MI_NOOP (0x00 << 23)
438#define MI_NOOP_WRITE_ID (1 << 22)
439#define MI_NOOP_ID_MASK ((1 << 22) - 1)
440
441#define MI_FLUSH (0x04 << 23)
442#define MI_WRITE_DIRTY_STATE (1 << 4)
443#define MI_END_SCENE (1 << 3)
444#define MI_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
445#define MI_INVALIDATE_MAP_CACHE (1 << 0)
446
447#define MI_STORE_DWORD_IMM ((0x20 << 23) | 1)
448
449/* 2D Commands */
450#define COLOR_BLT_CMD ((2 << 29) | (0x40 << 22) | 3)
451#define XY_COLOR_BLT_CMD ((2 << 29) | (0x50 << 22) | 4)
452#define XY_SETUP_CLIP_BLT_CMD ((2 << 29) | (0x03 << 22) | 1)
453#define XY_SRC_COPY_BLT_CMD ((2 << 29) | (0x53 << 22) | 6)
454#define SRC_COPY_BLT_CMD ((2 << 29) | (0x43 << 22) | 4)
455#define XY_MONO_PAT_BLT_CMD ((2 << 29) | (0x52 << 22) | 7)
456#define XY_MONO_SRC_BLT_CMD ((2 << 29) | (0x54 << 22) | 6)
457#define XY_MONO_SRC_IMM_BLT_CMD ((2 << 29) | (0x71 << 22) | 5)
458#define TXT_IMM_BLT_CMD ((2 << 29) | (0x30 << 22) | 2)
459#define SETUP_BLT_CMD ((2 << 29) | (0x00 << 22) | 6)
460
461#define DW_LENGTH_MASK 0xff
462
463#define WRITE_ALPHA (1 << 21)
464#define WRITE_RGB (1 << 20)
465#define VERT_SEED (3 << 8)
466#define HORIZ_SEED (3 << 12)
467
468#define COLOR_DEPTH_8 (0 << 24)
469#define COLOR_DEPTH_16 (1 << 24)
470#define COLOR_DEPTH_32 (3 << 24)
471
472#define SRC_ROP_GXCOPY 0xcc
473#define SRC_ROP_GXXOR 0x66
474
475#define PAT_ROP_GXCOPY 0xf0
476#define PAT_ROP_GXXOR 0x5a
477
478#define PITCH_SHIFT 0
479#define ROP_SHIFT 16
480#define WIDTH_SHIFT 0
481#define HEIGHT_SHIFT 16
482
483/* in bytes */
484#define MAX_MONO_IMM_SIZE 128
485
486
487/*** Macros ***/
488
489/* I/O macros */
490#define INREG8(addr) readb((u8 __iomem *)(dinfo->mmio_base + (addr)))
491#define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr)))
492#define OUTREG8(addr, val) writeb((val),(u8 __iomem *)(dinfo->mmio_base + \
493 (addr)))
494#define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \
495 (addr)))
496
497/* Ring buffer macros */
498#define OUT_RING(n) do { \
499 writel((n), (u32 __iomem *)(dinfo->ring.virtual + dinfo->ring_tail));\
500 dinfo->ring_tail += 4; \
501 dinfo->ring_tail &= dinfo->ring_tail_mask; \
502} while (0)
503
504#define START_RING(n) do { \
505 if (dinfo->ring_space < (n) * 4) \
506 wait_ring(dinfo,(n) * 4); \
507 dinfo->ring_space -= (n) * 4; \
508} while (0)
509
510#define ADVANCE_RING() do { \
511 OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \
512} while (0)
513
514#define DO_RING_IDLE() do { \
515 u32 head, tail; \
516 do { \
517 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \
518 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
519 udelay(10); \
520 } while (head != tail); \
521} while (0)
522
523
524/* function protoypes */
525extern int intelfbhw_get_chipset(struct pci_dev *pdev, const char **name,
526 int *chipset, int *mobile);
527extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
528 int *stolen_size);
529extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
530extern const char *intelfbhw_dvo_to_string(int dvo);
531extern int intelfbhw_validate_mode(struct intelfb_info *dinfo,
532 struct fb_var_screeninfo *var);
533extern int intelfbhw_pan_display(struct fb_var_screeninfo *var,
534 struct fb_info *info);
535extern void intelfbhw_do_blank(int blank, struct fb_info *info);
536extern void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
537 unsigned red, unsigned green, unsigned blue,
538 unsigned transp);
539extern int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
540 struct intelfb_hwstate *hw, int flag);
541extern void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
542 struct intelfb_hwstate *hw);
543extern int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
544 struct intelfb_hwstate *hw,
545 struct fb_var_screeninfo *var);
546extern int intelfbhw_program_mode(struct intelfb_info *dinfo,
547 const struct intelfb_hwstate *hw, int blank);
548extern void intelfbhw_do_sync(struct intelfb_info *dinfo);
549extern void intelfbhw_2d_stop(struct intelfb_info *dinfo);
550extern void intelfbhw_2d_start(struct intelfb_info *dinfo);
551extern void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y,
552 u32 w, u32 h, u32 color, u32 pitch, u32 bpp,
553 u32 rop);
554extern void intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
555 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch,
556 u32 bpp);
557extern int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg,
558 u32 w, u32 h, const u8* cdat, u32 x, u32 y,
559 u32 pitch, u32 bpp);
560extern void intelfbhw_cursor_init(struct intelfb_info *dinfo);
561extern void intelfbhw_cursor_hide(struct intelfb_info *dinfo);
562extern void intelfbhw_cursor_show(struct intelfb_info *dinfo);
563extern void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y);
564extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg,
565 u32 fg);
566extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width,
567 int height, u8 *data);
568extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo);
569
570#endif /* _INTELFBHW_H */