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authorJordan Crouse <jordan.crouse@amd.com>2006-12-08 05:40:56 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-08 11:29:08 -0500
commit58219896df521ddd749bee48a8465db69b6163f3 (patch)
tree12bacc56be8aa2bac5650e97b767e91bceaffe6c /drivers/video/geode/video_gx.c
parent53d53bd4ab3fd1498f728fa96635ab95d1ec8ba0 (diff)
[PATCH] gxfb: Turn on the flatpanel power and data
For Geode devices without a flatpanel aware BIOS, this enables the flatpanel power and data. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Acked-by: James Simmons <jsimmons@infradead.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/video/geode/video_gx.c')
-rw-r--r--drivers/video/geode/video_gx.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c
index bee0741794a3..7f3f18d06718 100644
--- a/drivers/video/geode/video_gx.c
+++ b/drivers/video/geode/video_gx.c
@@ -220,7 +220,13 @@ gx_configure_tft(struct fb_info *info)
220 /* Set the dither control */ 220 /* Set the dither control */
221 writel(0x70, par->vid_regs + GX_FP_DFC); 221 writel(0x70, par->vid_regs + GX_FP_DFC);
222 222
223 /* Turn on the device */ 223 /* Enable the FP data and power (in case the BIOS didn't) */
224
225 fp = readl(par->vid_regs + GX_DCFG);
226 fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
227 writel(fp, par->vid_regs + GX_DCFG);
228
229 /* Unblank the panel */
224 230
225 fp = readl(par->vid_regs + GX_FP_PM); 231 fp = readl(par->vid_regs + GX_FP_PM);
226 fp |= GX_FP_PM_P; 232 fp |= GX_FP_PM_P;
@@ -245,9 +251,12 @@ static void gx_configure_display(struct fb_info *info)
245 writel(misc, par->vid_regs + GX_MISC); 251 writel(misc, par->vid_regs + GX_MISC);
246 252
247 /* Write the display configuration */ 253 /* Write the display configuration */
248
249 dcfg = readl(par->vid_regs + GX_DCFG); 254 dcfg = readl(par->vid_regs + GX_DCFG);
250 255
256 /* Disable hsync and vsync */
257 dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
258 writel(dcfg, par->vid_regs + GX_DCFG);
259
251 /* Clear bits from existing mode. */ 260 /* Clear bits from existing mode. */
252 dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK 261 dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
253 | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL 262 | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL