diff options
author | Andres Salomon <dilinger@queued.net> | 2008-04-28 05:15:24 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-28 11:58:39 -0400 |
commit | f5c90e85dc77669a55fecfb593bb8e7f47374ee2 (patch) | |
tree | e33321b93005f2e0db1793f5c0c397cb386b4d28 /drivers/video/geode/lxfb_ops.c | |
parent | 9286361beab8ef5c928ecb2bfefe68ab0176238b (diff) |
lxfb: clean up register definitions
- Rename various bitfield defines to match the data sheet names.
- Rename DF_ register definitions to VP_ to match the data sheet;
ie, DF_PAR -> VP_PAR.
- for GP/DC registers, rather than defining to specific addresses, use
an enum to number them sequentially and just multiply by 4 (bytes) to
access them (in read_*/write_* functions).
- for VP/FP registers, use an enum and multiple by 8 (bytes). They're
64bit registers.
Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/geode/lxfb_ops.c')
-rw-r--r-- | drivers/video/geode/lxfb_ops.c | 162 |
1 files changed, 81 insertions, 81 deletions
diff --git a/drivers/video/geode/lxfb_ops.c b/drivers/video/geode/lxfb_ops.c index d1210e2d3894..7be6f578e87e 100644 --- a/drivers/video/geode/lxfb_ops.c +++ b/drivers/video/geode/lxfb_ops.c | |||
@@ -210,47 +210,47 @@ static void lx_graphics_disable(struct fb_info *info) | |||
210 | 210 | ||
211 | /* Note: This assumes that the video is in a quitet state */ | 211 | /* Note: This assumes that the video is in a quitet state */ |
212 | 212 | ||
213 | write_vp(par, DF_ALPHA_CONTROL_1, 0); | 213 | write_vp(par, VP_A1T, 0); |
214 | write_vp(par, DF_ALPHA_CONTROL_1 + 32, 0); | 214 | write_vp(par, VP_A2T, 0); |
215 | write_vp(par, DF_ALPHA_CONTROL_1 + 64, 0); | 215 | write_vp(par, VP_A3T, 0); |
216 | 216 | ||
217 | /* Turn off the VGA and video enable */ | 217 | /* Turn off the VGA and video enable */ |
218 | val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GCFG_VGAE | DC_GCFG_VIDE); | 218 | val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE | |
219 | DC_GENERAL_CFG_VIDE); | ||
219 | 220 | ||
220 | write_dc(par, DC_GENERAL_CFG, val); | 221 | write_dc(par, DC_GENERAL_CFG, val); |
221 | 222 | ||
222 | val = read_vp(par, DF_VIDEO_CFG) & ~DF_VCFG_VID_EN; | 223 | val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN; |
223 | write_vp(par, DF_VIDEO_CFG, val); | 224 | write_vp(par, VP_VCFG, val); |
224 | 225 | ||
225 | write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_VSYNC_IRQ_MASK | DC_IRQ_STATUS | | 226 | write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK | |
226 | DC_VSYNC_IRQ_STATUS); | 227 | DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS); |
227 | 228 | ||
228 | val = read_dc(par, DC_GENLCK_CTRL) & ~DC_GENLCK_ENABLE; | 229 | val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN; |
229 | write_dc(par, DC_GENLCK_CTRL, val); | 230 | write_dc(par, DC_GENLK_CTL, val); |
230 | 231 | ||
231 | val = read_dc(par, DC_COLOR_KEY) & ~DC_CLR_KEY_ENABLE; | 232 | val = read_dc(par, DC_CLR_KEY); |
232 | write_dc(par, DC_COLOR_KEY, val & ~DC_CLR_KEY_ENABLE); | 233 | write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN); |
233 | 234 | ||
234 | /* We don't actually blank the panel, due to the long latency | 235 | /* We don't actually blank the panel, due to the long latency |
235 | involved with bringing it back */ | 236 | involved with bringing it back */ |
236 | 237 | ||
237 | val = read_vp(par, DF_MISC) | DF_MISC_DAC_PWRDN; | 238 | val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN; |
238 | write_vp(par, DF_MISC, val); | 239 | write_vp(par, VP_MISC, val); |
239 | 240 | ||
240 | /* Turn off the display */ | 241 | /* Turn off the display */ |
241 | 242 | ||
242 | val = read_vp(par, DF_DISPLAY_CFG); | 243 | val = read_vp(par, VP_DCFG); |
243 | write_vp(par, DF_DISPLAY_CFG, val & | 244 | write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | |
244 | ~(DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | | 245 | VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN)); |
245 | DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN)); | ||
246 | 246 | ||
247 | gcfg = read_dc(par, DC_GENERAL_CFG); | 247 | gcfg = read_dc(par, DC_GENERAL_CFG); |
248 | gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE); | 248 | gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE); |
249 | write_dc(par, DC_GENERAL_CFG, gcfg); | 249 | write_dc(par, DC_GENERAL_CFG, gcfg); |
250 | 250 | ||
251 | /* Turn off the TGEN */ | 251 | /* Turn off the TGEN */ |
252 | val = read_dc(par, DC_DISPLAY_CFG); | 252 | val = read_dc(par, DC_DISPLAY_CFG); |
253 | val &= ~DC_DCFG_TGEN; | 253 | val &= ~DC_DISPLAY_CFG_TGEN; |
254 | write_dc(par, DC_DISPLAY_CFG, val); | 254 | write_dc(par, DC_DISPLAY_CFG, val); |
255 | 255 | ||
256 | /* Wait 1000 usecs to ensure that the TGEN is clear */ | 256 | /* Wait 1000 usecs to ensure that the TGEN is clear */ |
@@ -258,14 +258,14 @@ static void lx_graphics_disable(struct fb_info *info) | |||
258 | 258 | ||
259 | /* Turn off the FIFO loader */ | 259 | /* Turn off the FIFO loader */ |
260 | 260 | ||
261 | gcfg &= ~DC_GCFG_DFLE; | 261 | gcfg &= ~DC_GENERAL_CFG_DFLE; |
262 | write_dc(par, DC_GENERAL_CFG, gcfg); | 262 | write_dc(par, DC_GENERAL_CFG, gcfg); |
263 | 263 | ||
264 | /* Lastly, wait for the GP to go idle */ | 264 | /* Lastly, wait for the GP to go idle */ |
265 | 265 | ||
266 | do { | 266 | do { |
267 | val = read_gp(par, GP_BLT_STATUS); | 267 | val = read_gp(par, GP_BLT_STATUS); |
268 | } while ((val & GP_BS_BLT_BUSY) || !(val & GP_BS_CB_EMPTY)); | 268 | } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE)); |
269 | } | 269 | } |
270 | 270 | ||
271 | static void lx_graphics_enable(struct fb_info *info) | 271 | static void lx_graphics_enable(struct fb_info *info) |
@@ -274,30 +274,30 @@ static void lx_graphics_enable(struct fb_info *info) | |||
274 | u32 temp, config; | 274 | u32 temp, config; |
275 | 275 | ||
276 | /* Set the video request register */ | 276 | /* Set the video request register */ |
277 | write_vp(par, DF_VIDEO_REQUEST, 0); | 277 | write_vp(par, VP_VRR, 0); |
278 | 278 | ||
279 | /* Set up the polarities */ | 279 | /* Set up the polarities */ |
280 | 280 | ||
281 | config = read_vp(par, DF_DISPLAY_CFG); | 281 | config = read_vp(par, VP_DCFG); |
282 | 282 | ||
283 | config &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK | | 283 | config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY | |
284 | DF_DCFG_CRT_HSYNC_POL | DF_DCFG_CRT_VSYNC_POL); | 284 | VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL); |
285 | 285 | ||
286 | config |= (DF_DCFG_CRT_SYNC_SKW_INIT | DF_DCFG_PWR_SEQ_DLY_INIT | | 286 | config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT |
287 | DF_DCFG_GV_PAL_BYP); | 287 | | VP_DCFG_GV_GAM); |
288 | 288 | ||
289 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) | 289 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) |
290 | config |= DF_DCFG_CRT_HSYNC_POL; | 290 | config |= VP_DCFG_CRT_HSYNC_POL; |
291 | 291 | ||
292 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) | 292 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) |
293 | config |= DF_DCFG_CRT_VSYNC_POL; | 293 | config |= VP_DCFG_CRT_VSYNC_POL; |
294 | 294 | ||
295 | if (par->output & OUTPUT_PANEL) { | 295 | if (par->output & OUTPUT_PANEL) { |
296 | u32 msrlo, msrhi; | 296 | u32 msrlo, msrhi; |
297 | 297 | ||
298 | write_fp(par, DF_PANEL_TIM1, DF_DEFAULT_TFT_PMTIM1); | 298 | write_fp(par, FP_PT1, 0); |
299 | write_fp(par, DF_PANEL_TIM2, DF_DEFAULT_TFT_PMTIM2); | 299 | write_fp(par, FP_PT2, FP_PT2_SCRC); |
300 | write_fp(par, DF_DITHER_CONTROL, DF_DEFAULT_TFT_DITHCTL); | 300 | write_fp(par, FP_DFC, FP_DFC_BC); |
301 | 301 | ||
302 | msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW; | 302 | msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW; |
303 | msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH; | 303 | msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH; |
@@ -306,27 +306,27 @@ static void lx_graphics_enable(struct fb_info *info) | |||
306 | } | 306 | } |
307 | 307 | ||
308 | if (par->output & OUTPUT_CRT) { | 308 | if (par->output & OUTPUT_CRT) { |
309 | config |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | | 309 | config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | |
310 | DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN; | 310 | VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN; |
311 | } | 311 | } |
312 | 312 | ||
313 | write_vp(par, DF_DISPLAY_CFG, config); | 313 | write_vp(par, VP_DCFG, config); |
314 | 314 | ||
315 | /* Turn the CRT dacs back on */ | 315 | /* Turn the CRT dacs back on */ |
316 | 316 | ||
317 | if (par->output & OUTPUT_CRT) { | 317 | if (par->output & OUTPUT_CRT) { |
318 | temp = read_vp(par, DF_MISC); | 318 | temp = read_vp(par, VP_MISC); |
319 | temp &= ~(DF_MISC_DAC_PWRDN | DF_MISC_A_PWRDN); | 319 | temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN); |
320 | write_vp(par, DF_MISC, temp); | 320 | write_vp(par, VP_MISC, temp); |
321 | } | 321 | } |
322 | 322 | ||
323 | /* Turn the panel on (if it isn't already) */ | 323 | /* Turn the panel on (if it isn't already) */ |
324 | 324 | ||
325 | if (par->output & OUTPUT_PANEL) { | 325 | if (par->output & OUTPUT_PANEL) { |
326 | temp = read_fp(par, DF_FP_PM); | 326 | temp = read_fp(par, FP_PM); |
327 | 327 | ||
328 | if (!(temp & 0x09)) | 328 | if (!(temp & 0x09)) |
329 | write_fp(par, DF_FP_PM, temp | DF_FP_PM_P); | 329 | write_fp(par, FP_PM, temp | FP_PM_P); |
330 | } | 330 | } |
331 | } | 331 | } |
332 | 332 | ||
@@ -357,7 +357,7 @@ void lx_set_mode(struct fb_info *info) | |||
357 | int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; | 357 | int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; |
358 | 358 | ||
359 | /* Unlock the DC registers */ | 359 | /* Unlock the DC registers */ |
360 | write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE); | 360 | write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); |
361 | 361 | ||
362 | lx_graphics_disable(info); | 362 | lx_graphics_disable(info); |
363 | 363 | ||
@@ -384,45 +384,45 @@ void lx_set_mode(struct fb_info *info) | |||
384 | /* Clear the various buffers */ | 384 | /* Clear the various buffers */ |
385 | /* FIXME: Adjust for panning here */ | 385 | /* FIXME: Adjust for panning here */ |
386 | 386 | ||
387 | write_dc(par, DC_FB_START, 0); | 387 | write_dc(par, DC_FB_ST_OFFSET, 0); |
388 | write_dc(par, DC_CB_START, 0); | 388 | write_dc(par, DC_CB_ST_OFFSET, 0); |
389 | write_dc(par, DC_CURSOR_START, 0); | 389 | write_dc(par, DC_CURS_ST_OFFSET, 0); |
390 | 390 | ||
391 | /* FIXME: Add support for interlacing */ | 391 | /* FIXME: Add support for interlacing */ |
392 | /* FIXME: Add support for scaling */ | 392 | /* FIXME: Add support for scaling */ |
393 | 393 | ||
394 | val = read_dc(par, DC_GENLCK_CTRL); | 394 | val = read_dc(par, DC_GENLK_CTL); |
395 | val &= ~(DC_GC_ALPHA_FLICK_ENABLE | | 395 | val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN | |
396 | DC_GC_FLICKER_FILTER_ENABLE | DC_GC_FLICKER_FILTER_MASK); | 396 | DC_GENLK_CTL_FLICK_SEL_MASK); |
397 | 397 | ||
398 | /* Default scaling params */ | 398 | /* Default scaling params */ |
399 | 399 | ||
400 | write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000); | 400 | write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000); |
401 | write_dc(par, DC_IRQ_FILT_CTL, 0); | 401 | write_dc(par, DC_IRQ_FILT_CTL, 0); |
402 | write_dc(par, DC_GENLCK_CTRL, val); | 402 | write_dc(par, DC_GENLK_CTL, val); |
403 | 403 | ||
404 | /* FIXME: Support compression */ | 404 | /* FIXME: Support compression */ |
405 | 405 | ||
406 | if (info->fix.line_length > 4096) | 406 | if (info->fix.line_length > 4096) |
407 | dv = DC_DV_LINE_SIZE_8192; | 407 | dv = DC_DV_CTL_DV_LINE_SIZE_8K; |
408 | else if (info->fix.line_length > 2048) | 408 | else if (info->fix.line_length > 2048) |
409 | dv = DC_DV_LINE_SIZE_4096; | 409 | dv = DC_DV_CTL_DV_LINE_SIZE_4K; |
410 | else if (info->fix.line_length > 1024) | 410 | else if (info->fix.line_length > 1024) |
411 | dv = DC_DV_LINE_SIZE_2048; | 411 | dv = DC_DV_CTL_DV_LINE_SIZE_2K; |
412 | else | 412 | else |
413 | dv = DC_DV_LINE_SIZE_1024; | 413 | dv = DC_DV_CTL_DV_LINE_SIZE_1K; |
414 | 414 | ||
415 | max = info->fix.line_length * info->var.yres; | 415 | max = info->fix.line_length * info->var.yres; |
416 | max = (max + 0x3FF) & 0xFFFFFC00; | 416 | max = (max + 0x3FF) & 0xFFFFFC00; |
417 | 417 | ||
418 | write_dc(par, DC_DV_TOP, max | DC_DV_TOP_ENABLE); | 418 | write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN); |
419 | 419 | ||
420 | val = read_dc(par, DC_DV_CTL) & ~DC_DV_LINE_SIZE_MASK; | 420 | val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE; |
421 | write_dc(par, DC_DV_CTL, val | dv); | 421 | write_dc(par, DC_DV_CTL, val | dv); |
422 | 422 | ||
423 | size = info->var.xres * (info->var.bits_per_pixel >> 3); | 423 | size = info->var.xres * (info->var.bits_per_pixel >> 3); |
424 | 424 | ||
425 | write_dc(par, DC_GRAPHICS_PITCH, info->fix.line_length >> 3); | 425 | write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); |
426 | write_dc(par, DC_LINE_SIZE, (size + 7) >> 3); | 426 | write_dc(par, DC_LINE_SIZE, (size + 7) >> 3); |
427 | 427 | ||
428 | /* Set default watermark values */ | 428 | /* Set default watermark values */ |
@@ -435,32 +435,33 @@ void lx_set_mode(struct fb_info *info) | |||
435 | msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI; | 435 | msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI; |
436 | wrmsrl(MSR_LX_SPARE_MSR, msrval); | 436 | wrmsrl(MSR_LX_SPARE_MSR, msrval); |
437 | 437 | ||
438 | gcfg = DC_GCFG_DFLE; /* Display fifo enable */ | 438 | gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */ |
439 | gcfg |= 0xB600; /* Set default priority */ | 439 | gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */ |
440 | gcfg |= DC_GCFG_FDTY; /* Set the frame dirty mode */ | 440 | (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT); |
441 | gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */ | ||
441 | 442 | ||
442 | dcfg = DC_DCFG_VDEN; /* Enable video data */ | 443 | dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ |
443 | dcfg |= DC_DCFG_GDEN; /* Enable graphics */ | 444 | dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ |
444 | dcfg |= DC_DCFG_TGEN; /* Turn on the timing generator */ | 445 | dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ |
445 | dcfg |= DC_DCFG_TRUP; /* Update timings immediately */ | 446 | dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ |
446 | dcfg |= DC_DCFG_PALB; /* Palette bypass in > 8 bpp modes */ | 447 | dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ |
447 | dcfg |= DC_DCFG_VISL; | 448 | dcfg |= DC_DISPLAY_CFG_VISL; |
448 | dcfg |= DC_DCFG_DCEN; /* Always center the display */ | 449 | dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ |
449 | 450 | ||
450 | /* Set the current BPP mode */ | 451 | /* Set the current BPP mode */ |
451 | 452 | ||
452 | switch (info->var.bits_per_pixel) { | 453 | switch (info->var.bits_per_pixel) { |
453 | case 8: | 454 | case 8: |
454 | dcfg |= DC_DCFG_DISP_MODE_8BPP; | 455 | dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; |
455 | break; | 456 | break; |
456 | 457 | ||
457 | case 16: | 458 | case 16: |
458 | dcfg |= DC_DCFG_DISP_MODE_16BPP | DC_DCFG_16BPP; | 459 | dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; |
459 | break; | 460 | break; |
460 | 461 | ||
461 | case 32: | 462 | case 32: |
462 | case 24: | 463 | case 24: |
463 | dcfg |= DC_DCFG_DISP_MODE_24BPP; | 464 | dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; |
464 | break; | 465 | break; |
465 | } | 466 | } |
466 | 467 | ||
@@ -504,7 +505,7 @@ void lx_set_mode(struct fb_info *info) | |||
504 | write_dc(par, DC_GENERAL_CFG, gcfg); | 505 | write_dc(par, DC_GENERAL_CFG, gcfg); |
505 | 506 | ||
506 | /* Lock the DC registers */ | 507 | /* Lock the DC registers */ |
507 | write_dc(par, DC_UNLOCK, 0); | 508 | write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); |
508 | } | 509 | } |
509 | 510 | ||
510 | void lx_set_palette_reg(struct fb_info *info, unsigned regno, | 511 | void lx_set_palette_reg(struct fb_info *info, unsigned regno, |
@@ -550,26 +551,25 @@ int lx_blank_display(struct fb_info *info, int blank_mode) | |||
550 | return -EINVAL; | 551 | return -EINVAL; |
551 | } | 552 | } |
552 | 553 | ||
553 | dcfg = read_vp(par, DF_DISPLAY_CFG); | 554 | dcfg = read_vp(par, VP_DCFG); |
554 | dcfg &= ~(DF_DCFG_DAC_BL_EN | 555 | dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN); |
555 | | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN); | ||
556 | if (!blank) | 556 | if (!blank) |
557 | dcfg |= DF_DCFG_DAC_BL_EN; | 557 | dcfg |= VP_DCFG_DAC_BL_EN; |
558 | if (hsync) | 558 | if (hsync) |
559 | dcfg |= DF_DCFG_HSYNC_EN; | 559 | dcfg |= VP_DCFG_HSYNC_EN; |
560 | if (vsync) | 560 | if (vsync) |
561 | dcfg |= DF_DCFG_VSYNC_EN; | 561 | dcfg |= VP_DCFG_VSYNC_EN; |
562 | write_vp(par, DF_DISPLAY_CFG, dcfg); | 562 | write_vp(par, VP_DCFG, dcfg); |
563 | 563 | ||
564 | /* Power on/off flat panel */ | 564 | /* Power on/off flat panel */ |
565 | 565 | ||
566 | if (par->output & OUTPUT_PANEL) { | 566 | if (par->output & OUTPUT_PANEL) { |
567 | fp_pm = read_fp(par, DF_FP_PM); | 567 | fp_pm = read_fp(par, FP_PM); |
568 | if (blank_mode == FB_BLANK_POWERDOWN) | 568 | if (blank_mode == FB_BLANK_POWERDOWN) |
569 | fp_pm &= ~DF_FP_PM_P; | 569 | fp_pm &= ~FP_PM_P; |
570 | else | 570 | else |
571 | fp_pm |= DF_FP_PM_P; | 571 | fp_pm |= FP_PM_P; |
572 | write_fp(par, DF_FP_PM, fp_pm); | 572 | write_fp(par, FP_PM, fp_pm); |
573 | } | 573 | } |
574 | 574 | ||
575 | return 0; | 575 | return 0; |