drm: backmerge tag 'v3.17-rc5' into drm-next

This is requested to get the fixes for intel and radeon into the
same tree for future development work.

i915_display.c: fix missing dev_priv conflict.

4 files changed, 23 insertions, 10 deletions

diff --git a/drivers/video/fbdev/amba-clcd.c b/drivers/video/fbdev/amba-clcd.c
index beadd3edaa17..6ad23bd3523a 100644
--- a/drivers/video/fbdev/amba-clcd.c
+++ b/drivers/video/fbdev/amba-clcd.c
@@ -24,6 +24,7 @@
 #include <linux/list.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/hardirq.h>
 #include <linux/dma-mapping.h>
@@ -638,9 +639,7 @@ static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0)
                 if (g0 != panels[i].g0)
                         continue;
                 if (r0 == panels[i].r0 && b0 == panels[i].b0)
-                        fb->panel->caps = panels[i].caps & CLCD_CAP_RGB;
-                if (r0 == panels[i].b0 && b0 == panels[i].r0)
-                        fb->panel->caps = panels[i].caps & CLCD_CAP_BGR;
+                        fb->panel->caps = panels[i].caps;
         }
 
         return fb->panel->caps ? 0 : -EINVAL;
@@ -650,6 +649,7 @@ static int clcdfb_of_init_display(struct clcd_fb *fb)
 {
         struct device_node *endpoint;
         int err;
+        unsigned int bpp;
         u32 max_bandwidth;
         u32 tft_r0b0g0[3];
 
@@ -667,11 +667,22 @@ static int clcdfb_of_init_display(struct clcd_fb *fb)
 
         err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth",
                         &max_bandwidth);
-        if (!err)
-                fb->panel->bpp = 8 * max_bandwidth / (fb->panel->mode.xres *
-                                fb->panel->mode.yres * fb->panel->mode.refresh);
-        else
-                fb->panel->bpp = 32;
+        if (!err) {
+                /*
+                 * max_bandwidth is in bytes per second and pixclock in
+                 * pico-seconds, so the maximum allowed bits per pixel is
+                 *   8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
+                 * Rearrange this calculation to avoid overflow and then ensure
+                 * result is a valid format.
+                 */
+                bpp = max_bandwidth / (1000 / 8)
+                        / PICOS2KHZ(fb->panel->mode.pixclock);
+                bpp = rounddown_pow_of_two(bpp);
+                if (bpp > 32)
+                        bpp = 32;
+        } else
+                bpp = 32;
+        fb->panel->bpp = bpp;
 
 #ifdef CONFIG_CPU_BIG_ENDIAN
         fb->panel->cntl |= CNTL_BEBO;
diff --git a/drivers/video/fbdev/atmel_lcdfb.c b/drivers/video/fbdev/atmel_lcdfb.c
index 92640d46770a..1d8bdb92939b 100644
--- a/drivers/video/fbdev/atmel_lcdfb.c
+++ b/drivers/video/fbdev/atmel_lcdfb.c
@@ -1102,12 +1102,14 @@ static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo)
         timings = of_get_display_timings(display_np);
         if (!timings) {
                 dev_err(dev, "failed to get display timings\n");
+                ret = -EINVAL;
                 goto put_display_node;
         }
 
         timings_np = of_find_node_by_name(display_np, "display-timings");
         if (!timings_np) {
                 dev_err(dev, "failed to find display-timings node\n");
+                ret = -ENODEV;
                 goto put_display_node;
         }
 
diff --git a/drivers/video/fbdev/chipsfb.c b/drivers/video/fbdev/chipsfb.c
index 206a66b61072..59abdc6a97f6 100644
--- a/drivers/video/fbdev/chipsfb.c
+++ b/drivers/video/fbdev/chipsfb.c
@@ -273,7 +273,7 @@ static struct chips_init_reg chips_init_xr[] = {
         { 0xa8, 0x00 }
 };
 
-static void __init chips_hw_init(void)
+static void chips_hw_init(void)
 {
         int i;
 
diff --git a/drivers/video/fbdev/da8xx-fb.c b/drivers/video/fbdev/da8xx-fb.c
index 788f6b37fce7..10c876c95772 100644
--- a/drivers/video/fbdev/da8xx-fb.c
+++ b/drivers/video/fbdev/da8xx-fb.c
@@ -419,7 +419,7 @@ static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 {
         u32 reg;
 
-        reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
+        reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
         reg |= (((back_porch-1) & 0xff) << 24)
             | (((front_porch-1) & 0xff) << 16)
             | (((pulse_width-1) & 0x3f) << 10);