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authorKrzysztof Helt <krzysztof.h1@wp.pl>2007-10-16 04:29:08 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-16 12:43:18 -0400
commit8503df65976d0f845f49e8debff55c031635754e (patch)
tree8c593d909f1325da9327a207bb398eb7ef5264a6 /drivers/video/cirrusfb.c
parente7076389f48128b00dd3f33767fb60bd3f5a06a8 (diff)
cirrusfb: checkpatch.pl cleanup
This patch fixes over 850 errors and warnings pointed out by the checkpatch.pl script. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/cirrusfb.c')
-rw-r--r--drivers/video/cirrusfb.c1788
1 files changed, 983 insertions, 805 deletions
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index 8269d704ab2a..0b9fe74630f1 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c
@@ -59,7 +59,7 @@
59#endif 59#endif
60#ifdef CONFIG_PPC_PREP 60#ifdef CONFIG_PPC_PREP
61#include <asm/machdep.h> 61#include <asm/machdep.h>
62#define isPReP (machine_is(prep)) 62#define isPReP machine_is(prep)
63#else 63#else
64#define isPReP 0 64#define isPReP 0
65#endif 65#endif
@@ -67,7 +67,6 @@
67#include "video/vga.h" 67#include "video/vga.h"
68#include "video/cirrus.h" 68#include "video/cirrus.h"
69 69
70
71/***************************************************************** 70/*****************************************************************
72 * 71 *
73 * debugging and utility macros 72 * debugging and utility macros
@@ -82,7 +81,8 @@
82 81
83/* debug output */ 82/* debug output */
84#ifdef CIRRUSFB_DEBUG 83#ifdef CIRRUSFB_DEBUG
85#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args) 84#define DPRINTK(fmt, args...) \
85 printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
86#else 86#else
87#define DPRINTK(fmt, args...) 87#define DPRINTK(fmt, args...)
88#endif 88#endif
@@ -90,20 +90,19 @@
90/* debugging assertions */ 90/* debugging assertions */
91#ifndef CIRRUSFB_NDEBUG 91#ifndef CIRRUSFB_NDEBUG
92#define assert(expr) \ 92#define assert(expr) \
93 if(!(expr)) { \ 93 if (!(expr)) { \
94 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 94 printk("Assertion failed! %s,%s,%s,line=%d\n", \
95 #expr,__FILE__,__FUNCTION__,__LINE__); \ 95 #expr, __FILE__, __FUNCTION__, __LINE__); \
96 } 96 }
97#else 97#else
98#define assert(expr) 98#define assert(expr)
99#endif 99#endif
100 100
101#define MB_ (1024*1024) 101#define MB_ (1024 * 1024)
102#define KB_ (1024) 102#define KB_ (1024)
103 103
104#define MAX_NUM_BOARDS 7 104#define MAX_NUM_BOARDS 7
105 105
106
107/***************************************************************** 106/*****************************************************************
108 * 107 *
109 * chipset information 108 * chipset information
@@ -123,7 +122,6 @@ typedef enum {
123 BT_LAGUNA, /* GD546x */ 122 BT_LAGUNA, /* GD546x */
124} cirrusfb_board_t; 123} cirrusfb_board_t;
125 124
126
127/* 125/*
128 * per-board-type information, used for enumerating and abstracting 126 * per-board-type information, used for enumerating and abstracting
129 * chip-specific information 127 * chip-specific information
@@ -139,7 +137,8 @@ static const struct cirrusfb_board_info_rec {
139 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */ 137 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
140 bool init_sr07 : 1; /* init SR07 during init_vgachip() */ 138 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
141 bool init_sr1f : 1; /* write SR1F during init_vgachip() */ 139 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
142 bool scrn_start_bit19 : 1; /* construct bit 19 of screen start address */ 140 /* construct bit 19 of screen start address */
141 bool scrn_start_bit19 : 1;
143 142
144 /* initial SR07 value, then for each mode */ 143 /* initial SR07 value, then for each mode */
145 unsigned char sr07; 144 unsigned char sr07;
@@ -261,30 +260,28 @@ static const struct cirrusfb_board_info_rec {
261 } 260 }
262}; 261};
263 262
264
265#ifdef CONFIG_PCI 263#ifdef CONFIG_PCI
266#define CHIP(id, btype) \ 264#define CHIP(id, btype) \
267 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) } 265 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
268 266
269static struct pci_device_id cirrusfb_pci_table[] = { 267static struct pci_device_id cirrusfb_pci_table[] = {
270 CHIP( PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE ), 268 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
271 CHIP( PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE ), 269 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
272 CHIP( PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE ), 270 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
273 CHIP( PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE ), /* GD-5440 is same id */ 271 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
274 CHIP( PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE ), 272 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
275 CHIP( PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE ), 273 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
276 CHIP( PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480 ), /* MacPicasso likely */ 274 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
277 CHIP( PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4 ), /* Picasso 4 is 5446 */ 275 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
278 CHIP( PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA ), /* CL Laguna */ 276 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
279 CHIP( PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA ), /* CL Laguna 3D */ 277 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
280 CHIP( PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA ), /* CL Laguna 3DA*/ 278 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
281 { 0, } 279 { 0, }
282}; 280};
283MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table); 281MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
284#undef CHIP 282#undef CHIP
285#endif /* CONFIG_PCI */ 283#endif /* CONFIG_PCI */
286 284
287
288#ifdef CONFIG_ZORRO 285#ifdef CONFIG_ZORRO
289static const struct zorro_device_id cirrusfb_zorro_table[] = { 286static const struct zorro_device_id cirrusfb_zorro_table[] = {
290 { 287 {
@@ -294,7 +291,7 @@ static const struct zorro_device_id cirrusfb_zorro_table[] = {
294 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM, 291 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
295 .driver_data = BT_PICCOLO, 292 .driver_data = BT_PICCOLO,
296 }, { 293 }, {
297 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM, 294 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
298 .driver_data = BT_PICASSO, 295 .driver_data = BT_PICASSO,
299 }, { 296 }, {
300 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM, 297 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
@@ -333,7 +330,6 @@ static const struct {
333}; 330};
334#endif /* CONFIG_ZORRO */ 331#endif /* CONFIG_ZORRO */
335 332
336
337struct cirrusfb_regs { 333struct cirrusfb_regs {
338 __u32 line_length; /* in BYTES! */ 334 __u32 line_length; /* in BYTES! */
339 __u32 visual; 335 __u32 visual;
@@ -364,17 +360,12 @@ struct cirrusfb_regs {
364 long VertBlankEnd; 360 long VertBlankEnd;
365}; 361};
366 362
367
368
369#ifdef CIRRUSFB_DEBUG 363#ifdef CIRRUSFB_DEBUG
370typedef enum { 364typedef enum {
371 CRT, 365 CRT,
372 SEQ 366 SEQ
373} cirrusfb_dbg_reg_class_t; 367} cirrusfb_dbg_reg_class_t;
374#endif /* CIRRUSFB_DEBUG */ 368#endif /* CIRRUSFB_DEBUG */
375
376
377
378 369
379/* info about board */ 370/* info about board */
380struct cirrusfb_info { 371struct cirrusfb_info {
@@ -405,9 +396,8 @@ struct cirrusfb_info {
405 void (*unmap)(struct cirrusfb_info *cinfo); 396 void (*unmap)(struct cirrusfb_info *cinfo);
406}; 397};
407 398
408
409static unsigned cirrusfb_def_mode = 1; 399static unsigned cirrusfb_def_mode = 1;
410static int noaccel = 0; 400static int noaccel;
411 401
412/* 402/*
413 * Predefined Video Modes 403 * Predefined Video Modes
@@ -441,7 +431,7 @@ static const struct {
441 .lower_margin = 8, 431 .lower_margin = 8,
442 .hsync_len = 96, 432 .hsync_len = 96,
443 .vsync_len = 4, 433 .vsync_len = 4,
444 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 434 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
445 .vmode = FB_VMODE_NONINTERLACED 435 .vmode = FB_VMODE_NONINTERLACED
446 } 436 }
447 }, { 437 }, {
@@ -502,27 +492,29 @@ static const struct {
502/****************************************************************************/ 492/****************************************************************************/
503/**** BEGIN PROTOTYPES ******************************************************/ 493/**** BEGIN PROTOTYPES ******************************************************/
504 494
505
506/*--- Interface used by the world ------------------------------------------*/ 495/*--- Interface used by the world ------------------------------------------*/
507static int cirrusfb_init (void); 496static int cirrusfb_init(void);
508#ifndef MODULE 497#ifndef MODULE
509static int cirrusfb_setup (char *options); 498static int cirrusfb_setup(char *options);
510#endif 499#endif
511 500
512static int cirrusfb_open (struct fb_info *info, int user); 501static int cirrusfb_open(struct fb_info *info, int user);
513static int cirrusfb_release (struct fb_info *info, int user); 502static int cirrusfb_release(struct fb_info *info, int user);
514static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green, 503static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
515 unsigned blue, unsigned transp, 504 unsigned blue, unsigned transp,
516 struct fb_info *info); 505 struct fb_info *info);
517static int cirrusfb_check_var (struct fb_var_screeninfo *var, 506static int cirrusfb_check_var(struct fb_var_screeninfo *var,
518 struct fb_info *info); 507 struct fb_info *info);
519static int cirrusfb_set_par (struct fb_info *info); 508static int cirrusfb_set_par(struct fb_info *info);
520static int cirrusfb_pan_display (struct fb_var_screeninfo *var, 509static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
521 struct fb_info *info); 510 struct fb_info *info);
522static int cirrusfb_blank (int blank_mode, struct fb_info *info); 511static int cirrusfb_blank(int blank_mode, struct fb_info *info);
523static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region); 512static void cirrusfb_fillrect(struct fb_info *info,
524static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area); 513 const struct fb_fillrect *region);
525static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image); 514static void cirrusfb_copyarea(struct fb_info *info,
515 const struct fb_copyarea *area);
516static void cirrusfb_imageblit(struct fb_info *info,
517 const struct fb_image *image);
526 518
527/* function table of the above functions */ 519/* function table of the above functions */
528static struct fb_ops cirrusfb_ops = { 520static struct fb_ops cirrusfb_ops = {
@@ -540,68 +532,68 @@ static struct fb_ops cirrusfb_ops = {
540}; 532};
541 533
542/*--- Hardware Specific Routines -------------------------------------------*/ 534/*--- Hardware Specific Routines -------------------------------------------*/
543static int cirrusfb_decode_var (const struct fb_var_screeninfo *var, 535static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
544 struct cirrusfb_regs *regs, 536 struct cirrusfb_regs *regs,
545 const struct fb_info *info); 537 const struct fb_info *info);
546/*--- Internal routines ----------------------------------------------------*/ 538/*--- Internal routines ----------------------------------------------------*/
547static void init_vgachip (struct cirrusfb_info *cinfo); 539static void init_vgachip(struct cirrusfb_info *cinfo);
548static void switch_monitor (struct cirrusfb_info *cinfo, int on); 540static void switch_monitor(struct cirrusfb_info *cinfo, int on);
549static void WGen (const struct cirrusfb_info *cinfo, 541static void WGen(const struct cirrusfb_info *cinfo,
550 int regnum, unsigned char val); 542 int regnum, unsigned char val);
551static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum); 543static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
552static void AttrOn (const struct cirrusfb_info *cinfo); 544static void AttrOn(const struct cirrusfb_info *cinfo);
553static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val); 545static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
554static void WSFR (struct cirrusfb_info *cinfo, unsigned char val); 546static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
555static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val); 547static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
556static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red, 548static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
557 unsigned char green, 549 unsigned char red, unsigned char green, unsigned char blue);
558 unsigned char blue);
559#if 0 550#if 0
560static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red, 551static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
561 unsigned char *green, 552 unsigned char *red, unsigned char *green,
562 unsigned char *blue); 553 unsigned char *blue);
563#endif 554#endif
564static void cirrusfb_WaitBLT (u8 __iomem *regbase); 555static void cirrusfb_WaitBLT(u8 __iomem *regbase);
565static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel, 556static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
566 u_short curx, u_short cury, 557 u_short curx, u_short cury,
567 u_short destx, u_short desty, 558 u_short destx, u_short desty,
568 u_short width, u_short height, 559 u_short width, u_short height,
569 u_short line_length); 560 u_short line_length);
570static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel, 561static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
571 u_short x, u_short y, 562 u_short x, u_short y,
572 u_short width, u_short height, 563 u_short width, u_short height,
573 u_char color, u_short line_length); 564 u_char color, u_short line_length);
574 565
575static void bestclock (long freq, long *best, 566static void bestclock(long freq, long *best,
576 long *nom, long *den, 567 long *nom, long *den,
577 long *div, long maxfreq); 568 long *div, long maxfreq);
578 569
579#ifdef CIRRUSFB_DEBUG 570#ifdef CIRRUSFB_DEBUG
580static void cirrusfb_dump (void); 571static void cirrusfb_dump(void);
581static void cirrusfb_dbg_reg_dump (caddr_t regbase); 572static void cirrusfb_dbg_reg_dump(caddr_t regbase);
582static void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...); 573static void cirrusfb_dbg_print_regs(caddr_t regbase,
583static void cirrusfb_dbg_print_byte (const char *name, unsigned char val); 574 cirrusfb_dbg_reg_class_t reg_class, ...);
575static void cirrusfb_dbg_print_byte(const char *name, unsigned char val);
584#endif /* CIRRUSFB_DEBUG */ 576#endif /* CIRRUSFB_DEBUG */
585 577
586/*** END PROTOTYPES ********************************************************/ 578/*** END PROTOTYPES ********************************************************/
587/*****************************************************************************/ 579/*****************************************************************************/
588/*** BEGIN Interface Used by the World ***************************************/ 580/*** BEGIN Interface Used by the World ***************************************/
589 581
590static int opencount = 0; 582static int opencount;
591 583
592/*--- Open /dev/fbx ---------------------------------------------------------*/ 584/*--- Open /dev/fbx ---------------------------------------------------------*/
593static int cirrusfb_open (struct fb_info *info, int user) 585static int cirrusfb_open(struct fb_info *info, int user)
594{ 586{
595 if (opencount++ == 0) 587 if (opencount++ == 0)
596 switch_monitor (info->par, 1); 588 switch_monitor(info->par, 1);
597 return 0; 589 return 0;
598} 590}
599 591
600/*--- Close /dev/fbx --------------------------------------------------------*/ 592/*--- Close /dev/fbx --------------------------------------------------------*/
601static int cirrusfb_release (struct fb_info *info, int user) 593static int cirrusfb_release(struct fb_info *info, int user)
602{ 594{
603 if (--opencount == 0) 595 if (--opencount == 0)
604 switch_monitor (info->par, 0); 596 switch_monitor(info->par, 0);
605 return 0; 597 return 0;
606} 598}
607 599
@@ -610,11 +602,11 @@ static int cirrusfb_release (struct fb_info *info, int user)
610/**** BEGIN Hardware specific Routines **************************************/ 602/**** BEGIN Hardware specific Routines **************************************/
611 603
612/* Get a good MCLK value */ 604/* Get a good MCLK value */
613static long cirrusfb_get_mclk (long freq, int bpp, long *div) 605static long cirrusfb_get_mclk(long freq, int bpp, long *div)
614{ 606{
615 long mclk; 607 long mclk;
616 608
617 assert (div != NULL); 609 assert(div != NULL);
618 610
619 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz. 611 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
620 * Assume a 64-bit data path for now. The formula is: 612 * Assume a 64-bit data path for now. The formula is:
@@ -624,23 +616,23 @@ static long cirrusfb_get_mclk (long freq, int bpp, long *div)
624 mclk = (mclk * 12) / 10; 616 mclk = (mclk * 12) / 10;
625 if (mclk < 50000) 617 if (mclk < 50000)
626 mclk = 50000; 618 mclk = 50000;
627 DPRINTK ("Use MCLK of %ld kHz\n", mclk); 619 DPRINTK("Use MCLK of %ld kHz\n", mclk);
628 620
629 /* Calculate value for SR1F. Multiply by 2 so we can round up. */ 621 /* Calculate value for SR1F. Multiply by 2 so we can round up. */
630 mclk = ((mclk * 16) / 14318); 622 mclk = ((mclk * 16) / 14318);
631 mclk = (mclk + 1) / 2; 623 mclk = (mclk + 1) / 2;
632 DPRINTK ("Set SR1F[5:0] to 0x%lx\n", mclk); 624 DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
633 625
634 /* Determine if we should use MCLK instead of VCLK, and if so, what we 626 /* Determine if we should use MCLK instead of VCLK, and if so, what we
635 * should divide it by to get VCLK */ 627 * should divide it by to get VCLK */
636 switch (freq) { 628 switch (freq) {
637 case 24751 ... 25249: 629 case 24751 ... 25249:
638 *div = 2; 630 *div = 2;
639 DPRINTK ("Using VCLK = MCLK/2\n"); 631 DPRINTK("Using VCLK = MCLK/2\n");
640 break; 632 break;
641 case 49501 ... 50499: 633 case 49501 ... 50499:
642 *div = 1; 634 *div = 1;
643 DPRINTK ("Using VCLK = MCLK\n"); 635 DPRINTK("Using VCLK = MCLK\n");
644 break; 636 break;
645 default: 637 default:
646 *div = 0; 638 *div = 0;
@@ -691,37 +683,42 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
691 den = 1; 683 den = 1;
692 break; /* 4 bytes per pixel */ 684 break; /* 4 bytes per pixel */
693 default: 685 default:
694 printk ("cirrusfb: mode %dx%dx%d rejected...color depth not supported.\n", 686 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
687 "color depth not supported.\n",
695 var->xres, var->yres, var->bits_per_pixel); 688 var->xres, var->yres, var->bits_per_pixel);
696 DPRINTK ("EXIT - EINVAL error\n"); 689 DPRINTK("EXIT - EINVAL error\n");
697 return -EINVAL; 690 return -EINVAL;
698 } 691 }
699 692
700 if (var->xres * nom / den * var->yres > cinfo->size) { 693 if (var->xres * nom / den * var->yres > cinfo->size) {
701 printk ("cirrusfb: mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", 694 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
695 "resolution too high to fit into video memory!\n",
702 var->xres, var->yres, var->bits_per_pixel); 696 var->xres, var->yres, var->bits_per_pixel);
703 DPRINTK ("EXIT - EINVAL error\n"); 697 DPRINTK("EXIT - EINVAL error\n");
704 return -EINVAL; 698 return -EINVAL;
705 } 699 }
706 700
707 /* use highest possible virtual resolution */ 701 /* use highest possible virtual resolution */
708 if (var->xres_virtual == -1 && 702 if (var->xres_virtual == -1 &&
709 var->yres_virtual == -1) { 703 var->yres_virtual == -1) {
710 printk ("cirrusfb: using maximum available virtual resolution\n"); 704 printk(KERN_INFO
705 "cirrusfb: using maximum available virtual resolution\n");
711 for (i = 0; modes[i].xres != -1; i++) { 706 for (i = 0; modes[i].xres != -1; i++) {
712 if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2) 707 if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2)
713 break; 708 break;
714 } 709 }
715 if (modes[i].xres == -1) { 710 if (modes[i].xres == -1) {
716 printk ("cirrusfb: could not find a virtual resolution that fits into video memory!!\n"); 711 printk(KERN_ERR "cirrusfb: could not find a virtual "
717 DPRINTK ("EXIT - EINVAL error\n"); 712 "resolution that fits into video memory!!\n");
713 DPRINTK("EXIT - EINVAL error\n");
718 return -EINVAL; 714 return -EINVAL;
719 } 715 }
720 var->xres_virtual = modes[i].xres; 716 var->xres_virtual = modes[i].xres;
721 var->yres_virtual = modes[i].yres; 717 var->yres_virtual = modes[i].yres;
722 718
723 printk ("cirrusfb: virtual resolution set to maximum of %dx%d\n", 719 printk(KERN_INFO "cirrusfb: virtual resolution set to "
724 var->xres_virtual, var->yres_virtual); 720 "maximum of %dx%d\n", var->xres_virtual,
721 var->yres_virtual);
725 } 722 }
726 723
727 if (var->xres_virtual < var->xres) 724 if (var->xres_virtual < var->xres)
@@ -760,7 +757,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
760 break; 757 break;
761 758
762 case 16: 759 case 16:
763 if(isPReP) { 760 if (isPReP) {
764 var->red.offset = 2; 761 var->red.offset = 2;
765 var->green.offset = -3; 762 var->green.offset = -3;
766 var->blue.offset = 8; 763 var->blue.offset = 8;
@@ -775,7 +772,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
775 break; 772 break;
776 773
777 case 24: 774 case 24:
778 if(isPReP) { 775 if (isPReP) {
779 var->red.offset = 8; 776 var->red.offset = 8;
780 var->green.offset = 16; 777 var->green.offset = 16;
781 var->blue.offset = 24; 778 var->blue.offset = 24;
@@ -790,7 +787,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
790 break; 787 break;
791 788
792 case 32: 789 case 32:
793 if(isPReP) { 790 if (isPReP) {
794 var->red.offset = 8; 791 var->red.offset = 8;
795 var->green.offset = 16; 792 var->green.offset = 16;
796 var->blue.offset = 24; 793 var->blue.offset = 24;
@@ -825,15 +822,16 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
825 yres = (yres + 1) / 2; 822 yres = (yres + 1) / 2;
826 823
827 if (yres >= 1280) { 824 if (yres >= 1280) {
828 printk (KERN_WARNING "cirrusfb: ERROR: VerticalTotal >= 1280; special treatment required! (TODO)\n"); 825 printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280; "
829 DPRINTK ("EXIT - EINVAL error\n"); 826 "special treatment required! (TODO)\n");
827 DPRINTK("EXIT - EINVAL error\n");
830 return -EINVAL; 828 return -EINVAL;
831 } 829 }
832 830
833 return 0; 831 return 0;
834} 832}
835 833
836static int cirrusfb_decode_var (const struct fb_var_screeninfo *var, 834static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
837 struct cirrusfb_regs *regs, 835 struct cirrusfb_regs *regs,
838 const struct fb_info *info) 836 const struct fb_info *info)
839{ 837{
@@ -844,7 +842,7 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
844 int xres, hfront, hsync, hback; 842 int xres, hfront, hsync, hback;
845 int yres, vfront, vsync, vback; 843 int yres, vfront, vsync, vback;
846 844
847 switch(var->bits_per_pixel) { 845 switch (var->bits_per_pixel) {
848 case 1: 846 case 1:
849 regs->line_length = var->xres_virtual / 8; 847 regs->line_length = var->xres_virtual / 8;
850 regs->visual = FB_VISUAL_MONO10; 848 regs->visual = FB_VISUAL_MONO10;
@@ -887,7 +885,7 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
887 /* convert from ps to kHz */ 885 /* convert from ps to kHz */
888 freq = 1000000000 / var->pixclock; 886 freq = 1000000000 / var->pixclock;
889 887
890 DPRINTK ("desired pixclock: %ld kHz\n", freq); 888 DPRINTK("desired pixclock: %ld kHz\n", freq);
891 889
892 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx]; 890 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
893 regs->multiplexing = 0; 891 regs->multiplexing = 0;
@@ -902,8 +900,9 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
902 break; 900 break;
903 901
904 default: 902 default:
905 printk (KERN_WARNING "cirrusfb: ERROR: Frequency greater than maxclock (%ld kHz)\n", maxclock); 903 printk(KERN_ERR "cirrusfb: Frequency greater "
906 DPRINTK ("EXIT - return -EINVAL\n"); 904 "than maxclock (%ld kHz)\n", maxclock);
905 DPRINTK("EXIT - return -EINVAL\n");
907 return -EINVAL; 906 return -EINVAL;
908 } 907 }
909 } 908 }
@@ -914,14 +913,16 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
914 case 16: 913 case 16:
915 case 32: 914 case 32:
916 if (regs->HorizRes <= 800) 915 if (regs->HorizRes <= 800)
917 freq /= 2; /* Xbh has this type of clock for 32-bit */ 916 /* Xbh has this type of clock for 32-bit */
917 freq /= 2;
918 break; 918 break;
919 } 919 }
920#endif 920#endif
921 921
922 bestclock (freq, &regs->freq, &regs->nom, &regs->den, &regs->div, 922 bestclock(freq, &regs->freq, &regs->nom, &regs->den, &regs->div,
923 maxclock); 923 maxclock);
924 regs->mclk = cirrusfb_get_mclk (freq, var->bits_per_pixel, &regs->divMCLK); 924 regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
925 &regs->divMCLK);
925 926
926 xres = var->xres; 927 xres = var->xres;
927 hfront = var->right_margin; 928 hfront = var->right_margin;
@@ -948,7 +949,8 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
948 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5; 949 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
949 regs->HorizDispEnd = xres / 8 - 1; 950 regs->HorizDispEnd = xres / 8 - 1;
950 regs->HorizBlankStart = xres / 8; 951 regs->HorizBlankStart = xres / 8;
951 regs->HorizBlankEnd = regs->HorizTotal + 5; /* does not count with "-5" */ 952 /* does not count with "-5" */
953 regs->HorizBlankEnd = regs->HorizTotal + 5;
952 regs->HorizSyncStart = (xres + hfront) / 8 + 1; 954 regs->HorizSyncStart = (xres + hfront) / 8 + 1;
953 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1; 955 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
954 956
@@ -976,23 +978,23 @@ static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
976 return 0; 978 return 0;
977} 979}
978 980
979 981static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
980static void cirrusfb_set_mclk (const struct cirrusfb_info *cinfo, int val, int div) 982 int div)
981{ 983{
982 assert (cinfo != NULL); 984 assert(cinfo != NULL);
983 985
984 if (div == 2) { 986 if (div == 2) {
985 /* VCLK = MCLK/2 */ 987 /* VCLK = MCLK/2 */
986 unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E); 988 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
987 vga_wseq (cinfo->regbase, CL_SEQR1E, old | 0x1); 989 vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
988 vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f)); 990 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
989 } else if (div == 1) { 991 } else if (div == 1) {
990 /* VCLK = MCLK */ 992 /* VCLK = MCLK */
991 unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E); 993 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
992 vga_wseq (cinfo->regbase, CL_SEQR1E, old & ~0x1); 994 vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
993 vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f)); 995 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
994 } else { 996 } else {
995 vga_wseq (cinfo->regbase, CL_SEQR1F, val & 0x3f); 997 vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
996 } 998 }
997} 999}
998 1000
@@ -1001,7 +1003,7 @@ static void cirrusfb_set_mclk (const struct cirrusfb_info *cinfo, int val, int d
1001 1003
1002 actually writes the values for a new video mode into the hardware, 1004 actually writes the values for a new video mode into the hardware,
1003**************************************************************************/ 1005**************************************************************************/
1004static int cirrusfb_set_par_foo (struct fb_info *info) 1006static int cirrusfb_set_par_foo(struct fb_info *info)
1005{ 1007{
1006 struct cirrusfb_info *cinfo = info->par; 1008 struct cirrusfb_info *cinfo = info->par;
1007 struct fb_var_screeninfo *var = &info->var; 1009 struct fb_var_screeninfo *var = &info->var;
@@ -1011,15 +1013,15 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1011 int offset = 0, err; 1013 int offset = 0, err;
1012 const struct cirrusfb_board_info_rec *bi; 1014 const struct cirrusfb_board_info_rec *bi;
1013 1015
1014 DPRINTK ("ENTER\n"); 1016 DPRINTK("ENTER\n");
1015 DPRINTK ("Requested mode: %dx%dx%d\n", 1017 DPRINTK("Requested mode: %dx%dx%d\n",
1016 var->xres, var->yres, var->bits_per_pixel); 1018 var->xres, var->yres, var->bits_per_pixel);
1017 DPRINTK ("pixclock: %d\n", var->pixclock); 1019 DPRINTK("pixclock: %d\n", var->pixclock);
1018 1020
1019 init_vgachip (cinfo); 1021 init_vgachip(cinfo);
1020 1022
1021 err = cirrusfb_decode_var(var, &regs, info); 1023 err = cirrusfb_decode_var(var, &regs, info);
1022 if(err) { 1024 if (err) {
1023 /* should never happen */ 1025 /* should never happen */
1024 DPRINTK("mode change aborted. invalid var.\n"); 1026 DPRINTK("mode change aborted. invalid var.\n");
1025 return -EINVAL; 1027 return -EINVAL;
@@ -1027,34 +1029,35 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1027 1029
1028 bi = &cirrusfb_board_info[cinfo->btype]; 1030 bi = &cirrusfb_board_info[cinfo->btype];
1029 1031
1030
1031 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */ 1032 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
1032 vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */ 1033 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
1033 1034
1034 /* if debugging is enabled, all parameters get output before writing */ 1035 /* if debugging is enabled, all parameters get output before writing */
1035 DPRINTK ("CRT0: %ld\n", regs.HorizTotal); 1036 DPRINTK("CRT0: %ld\n", regs.HorizTotal);
1036 vga_wcrt (regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal); 1037 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
1037 1038
1038 DPRINTK ("CRT1: %ld\n", regs.HorizDispEnd); 1039 DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
1039 vga_wcrt (regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd); 1040 vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
1040 1041
1041 DPRINTK ("CRT2: %ld\n", regs.HorizBlankStart); 1042 DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
1042 vga_wcrt (regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart); 1043 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
1043 1044
1044 DPRINTK ("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32); /* + 128: Compatible read */ 1045 /* + 128: Compatible read */
1045 vga_wcrt (regbase, VGA_CRTC_H_BLANK_END, 128 + (regs.HorizBlankEnd % 32)); 1046 DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
1047 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
1048 128 + (regs.HorizBlankEnd % 32));
1046 1049
1047 DPRINTK ("CRT4: %ld\n", regs.HorizSyncStart); 1050 DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
1048 vga_wcrt (regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart); 1051 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
1049 1052
1050 tmp = regs.HorizSyncEnd % 32; 1053 tmp = regs.HorizSyncEnd % 32;
1051 if (regs.HorizBlankEnd & 32) 1054 if (regs.HorizBlankEnd & 32)
1052 tmp += 128; 1055 tmp += 128;
1053 DPRINTK ("CRT5: %d\n", tmp); 1056 DPRINTK("CRT5: %d\n", tmp);
1054 vga_wcrt (regbase, VGA_CRTC_H_SYNC_END, tmp); 1057 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
1055 1058
1056 DPRINTK ("CRT6: %ld\n", regs.VertTotal & 0xff); 1059 DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
1057 vga_wcrt (regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff)); 1060 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
1058 1061
1059 tmp = 16; /* LineCompare bit #9 */ 1062 tmp = 16; /* LineCompare bit #9 */
1060 if (regs.VertTotal & 256) 1063 if (regs.VertTotal & 256)
@@ -1071,34 +1074,34 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1071 tmp |= 64; 1074 tmp |= 64;
1072 if (regs.VertSyncStart & 512) 1075 if (regs.VertSyncStart & 512)
1073 tmp |= 128; 1076 tmp |= 128;
1074 DPRINTK ("CRT7: %d\n", tmp); 1077 DPRINTK("CRT7: %d\n", tmp);
1075 vga_wcrt (regbase, VGA_CRTC_OVERFLOW, tmp); 1078 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
1076 1079
1077 tmp = 0x40; /* LineCompare bit #8 */ 1080 tmp = 0x40; /* LineCompare bit #8 */
1078 if (regs.VertBlankStart & 512) 1081 if (regs.VertBlankStart & 512)
1079 tmp |= 0x20; 1082 tmp |= 0x20;
1080 if (var->vmode & FB_VMODE_DOUBLE) 1083 if (var->vmode & FB_VMODE_DOUBLE)
1081 tmp |= 0x80; 1084 tmp |= 0x80;
1082 DPRINTK ("CRT9: %d\n", tmp); 1085 DPRINTK("CRT9: %d\n", tmp);
1083 vga_wcrt (regbase, VGA_CRTC_MAX_SCAN, tmp); 1086 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
1084 1087
1085 DPRINTK ("CRT10: %ld\n", regs.VertSyncStart & 0xff); 1088 DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
1086 vga_wcrt (regbase, VGA_CRTC_V_SYNC_START, (regs.VertSyncStart & 0xff)); 1089 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
1087 1090
1088 DPRINTK ("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16); 1091 DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
1089 vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, (regs.VertSyncEnd % 16 + 64 + 32)); 1092 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
1090 1093
1091 DPRINTK ("CRT12: %ld\n", regs.VertDispEnd & 0xff); 1094 DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
1092 vga_wcrt (regbase, VGA_CRTC_V_DISP_END, (regs.VertDispEnd & 0xff)); 1095 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
1093 1096
1094 DPRINTK ("CRT15: %ld\n", regs.VertBlankStart & 0xff); 1097 DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
1095 vga_wcrt (regbase, VGA_CRTC_V_BLANK_START, (regs.VertBlankStart & 0xff)); 1098 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
1096 1099
1097 DPRINTK ("CRT16: %ld\n", regs.VertBlankEnd & 0xff); 1100 DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
1098 vga_wcrt (regbase, VGA_CRTC_V_BLANK_END, (regs.VertBlankEnd & 0xff)); 1101 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
1099 1102
1100 DPRINTK ("CRT18: 0xff\n"); 1103 DPRINTK("CRT18: 0xff\n");
1101 vga_wcrt (regbase, VGA_CRTC_LINE_COMPARE, 0xff); 1104 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
1102 1105
1103 tmp = 0; 1106 tmp = 0;
1104 if (var->vmode & FB_VMODE_INTERLACED) 1107 if (var->vmode & FB_VMODE_INTERLACED)
@@ -1112,57 +1115,63 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1112 if (regs.VertBlankEnd & 512) 1115 if (regs.VertBlankEnd & 512)
1113 tmp |= 128; 1116 tmp |= 128;
1114 1117
1115 DPRINTK ("CRT1a: %d\n", tmp); 1118 DPRINTK("CRT1a: %d\n", tmp);
1116 vga_wcrt (regbase, CL_CRT1A, tmp); 1119 vga_wcrt(regbase, CL_CRT1A, tmp);
1117 1120
1118 /* set VCLK0 */ 1121 /* set VCLK0 */
1119 /* hardware RefClock: 14.31818 MHz */ 1122 /* hardware RefClock: 14.31818 MHz */
1120 /* formula: VClk = (OSC * N) / (D * (1+P)) */ 1123 /* formula: VClk = (OSC * N) / (D * (1+P)) */
1121 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */ 1124 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
1122 1125
1123 vga_wseq (regbase, CL_SEQRB, regs.nom); 1126 vga_wseq(regbase, CL_SEQRB, regs.nom);
1124 tmp = regs.den << 1; 1127 tmp = regs.den << 1;
1125 if (regs.div != 0) 1128 if (regs.div != 0)
1126 tmp |= 1; 1129 tmp |= 1;
1127 1130
1131 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
1128 if ((cinfo->btype == BT_SD64) || 1132 if ((cinfo->btype == BT_SD64) ||
1129 (cinfo->btype == BT_ALPINE) || 1133 (cinfo->btype == BT_ALPINE) ||
1130 (cinfo->btype == BT_GD5480)) 1134 (cinfo->btype == BT_GD5480))
1131 tmp |= 0x80; /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */ 1135 tmp |= 0x80;
1132 1136
1133 DPRINTK ("CL_SEQR1B: %ld\n", (long) tmp); 1137 DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
1134 vga_wseq (regbase, CL_SEQR1B, tmp); 1138 vga_wseq(regbase, CL_SEQR1B, tmp);
1135 1139
1136 if (regs.VertRes >= 1024) 1140 if (regs.VertRes >= 1024)
1137 /* 1280x1024 */ 1141 /* 1280x1024 */
1138 vga_wcrt (regbase, VGA_CRTC_MODE, 0xc7); 1142 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
1139 else 1143 else
1140 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit 1144 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
1141 * address wrap, no compat. */ 1145 * address wrap, no compat. */
1142 vga_wcrt (regbase, VGA_CRTC_MODE, 0xc3); 1146 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
1143 1147
1144/* HAEH? vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */ 1148/* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
1149 * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
1145 1150
1146 /* don't know if it would hurt to also program this if no interlaced */ 1151 /* don't know if it would hurt to also program this if no interlaced */
1147 /* mode is used, but I feel better this way.. :-) */ 1152 /* mode is used, but I feel better this way.. :-) */
1148 if (var->vmode & FB_VMODE_INTERLACED) 1153 if (var->vmode & FB_VMODE_INTERLACED)
1149 vga_wcrt (regbase, VGA_CRTC_REGS, regs.HorizTotal / 2); 1154 vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
1150 else 1155 else
1151 vga_wcrt (regbase, VGA_CRTC_REGS, 0x00); /* interlace control */ 1156 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1152 1157
1153 vga_wseq (regbase, VGA_SEQ_CHARACTER_MAP, 0); 1158 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
1154 1159
1155 /* adjust horizontal/vertical sync type (low/high) */ 1160 /* adjust horizontal/vertical sync type (low/high) */
1156 tmp = 0x03; /* enable display memory & CRTC I/O address for color mode */ 1161 /* enable display memory & CRTC I/O address for color mode */
1162 tmp = 0x03;
1157 if (var->sync & FB_SYNC_HOR_HIGH_ACT) 1163 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1158 tmp |= 0x40; 1164 tmp |= 0x40;
1159 if (var->sync & FB_SYNC_VERT_HIGH_ACT) 1165 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1160 tmp |= 0x80; 1166 tmp |= 0x80;
1161 WGen (cinfo, VGA_MIS_W, tmp); 1167 WGen(cinfo, VGA_MIS_W, tmp);
1162 1168
1163 vga_wcrt (regbase, VGA_CRTC_PRESET_ROW, 0); /* Screen A Preset Row-Scan register */ 1169 /* Screen A Preset Row-Scan register */
1164 vga_wcrt (regbase, VGA_CRTC_CURSOR_START, 0); /* text cursor on and start line */ 1170 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
1165 vga_wcrt (regbase, VGA_CRTC_CURSOR_END, 31); /* text cursor end line */ 1171 /* text cursor on and start line */
1172 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
1173 /* text cursor end line */
1174 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
1166 1175
1167 /****************************************************** 1176 /******************************************************
1168 * 1177 *
@@ -1172,8 +1181,8 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1172 1181
1173 /* programming for different color depths */ 1182 /* programming for different color depths */
1174 if (var->bits_per_pixel == 1) { 1183 if (var->bits_per_pixel == 1) {
1175 DPRINTK ("cirrusfb: preparing for 1 bit deep display\n"); 1184 DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
1176 vga_wgfx (regbase, VGA_GFX_MODE, 0); /* mode register */ 1185 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
1177 1186
1178 /* SR07 */ 1187 /* SR07 */
1179 switch (cinfo->btype) { 1188 switch (cinfo->btype) {
@@ -1184,71 +1193,85 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1184 case BT_PICASSO4: 1193 case BT_PICASSO4:
1185 case BT_ALPINE: 1194 case BT_ALPINE:
1186 case BT_GD5480: 1195 case BT_GD5480:
1187 DPRINTK (" (for GD54xx)\n"); 1196 DPRINTK(" (for GD54xx)\n");
1188 vga_wseq (regbase, CL_SEQR7, 1197 vga_wseq(regbase, CL_SEQR7,
1189 regs.multiplexing ? 1198 regs.multiplexing ?
1190 bi->sr07_1bpp_mux : bi->sr07_1bpp); 1199 bi->sr07_1bpp_mux : bi->sr07_1bpp);
1191 break; 1200 break;
1192 1201
1193 case BT_LAGUNA: 1202 case BT_LAGUNA:
1194 DPRINTK (" (for GD546x)\n"); 1203 DPRINTK(" (for GD546x)\n");
1195 vga_wseq (regbase, CL_SEQR7, 1204 vga_wseq(regbase, CL_SEQR7,
1196 vga_rseq (regbase, CL_SEQR7) & ~0x01); 1205 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1197 break; 1206 break;
1198 1207
1199 default: 1208 default:
1200 printk (KERN_WARNING "cirrusfb: unknown Board\n"); 1209 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1201 break; 1210 break;
1202 } 1211 }
1203 1212
1204 /* Extended Sequencer Mode */ 1213 /* Extended Sequencer Mode */
1205 switch (cinfo->btype) { 1214 switch (cinfo->btype) {
1206 case BT_SD64: 1215 case BT_SD64:
1207 /* setting the SEQRF on SD64 is not necessary (only during init) */ 1216 /* setting the SEQRF on SD64 is not necessary
1208 DPRINTK ("(for SD64)\n"); 1217 * (only during init)
1209 vga_wseq (regbase, CL_SEQR1F, 0x1a); /* MCLK select */ 1218 */
1219 DPRINTK("(for SD64)\n");
1220 /* MCLK select */
1221 vga_wseq(regbase, CL_SEQR1F, 0x1a);
1210 break; 1222 break;
1211 1223
1212 case BT_PICCOLO: 1224 case BT_PICCOLO:
1213 DPRINTK ("(for Piccolo)\n"); 1225 DPRINTK("(for Piccolo)\n");
1214/* ### ueberall 0x22? */ 1226 /* ### ueberall 0x22? */
1215 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */ 1227 /* ##vorher 1c MCLK select */
1216 vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0 bei 1 bit? avoid FIFO underruns..? */ 1228 vga_wseq(regbase, CL_SEQR1F, 0x22);
1229 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
1230 vga_wseq(regbase, CL_SEQRF, 0xb0);
1217 break; 1231 break;
1218 1232
1219 case BT_PICASSO: 1233 case BT_PICASSO:
1220 DPRINTK ("(for Picasso)\n"); 1234 DPRINTK("(for Picasso)\n");
1221 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 22 MCLK select */ 1235 /* ##vorher 22 MCLK select */
1222 vga_wseq (regbase, CL_SEQRF, 0xd0); /* ## vorher d0 avoid FIFO underruns..? */ 1236 vga_wseq(regbase, CL_SEQR1F, 0x22);
1237 /* ## vorher d0 avoid FIFO underruns..? */
1238 vga_wseq(regbase, CL_SEQRF, 0xd0);
1223 break; 1239 break;
1224 1240
1225 case BT_SPECTRUM: 1241 case BT_SPECTRUM:
1226 DPRINTK ("(for Spectrum)\n"); 1242 DPRINTK("(for Spectrum)\n");
1227/* ### ueberall 0x22? */ 1243 /* ### ueberall 0x22? */
1228 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */ 1244 /* ##vorher 1c MCLK select */
1229 vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0? avoid FIFO underruns..? */ 1245 vga_wseq(regbase, CL_SEQR1F, 0x22);
1246 /* evtl d0? avoid FIFO underruns..? */
1247 vga_wseq(regbase, CL_SEQRF, 0xb0);
1230 break; 1248 break;
1231 1249
1232 case BT_PICASSO4: 1250 case BT_PICASSO4:
1233 case BT_ALPINE: 1251 case BT_ALPINE:
1234 case BT_GD5480: 1252 case BT_GD5480:
1235 case BT_LAGUNA: 1253 case BT_LAGUNA:
1236 DPRINTK (" (for GD54xx)\n"); 1254 DPRINTK(" (for GD54xx)\n");
1237 /* do nothing */ 1255 /* do nothing */
1238 break; 1256 break;
1239 1257
1240 default: 1258 default:
1241 printk (KERN_WARNING "cirrusfb: unknown Board\n"); 1259 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1242 break; 1260 break;
1243 } 1261 }
1244 1262
1245 WGen (cinfo, VGA_PEL_MSK, 0x01); /* pixel mask: pass-through for first plane */ 1263 /* pixel mask: pass-through for first plane */
1264 WGen(cinfo, VGA_PEL_MSK, 0x01);
1246 if (regs.multiplexing) 1265 if (regs.multiplexing)
1247 WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */ 1266 /* hidden dac reg: 1280x1024 */
1267 WHDR(cinfo, 0x4a);
1248 else 1268 else
1249 WHDR (cinfo, 0); /* hidden dac: nothing */ 1269 /* hidden dac: nothing */
1250 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x06); /* memory mode: odd/even, ext. memory */ 1270 WHDR(cinfo, 0);
1251 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0x01); /* plane mask: only write to first plane */ 1271 /* memory mode: odd/even, ext. memory */
1272 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1273 /* plane mask: only write to first plane */
1274 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1252 offset = var->xres_virtual / 16; 1275 offset = var->xres_virtual / 16;
1253 } 1276 }
1254 1277
@@ -1259,7 +1282,7 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1259 */ 1282 */
1260 1283
1261 else if (var->bits_per_pixel == 8) { 1284 else if (var->bits_per_pixel == 8) {
1262 DPRINTK ("cirrusfb: preparing for 8 bit deep display\n"); 1285 DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
1263 switch (cinfo->btype) { 1286 switch (cinfo->btype) {
1264 case BT_SD64: 1287 case BT_SD64:
1265 case BT_PICCOLO: 1288 case BT_PICCOLO:
@@ -1268,75 +1291,89 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1268 case BT_PICASSO4: 1291 case BT_PICASSO4:
1269 case BT_ALPINE: 1292 case BT_ALPINE:
1270 case BT_GD5480: 1293 case BT_GD5480:
1271 DPRINTK (" (for GD54xx)\n"); 1294 DPRINTK(" (for GD54xx)\n");
1272 vga_wseq (regbase, CL_SEQR7, 1295 vga_wseq(regbase, CL_SEQR7,
1273 regs.multiplexing ? 1296 regs.multiplexing ?
1274 bi->sr07_8bpp_mux : bi->sr07_8bpp); 1297 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1275 break; 1298 break;
1276 1299
1277 case BT_LAGUNA: 1300 case BT_LAGUNA:
1278 DPRINTK (" (for GD546x)\n"); 1301 DPRINTK(" (for GD546x)\n");
1279 vga_wseq (regbase, CL_SEQR7, 1302 vga_wseq(regbase, CL_SEQR7,
1280 vga_rseq (regbase, CL_SEQR7) | 0x01); 1303 vga_rseq(regbase, CL_SEQR7) | 0x01);
1281 break; 1304 break;
1282 1305
1283 default: 1306 default:
1284 printk (KERN_WARNING "cirrusfb: unknown Board\n"); 1307 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1285 break; 1308 break;
1286 } 1309 }
1287 1310
1288 switch (cinfo->btype) { 1311 switch (cinfo->btype) {
1289 case BT_SD64: 1312 case BT_SD64:
1290 vga_wseq (regbase, CL_SEQR1F, 0x1d); /* MCLK select */ 1313 /* MCLK select */
1314 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1291 break; 1315 break;
1292 1316
1293 case BT_PICCOLO: 1317 case BT_PICCOLO:
1294 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */ 1318 /* ### vorher 1c MCLK select */
1295 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1319 vga_wseq(regbase, CL_SEQR1F, 0x22);
1320 /* Fast Page-Mode writes */
1321 vga_wseq(regbase, CL_SEQRF, 0xb0);
1296 break; 1322 break;
1297 1323
1298 case BT_PICASSO: 1324 case BT_PICASSO:
1299 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */ 1325 /* ### vorher 1c MCLK select */
1300 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1326 vga_wseq(regbase, CL_SEQR1F, 0x22);
1327 /* Fast Page-Mode writes */
1328 vga_wseq(regbase, CL_SEQRF, 0xb0);
1301 break; 1329 break;
1302 1330
1303 case BT_SPECTRUM: 1331 case BT_SPECTRUM:
1304 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */ 1332 /* ### vorher 1c MCLK select */
1305 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1333 vga_wseq(regbase, CL_SEQR1F, 0x22);
1334 /* Fast Page-Mode writes */
1335 vga_wseq(regbase, CL_SEQRF, 0xb0);
1306 break; 1336 break;
1307 1337
1308 case BT_PICASSO4: 1338 case BT_PICASSO4:
1309#ifdef CONFIG_ZORRO 1339#ifdef CONFIG_ZORRO
1310 vga_wseq (regbase, CL_SEQRF, 0xb8); /* ### INCOMPLETE!! */ 1340 /* ### INCOMPLETE!! */
1341 vga_wseq(regbase, CL_SEQRF, 0xb8);
1311#endif 1342#endif
1312/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */ 1343/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1313 break; 1344 break;
1314 1345
1315 case BT_ALPINE: 1346 case BT_ALPINE:
1316 DPRINTK (" (for GD543x)\n"); 1347 DPRINTK(" (for GD543x)\n");
1317 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK); 1348 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1318 /* We already set SRF and SR1F */ 1349 /* We already set SRF and SR1F */
1319 break; 1350 break;
1320 1351
1321 case BT_GD5480: 1352 case BT_GD5480:
1322 case BT_LAGUNA: 1353 case BT_LAGUNA:
1323 DPRINTK (" (for GD54xx)\n"); 1354 DPRINTK(" (for GD54xx)\n");
1324 /* do nothing */ 1355 /* do nothing */
1325 break; 1356 break;
1326 1357
1327 default: 1358 default:
1328 printk (KERN_WARNING "cirrusfb: unknown Board\n"); 1359 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1329 break; 1360 break;
1330 } 1361 }
1331 1362
1332 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */ 1363 /* mode register: 256 color mode */
1333 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */ 1364 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1365 /* pixel mask: pass-through all planes */
1366 WGen(cinfo, VGA_PEL_MSK, 0xff);
1334 if (regs.multiplexing) 1367 if (regs.multiplexing)
1335 WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */ 1368 /* hidden dac reg: 1280x1024 */
1369 WHDR(cinfo, 0x4a);
1336 else 1370 else
1337 WHDR (cinfo, 0); /* hidden dac: nothing */ 1371 /* hidden dac: nothing */
1338 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */ 1372 WHDR(cinfo, 0);
1339 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */ 1373 /* memory mode: chain4, ext. memory */
1374 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1375 /* plane mask: enable writing to all 4 planes */
1376 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1340 offset = var->xres_virtual / 8; 1377 offset = var->xres_virtual / 8;
1341 } 1378 }
1342 1379
@@ -1347,72 +1384,84 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1347 */ 1384 */
1348 1385
1349 else if (var->bits_per_pixel == 16) { 1386 else if (var->bits_per_pixel == 16) {
1350 DPRINTK ("cirrusfb: preparing for 16 bit deep display\n"); 1387 DPRINTK("cirrusfb: preparing for 16 bit deep display\n");
1351 switch (cinfo->btype) { 1388 switch (cinfo->btype) {
1352 case BT_SD64: 1389 case BT_SD64:
1353 vga_wseq (regbase, CL_SEQR7, 0xf7); /* Extended Sequencer Mode: 256c col. mode */ 1390 /* Extended Sequencer Mode: 256c col. mode */
1354 vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */ 1391 vga_wseq(regbase, CL_SEQR7, 0xf7);
1392 /* MCLK select */
1393 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1355 break; 1394 break;
1356 1395
1357 case BT_PICCOLO: 1396 case BT_PICCOLO:
1358 vga_wseq (regbase, CL_SEQR7, 0x87); 1397 vga_wseq(regbase, CL_SEQR7, 0x87);
1359 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1398 /* Fast Page-Mode writes */
1360 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */ 1399 vga_wseq(regbase, CL_SEQRF, 0xb0);
1400 /* MCLK select */
1401 vga_wseq(regbase, CL_SEQR1F, 0x22);
1361 break; 1402 break;
1362 1403
1363 case BT_PICASSO: 1404 case BT_PICASSO:
1364 vga_wseq (regbase, CL_SEQR7, 0x27); 1405 vga_wseq(regbase, CL_SEQR7, 0x27);
1365 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1406 /* Fast Page-Mode writes */
1366 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */ 1407 vga_wseq(regbase, CL_SEQRF, 0xb0);
1408 /* MCLK select */
1409 vga_wseq(regbase, CL_SEQR1F, 0x22);
1367 break; 1410 break;
1368 1411
1369 case BT_SPECTRUM: 1412 case BT_SPECTRUM:
1370 vga_wseq (regbase, CL_SEQR7, 0x87); 1413 vga_wseq(regbase, CL_SEQR7, 0x87);
1371 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1414 /* Fast Page-Mode writes */
1372 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */ 1415 vga_wseq(regbase, CL_SEQRF, 0xb0);
1416 /* MCLK select */
1417 vga_wseq(regbase, CL_SEQR1F, 0x22);
1373 break; 1418 break;
1374 1419
1375 case BT_PICASSO4: 1420 case BT_PICASSO4:
1376 vga_wseq (regbase, CL_SEQR7, 0x27); 1421 vga_wseq(regbase, CL_SEQR7, 0x27);
1377/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */ 1422/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1378 break; 1423 break;
1379 1424
1380 case BT_ALPINE: 1425 case BT_ALPINE:
1381 DPRINTK (" (for GD543x)\n"); 1426 DPRINTK(" (for GD543x)\n");
1382 if (regs.HorizRes >= 1024) 1427 if (regs.HorizRes >= 1024)
1383 vga_wseq (regbase, CL_SEQR7, 0xa7); 1428 vga_wseq(regbase, CL_SEQR7, 0xa7);
1384 else 1429 else
1385 vga_wseq (regbase, CL_SEQR7, 0xa3); 1430 vga_wseq(regbase, CL_SEQR7, 0xa3);
1386 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK); 1431 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1387 break; 1432 break;
1388 1433
1389 case BT_GD5480: 1434 case BT_GD5480:
1390 DPRINTK (" (for GD5480)\n"); 1435 DPRINTK(" (for GD5480)\n");
1391 vga_wseq (regbase, CL_SEQR7, 0x17); 1436 vga_wseq(regbase, CL_SEQR7, 0x17);
1392 /* We already set SRF and SR1F */ 1437 /* We already set SRF and SR1F */
1393 break; 1438 break;
1394 1439
1395 case BT_LAGUNA: 1440 case BT_LAGUNA:
1396 DPRINTK (" (for GD546x)\n"); 1441 DPRINTK(" (for GD546x)\n");
1397 vga_wseq (regbase, CL_SEQR7, 1442 vga_wseq(regbase, CL_SEQR7,
1398 vga_rseq (regbase, CL_SEQR7) & ~0x01); 1443 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1399 break; 1444 break;
1400 1445
1401 default: 1446 default:
1402 printk (KERN_WARNING "CIRRUSFB: unknown Board\n"); 1447 printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
1403 break; 1448 break;
1404 } 1449 }
1405 1450
1406 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */ 1451 /* mode register: 256 color mode */
1407 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */ 1452 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1453 /* pixel mask: pass-through all planes */
1454 WGen(cinfo, VGA_PEL_MSK, 0xff);
1408#ifdef CONFIG_PCI 1455#ifdef CONFIG_PCI
1409 WHDR (cinfo, 0xc0); /* Copy Xbh */ 1456 WHDR(cinfo, 0xc0); /* Copy Xbh */
1410#elif defined(CONFIG_ZORRO) 1457#elif defined(CONFIG_ZORRO)
1411 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */ 1458 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1412 WHDR (cinfo, 0xa0); /* hidden dac reg: nothing special */ 1459 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1413#endif 1460#endif
1414 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */ 1461 /* memory mode: chain4, ext. memory */
1415 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */ 1462 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1463 /* plane mask: enable writing to all 4 planes */
1464 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1416 offset = var->xres_virtual / 4; 1465 offset = var->xres_virtual / 4;
1417 } 1466 }
1418 1467
@@ -1423,64 +1472,77 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1423 */ 1472 */
1424 1473
1425 else if (var->bits_per_pixel == 32) { 1474 else if (var->bits_per_pixel == 32) {
1426 DPRINTK ("cirrusfb: preparing for 24/32 bit deep display\n"); 1475 DPRINTK("cirrusfb: preparing for 24/32 bit deep display\n");
1427 switch (cinfo->btype) { 1476 switch (cinfo->btype) {
1428 case BT_SD64: 1477 case BT_SD64:
1429 vga_wseq (regbase, CL_SEQR7, 0xf9); /* Extended Sequencer Mode: 256c col. mode */ 1478 /* Extended Sequencer Mode: 256c col. mode */
1430 vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */ 1479 vga_wseq(regbase, CL_SEQR7, 0xf9);
1480 /* MCLK select */
1481 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1431 break; 1482 break;
1432 1483
1433 case BT_PICCOLO: 1484 case BT_PICCOLO:
1434 vga_wseq (regbase, CL_SEQR7, 0x85); 1485 vga_wseq(regbase, CL_SEQR7, 0x85);
1435 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1486 /* Fast Page-Mode writes */
1436 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */ 1487 vga_wseq(regbase, CL_SEQRF, 0xb0);
1488 /* MCLK select */
1489 vga_wseq(regbase, CL_SEQR1F, 0x22);
1437 break; 1490 break;
1438 1491
1439 case BT_PICASSO: 1492 case BT_PICASSO:
1440 vga_wseq (regbase, CL_SEQR7, 0x25); 1493 vga_wseq(regbase, CL_SEQR7, 0x25);
1441 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1494 /* Fast Page-Mode writes */
1442 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */ 1495 vga_wseq(regbase, CL_SEQRF, 0xb0);
1496 /* MCLK select */
1497 vga_wseq(regbase, CL_SEQR1F, 0x22);
1443 break; 1498 break;
1444 1499
1445 case BT_SPECTRUM: 1500 case BT_SPECTRUM:
1446 vga_wseq (regbase, CL_SEQR7, 0x85); 1501 vga_wseq(regbase, CL_SEQR7, 0x85);
1447 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */ 1502 /* Fast Page-Mode writes */
1448 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */ 1503 vga_wseq(regbase, CL_SEQRF, 0xb0);
1504 /* MCLK select */
1505 vga_wseq(regbase, CL_SEQR1F, 0x22);
1449 break; 1506 break;
1450 1507
1451 case BT_PICASSO4: 1508 case BT_PICASSO4:
1452 vga_wseq (regbase, CL_SEQR7, 0x25); 1509 vga_wseq(regbase, CL_SEQR7, 0x25);
1453/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */ 1510/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1454 break; 1511 break;
1455 1512
1456 case BT_ALPINE: 1513 case BT_ALPINE:
1457 DPRINTK (" (for GD543x)\n"); 1514 DPRINTK(" (for GD543x)\n");
1458 vga_wseq (regbase, CL_SEQR7, 0xa9); 1515 vga_wseq(regbase, CL_SEQR7, 0xa9);
1459 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK); 1516 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1460 break; 1517 break;
1461 1518
1462 case BT_GD5480: 1519 case BT_GD5480:
1463 DPRINTK (" (for GD5480)\n"); 1520 DPRINTK(" (for GD5480)\n");
1464 vga_wseq (regbase, CL_SEQR7, 0x19); 1521 vga_wseq(regbase, CL_SEQR7, 0x19);
1465 /* We already set SRF and SR1F */ 1522 /* We already set SRF and SR1F */
1466 break; 1523 break;
1467 1524
1468 case BT_LAGUNA: 1525 case BT_LAGUNA:
1469 DPRINTK (" (for GD546x)\n"); 1526 DPRINTK(" (for GD546x)\n");
1470 vga_wseq (regbase, CL_SEQR7, 1527 vga_wseq(regbase, CL_SEQR7,
1471 vga_rseq (regbase, CL_SEQR7) & ~0x01); 1528 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1472 break; 1529 break;
1473 1530
1474 default: 1531 default:
1475 printk (KERN_WARNING "cirrusfb: unknown Board\n"); 1532 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1476 break; 1533 break;
1477 } 1534 }
1478 1535
1479 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */ 1536 /* mode register: 256 color mode */
1480 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */ 1537 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1481 WHDR (cinfo, 0xc5); /* hidden dac reg: 8-8-8 mode (24 or 32) */ 1538 /* pixel mask: pass-through all planes */
1482 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */ 1539 WGen(cinfo, VGA_PEL_MSK, 0xff);
1483 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */ 1540 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1541 WHDR(cinfo, 0xc5);
1542 /* memory mode: chain4, ext. memory */
1543 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1544 /* plane mask: enable writing to all 4 planes */
1545 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1484 offset = var->xres_virtual / 4; 1546 offset = var->xres_virtual / 4;
1485 } 1547 }
1486 1548
@@ -1490,48 +1552,67 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1490 * 1552 *
1491 */ 1553 */
1492 1554
1493 else { 1555 else
1494 printk (KERN_ERR "cirrusfb: What's this?? requested color depth == %d.\n", 1556 printk(KERN_ERR "cirrusfb: What's this?? "
1557 " requested color depth == %d.\n",
1495 var->bits_per_pixel); 1558 var->bits_per_pixel);
1496 }
1497 1559
1498 vga_wcrt (regbase, VGA_CRTC_OFFSET, offset & 0xff); 1560 vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
1499 tmp = 0x22; 1561 tmp = 0x22;
1500 if (offset & 0x100) 1562 if (offset & 0x100)
1501 tmp |= 0x10; /* offset overflow bit */ 1563 tmp |= 0x10; /* offset overflow bit */
1502 1564
1503 vga_wcrt (regbase, CL_CRT1B, tmp); /* screen start addr #16-18, fastpagemode cycles */ 1565 /* screen start addr #16-18, fastpagemode cycles */
1566 vga_wcrt(regbase, CL_CRT1B, tmp);
1504 1567
1505 if (cinfo->btype == BT_SD64 || 1568 if (cinfo->btype == BT_SD64 ||
1506 cinfo->btype == BT_PICASSO4 || 1569 cinfo->btype == BT_PICASSO4 ||
1507 cinfo->btype == BT_ALPINE || 1570 cinfo->btype == BT_ALPINE ||
1508 cinfo->btype == BT_GD5480) 1571 cinfo->btype == BT_GD5480)
1509 vga_wcrt (regbase, CL_CRT1D, 0x00); /* screen start address bit 19 */ 1572 /* screen start address bit 19 */
1510 1573 vga_wcrt(regbase, CL_CRT1D, 0x00);
1511 vga_wcrt (regbase, VGA_CRTC_CURSOR_HI, 0); /* text cursor location high */ 1574
1512 vga_wcrt (regbase, VGA_CRTC_CURSOR_LO, 0); /* text cursor location low */ 1575 /* text cursor location high */
1513 vga_wcrt (regbase, VGA_CRTC_UNDERLINE, 0); /* underline row scanline = at very bottom */ 1576 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
1514 1577 /* text cursor location low */
1515 vga_wattr (regbase, VGA_ATC_MODE, 1); /* controller mode */ 1578 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
1516 vga_wattr (regbase, VGA_ATC_OVERSCAN, 0); /* overscan (border) color */ 1579 /* underline row scanline = at very bottom */
1517 vga_wattr (regbase, VGA_ATC_PLANE_ENABLE, 15); /* color plane enable */ 1580 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
1518 vga_wattr (regbase, CL_AR33, 0); /* pixel panning */ 1581
1519 vga_wattr (regbase, VGA_ATC_COLOR_PAGE, 0); /* color select */ 1582 /* controller mode */
1583 vga_wattr(regbase, VGA_ATC_MODE, 1);
1584 /* overscan (border) color */
1585 vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
1586 /* color plane enable */
1587 vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
1588 /* pixel panning */
1589 vga_wattr(regbase, CL_AR33, 0);
1590 /* color select */
1591 vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
1520 1592
1521 /* [ EGS: SetOffset(); ] */ 1593 /* [ EGS: SetOffset(); ] */
1522 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */ 1594 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1523 AttrOn (cinfo); 1595 AttrOn(cinfo);
1524 1596
1525 vga_wgfx (regbase, VGA_GFX_SR_VALUE, 0); /* set/reset register */ 1597 /* set/reset register */
1526 vga_wgfx (regbase, VGA_GFX_SR_ENABLE, 0); /* set/reset enable */ 1598 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
1527 vga_wgfx (regbase, VGA_GFX_COMPARE_VALUE, 0); /* color compare */ 1599 /* set/reset enable */
1528 vga_wgfx (regbase, VGA_GFX_DATA_ROTATE, 0); /* data rotate */ 1600 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
1529 vga_wgfx (regbase, VGA_GFX_PLANE_READ, 0); /* read map select */ 1601 /* color compare */
1530 vga_wgfx (regbase, VGA_GFX_MISC, 1); /* miscellaneous register */ 1602 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
1531 vga_wgfx (regbase, VGA_GFX_COMPARE_MASK, 15); /* color don't care */ 1603 /* data rotate */
1532 vga_wgfx (regbase, VGA_GFX_BIT_MASK, 255); /* bit mask */ 1604 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
1533 1605 /* read map select */
1534 vga_wseq (regbase, CL_SEQR12, 0x0); /* graphics cursor attributes: nothing special */ 1606 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
1607 /* miscellaneous register */
1608 vga_wgfx(regbase, VGA_GFX_MISC, 1);
1609 /* color don't care */
1610 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
1611 /* bit mask */
1612 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
1613
1614 /* graphics cursor attributes: nothing special */
1615 vga_wseq(regbase, CL_SEQR12, 0x0);
1535 1616
1536 /* finally, turn on everything - turn off "FullBandwidth" bit */ 1617 /* finally, turn on everything - turn off "FullBandwidth" bit */
1537 /* also, set "DotClock%2" bit where requested */ 1618 /* also, set "DotClock%2" bit where requested */
@@ -1542,8 +1623,8 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1542 tmp |= 0x08; 1623 tmp |= 0x08;
1543*/ 1624*/
1544 1625
1545 vga_wseq (regbase, VGA_SEQ_CLOCK_MODE, tmp); 1626 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1546 DPRINTK ("CL_SEQR1: %d\n", tmp); 1627 DPRINTK("CL_SEQR1: %d\n", tmp);
1547 1628
1548 cinfo->currentmode = regs; 1629 cinfo->currentmode = regs;
1549 info->fix.type = regs.type; 1630 info->fix.type = regs.type;
@@ -1551,27 +1632,27 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
1551 info->fix.line_length = regs.line_length; 1632 info->fix.line_length = regs.line_length;
1552 1633
1553 /* pan to requested offset */ 1634 /* pan to requested offset */
1554 cirrusfb_pan_display (var, info); 1635 cirrusfb_pan_display(var, info);
1555 1636
1556#ifdef CIRRUSFB_DEBUG 1637#ifdef CIRRUSFB_DEBUG
1557 cirrusfb_dump (); 1638 cirrusfb_dump();
1558#endif 1639#endif
1559 1640
1560 DPRINTK ("EXIT\n"); 1641 DPRINTK("EXIT\n");
1561 return 0; 1642 return 0;
1562} 1643}
1563 1644
1564/* for some reason incomprehensible to me, cirrusfb requires that you write 1645/* for some reason incomprehensible to me, cirrusfb requires that you write
1565 * the registers twice for the settings to take..grr. -dte */ 1646 * the registers twice for the settings to take..grr. -dte */
1566static int cirrusfb_set_par (struct fb_info *info) 1647static int cirrusfb_set_par(struct fb_info *info)
1567{ 1648{
1568 cirrusfb_set_par_foo (info); 1649 cirrusfb_set_par_foo(info);
1569 return cirrusfb_set_par_foo (info); 1650 return cirrusfb_set_par_foo(info);
1570} 1651}
1571 1652
1572static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green, 1653static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1573 unsigned blue, unsigned transp, 1654 unsigned blue, unsigned transp,
1574 struct fb_info *info) 1655 struct fb_info *info)
1575{ 1656{
1576 struct cirrusfb_info *cinfo = info->par; 1657 struct cirrusfb_info *cinfo = info->par;
1577 1658
@@ -1584,23 +1665,23 @@ static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1584 green >>= (16 - info->var.green.length); 1665 green >>= (16 - info->var.green.length);
1585 blue >>= (16 - info->var.blue.length); 1666 blue >>= (16 - info->var.blue.length);
1586 1667
1587 if (regno>=16) 1668 if (regno >= 16)
1588 return 1; 1669 return 1;
1589 v = (red << info->var.red.offset) | 1670 v = (red << info->var.red.offset) |
1590 (green << info->var.green.offset) | 1671 (green << info->var.green.offset) |
1591 (blue << info->var.blue.offset); 1672 (blue << info->var.blue.offset);
1592 1673
1593 switch (info->var.bits_per_pixel) { 1674 switch (info->var.bits_per_pixel) {
1594 case 8: 1675 case 8:
1595 cinfo->pseudo_palette[regno] = v; 1676 cinfo->pseudo_palette[regno] = v;
1596 break; 1677 break;
1597 case 16: 1678 case 16:
1598 cinfo->pseudo_palette[regno] = v; 1679 cinfo->pseudo_palette[regno] = v;
1599 break; 1680 break;
1600 case 24: 1681 case 24:
1601 case 32: 1682 case 32:
1602 cinfo->pseudo_palette[regno] = v; 1683 cinfo->pseudo_palette[regno] = v;
1603 break; 1684 break;
1604 } 1685 }
1605 return 0; 1686 return 0;
1606 } 1687 }
@@ -1609,9 +1690,8 @@ static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1609 cinfo->palette[regno].green = green; 1690 cinfo->palette[regno].green = green;
1610 cinfo->palette[regno].blue = blue; 1691 cinfo->palette[regno].blue = blue;
1611 1692
1612 if (info->var.bits_per_pixel == 8) { 1693 if (info->var.bits_per_pixel == 8)
1613 WClut (cinfo, regno, red >> 10, green >> 10, blue >> 10); 1694 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1614 }
1615 1695
1616 return 0; 1696 return 0;
1617 1697
@@ -1622,8 +1702,8 @@ static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1622 1702
1623 performs display panning - provided hardware permits this 1703 performs display panning - provided hardware permits this
1624**************************************************************************/ 1704**************************************************************************/
1625static int cirrusfb_pan_display (struct fb_var_screeninfo *var, 1705static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1626 struct fb_info *info) 1706 struct fb_info *info)
1627{ 1707{
1628 int xoffset = 0; 1708 int xoffset = 0;
1629 int yoffset = 0; 1709 int yoffset = 0;
@@ -1631,8 +1711,8 @@ static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
1631 unsigned char tmp = 0, tmp2 = 0, xpix; 1711 unsigned char tmp = 0, tmp2 = 0, xpix;
1632 struct cirrusfb_info *cinfo = info->par; 1712 struct cirrusfb_info *cinfo = info->par;
1633 1713
1634 DPRINTK ("ENTER\n"); 1714 DPRINTK("ENTER\n");
1635 DPRINTK ("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset); 1715 DPRINTK("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1636 1716
1637 /* no range checks for xoffset and yoffset, */ 1717 /* no range checks for xoffset and yoffset, */
1638 /* as fb_pan_display has already done this */ 1718 /* as fb_pan_display has already done this */
@@ -1655,11 +1735,13 @@ static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
1655 xpix = (unsigned char) ((xoffset % 4) * 2); 1735 xpix = (unsigned char) ((xoffset % 4) * 2);
1656 } 1736 }
1657 1737
1658 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */ 1738 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1659 1739
1660 /* lower 8 + 8 bits of screen start address */ 1740 /* lower 8 + 8 bits of screen start address */
1661 vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, (unsigned char) (base & 0xff)); 1741 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
1662 vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, (unsigned char) (base >> 8)); 1742 (unsigned char) (base & 0xff));
1743 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
1744 (unsigned char) (base >> 8));
1663 1745
1664 /* construct bits 16, 17 and 18 of screen start address */ 1746 /* construct bits 16, 17 and 18 of screen start address */
1665 if (base & 0x10000) 1747 if (base & 0x10000)
@@ -1669,50 +1751,53 @@ static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
1669 if (base & 0x40000) 1751 if (base & 0x40000)
1670 tmp |= 0x08; 1752 tmp |= 0x08;
1671 1753
1672 tmp2 = (vga_rcrt (cinfo->regbase, CL_CRT1B) & 0xf2) | tmp; /* 0xf2 is %11110010, exclude tmp bits */ 1754 /* 0xf2 is %11110010, exclude tmp bits */
1673 vga_wcrt (cinfo->regbase, CL_CRT1B, tmp2); 1755 tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
1756 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
1674 1757
1675 /* construct bit 19 of screen start address */ 1758 /* construct bit 19 of screen start address */
1676 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) { 1759 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1677 tmp2 = 0; 1760 tmp2 = 0;
1678 if (base & 0x80000) 1761 if (base & 0x80000)
1679 tmp2 = 0x80; 1762 tmp2 = 0x80;
1680 vga_wcrt (cinfo->regbase, CL_CRT1D, tmp2); 1763 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp2);
1681 } 1764 }
1682 1765
1683 /* write pixel panning value to AR33; this does not quite work in 8bpp */ 1766 /* write pixel panning value to AR33; this does not quite work in 8bpp
1684 /* ### Piccolo..? Will this work? */ 1767 *
1768 * ### Piccolo..? Will this work?
1769 */
1685 if (info->var.bits_per_pixel == 1) 1770 if (info->var.bits_per_pixel == 1)
1686 vga_wattr (cinfo->regbase, CL_AR33, xpix); 1771 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1687 1772
1688 cirrusfb_WaitBLT (cinfo->regbase); 1773 cirrusfb_WaitBLT(cinfo->regbase);
1689 1774
1690 DPRINTK ("EXIT\n"); 1775 DPRINTK("EXIT\n");
1691 return (0); 1776 return 0;
1692} 1777}
1693 1778
1694 1779static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1695static int cirrusfb_blank (int blank_mode, struct fb_info *info)
1696{ 1780{
1697 /* 1781 /*
1698 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL 1782 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1699 * then the caller blanks by setting the CLUT (Color Look Up Table) to all 1783 * then the caller blanks by setting the CLUT (Color Look Up Table)
1700 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due 1784 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1701 * to e.g. a video mode which doesn't support it. Implements VESA suspend 1785 * failed due to e.g. a video mode which doesn't support it.
1702 * and powerdown modes on hardware that supports disabling hsync/vsync: 1786 * Implements VESA suspend and powerdown modes on hardware that
1703 * blank_mode == 2: suspend vsync 1787 * supports disabling hsync/vsync:
1704 * blank_mode == 3: suspend hsync 1788 * blank_mode == 2: suspend vsync
1705 * blank_mode == 4: powerdown 1789 * blank_mode == 3: suspend hsync
1790 * blank_mode == 4: powerdown
1706 */ 1791 */
1707 unsigned char val; 1792 unsigned char val;
1708 struct cirrusfb_info *cinfo = info->par; 1793 struct cirrusfb_info *cinfo = info->par;
1709 int current_mode = cinfo->blank_mode; 1794 int current_mode = cinfo->blank_mode;
1710 1795
1711 DPRINTK ("ENTER, blank mode = %d\n", blank_mode); 1796 DPRINTK("ENTER, blank mode = %d\n", blank_mode);
1712 1797
1713 if (info->state != FBINFO_STATE_RUNNING || 1798 if (info->state != FBINFO_STATE_RUNNING ||
1714 current_mode == blank_mode) { 1799 current_mode == blank_mode) {
1715 DPRINTK ("EXIT, returning 0\n"); 1800 DPRINTK("EXIT, returning 0\n");
1716 return 0; 1801 return 0;
1717 } 1802 }
1718 1803
@@ -1720,17 +1805,19 @@ static int cirrusfb_blank (int blank_mode, struct fb_info *info)
1720 if (current_mode == FB_BLANK_NORMAL || 1805 if (current_mode == FB_BLANK_NORMAL ||
1721 current_mode == FB_BLANK_UNBLANK) { 1806 current_mode == FB_BLANK_UNBLANK) {
1722 /* unblank the screen */ 1807 /* unblank the screen */
1723 val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE); 1808 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1724 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf); /* clear "FullBandwidth" bit */ 1809 /* clear "FullBandwidth" bit */
1810 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
1725 /* and undo VESA suspend trickery */ 1811 /* and undo VESA suspend trickery */
1726 vga_wgfx (cinfo->regbase, CL_GRE, 0x00); 1812 vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
1727 } 1813 }
1728 1814
1729 /* set new */ 1815 /* set new */
1730 if(blank_mode > FB_BLANK_NORMAL) { 1816 if (blank_mode > FB_BLANK_NORMAL) {
1731 /* blank the screen */ 1817 /* blank the screen */
1732 val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE); 1818 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1733 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20); /* set "FullBandwidth" bit */ 1819 /* set "FullBandwidth" bit */
1820 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
1734 } 1821 }
1735 1822
1736 switch (blank_mode) { 1823 switch (blank_mode) {
@@ -1738,21 +1825,21 @@ static int cirrusfb_blank (int blank_mode, struct fb_info *info)
1738 case FB_BLANK_NORMAL: 1825 case FB_BLANK_NORMAL:
1739 break; 1826 break;
1740 case FB_BLANK_VSYNC_SUSPEND: 1827 case FB_BLANK_VSYNC_SUSPEND:
1741 vga_wgfx (cinfo->regbase, CL_GRE, 0x04); 1828 vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
1742 break; 1829 break;
1743 case FB_BLANK_HSYNC_SUSPEND: 1830 case FB_BLANK_HSYNC_SUSPEND:
1744 vga_wgfx (cinfo->regbase, CL_GRE, 0x02); 1831 vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
1745 break; 1832 break;
1746 case FB_BLANK_POWERDOWN: 1833 case FB_BLANK_POWERDOWN:
1747 vga_wgfx (cinfo->regbase, CL_GRE, 0x06); 1834 vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
1748 break; 1835 break;
1749 default: 1836 default:
1750 DPRINTK ("EXIT, returning 1\n"); 1837 DPRINTK("EXIT, returning 1\n");
1751 return 1; 1838 return 1;
1752 } 1839 }
1753 1840
1754 cinfo->blank_mode = blank_mode; 1841 cinfo->blank_mode = blank_mode;
1755 DPRINTK ("EXIT, returning 0\n"); 1842 DPRINTK("EXIT, returning 0\n");
1756 1843
1757 /* Let fbcon do a soft blank for us */ 1844 /* Let fbcon do a soft blank for us */
1758 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; 1845 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
@@ -1761,45 +1848,50 @@ static int cirrusfb_blank (int blank_mode, struct fb_info *info)
1761/****************************************************************************/ 1848/****************************************************************************/
1762/**** BEGIN Internal Routines ***********************************************/ 1849/**** BEGIN Internal Routines ***********************************************/
1763 1850
1764static void init_vgachip (struct cirrusfb_info *cinfo) 1851static void init_vgachip(struct cirrusfb_info *cinfo)
1765{ 1852{
1766 const struct cirrusfb_board_info_rec *bi; 1853 const struct cirrusfb_board_info_rec *bi;
1767 1854
1768 DPRINTK ("ENTER\n"); 1855 DPRINTK("ENTER\n");
1769 1856
1770 assert (cinfo != NULL); 1857 assert(cinfo != NULL);
1771 1858
1772 bi = &cirrusfb_board_info[cinfo->btype]; 1859 bi = &cirrusfb_board_info[cinfo->btype];
1773 1860
1774 /* reset board globally */ 1861 /* reset board globally */
1775 switch (cinfo->btype) { 1862 switch (cinfo->btype) {
1776 case BT_PICCOLO: 1863 case BT_PICCOLO:
1777 WSFR (cinfo, 0x01); 1864 WSFR(cinfo, 0x01);
1778 udelay (500); 1865 udelay(500);
1779 WSFR (cinfo, 0x51); 1866 WSFR(cinfo, 0x51);
1780 udelay (500); 1867 udelay(500);
1781 break; 1868 break;
1782 case BT_PICASSO: 1869 case BT_PICASSO:
1783 WSFR2 (cinfo, 0xff); 1870 WSFR2(cinfo, 0xff);
1784 udelay (500); 1871 udelay(500);
1785 break; 1872 break;
1786 case BT_SD64: 1873 case BT_SD64:
1787 case BT_SPECTRUM: 1874 case BT_SPECTRUM:
1788 WSFR (cinfo, 0x1f); 1875 WSFR(cinfo, 0x1f);
1789 udelay (500); 1876 udelay(500);
1790 WSFR (cinfo, 0x4f); 1877 WSFR(cinfo, 0x4f);
1791 udelay (500); 1878 udelay(500);
1792 break; 1879 break;
1793 case BT_PICASSO4: 1880 case BT_PICASSO4:
1794 vga_wcrt (cinfo->regbase, CL_CRT51, 0x00); /* disable flickerfixer */ 1881 /* disable flickerfixer */
1795 mdelay (100); 1882 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1796 vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */ 1883 mdelay(100);
1797 vga_wgfx (cinfo->regbase, CL_GR33, 0x00); /* put blitter into 542x compat */ 1884 /* from Klaus' NetBSD driver: */
1798 vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* mode */ 1885 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1886 /* put blitter into 542x compat */
1887 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1888 /* mode */
1889 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1799 break; 1890 break;
1800 1891
1801 case BT_GD5480: 1892 case BT_GD5480:
1802 vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */ 1893 /* from Klaus' NetBSD driver: */
1894 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1803 break; 1895 break;
1804 1896
1805 case BT_ALPINE: 1897 case BT_ALPINE:
@@ -1807,153 +1899,207 @@ static void init_vgachip (struct cirrusfb_info *cinfo)
1807 break; 1899 break;
1808 1900
1809 default: 1901 default:
1810 printk (KERN_ERR "cirrusfb: Warning: Unknown board type\n"); 1902 printk(KERN_ERR "cirrusfb: Warning: Unknown board type\n");
1811 break; 1903 break;
1812 } 1904 }
1813 1905
1814 assert (cinfo->size > 0); /* make sure RAM size set by this point */ 1906 assert(cinfo->size > 0); /* make sure RAM size set by this point */
1815 1907
1816 /* the P4 is not fully initialized here; I rely on it having been */ 1908 /* the P4 is not fully initialized here; I rely on it having been */
1817 /* inited under AmigaOS already, which seems to work just fine */ 1909 /* inited under AmigaOS already, which seems to work just fine */
1818 /* (Klaus advised to do it this way) */ 1910 /* (Klaus advised to do it this way) */
1819 1911
1820 if (cinfo->btype != BT_PICASSO4) { 1912 if (cinfo->btype != BT_PICASSO4) {
1821 WGen (cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */ 1913 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1822 WGen (cinfo, CL_POS102, 0x01); 1914 WGen(cinfo, CL_POS102, 0x01);
1823 WGen (cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */ 1915 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1824 1916
1825 if (cinfo->btype != BT_SD64) 1917 if (cinfo->btype != BT_SD64)
1826 WGen (cinfo, CL_VSSM2, 0x01); 1918 WGen(cinfo, CL_VSSM2, 0x01);
1827 1919
1828 vga_wseq (cinfo->regbase, CL_SEQR0, 0x03); /* reset sequencer logic */ 1920 /* reset sequencer logic */
1921 vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
1829 1922
1830 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); /* FullBandwidth (video off) and 8/9 dot clock */ 1923 /* FullBandwidth (video off) and 8/9 dot clock */
1831 WGen (cinfo, VGA_MIS_W, 0xc1); /* polarity (-/-), disable access to display memory, VGA_CRTC_START_HI base address: color */ 1924 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1925 /* polarity (-/-), disable access to display memory,
1926 * VGA_CRTC_START_HI base address: color
1927 */
1928 WGen(cinfo, VGA_MIS_W, 0xc1);
1832 1929
1833/* vga_wgfx (cinfo->regbase, CL_GRA, 0xce); "magic cookie" - doesn't make any sense to me.. */ 1930 /* "magic cookie" - doesn't make any sense to me.. */
1834 vga_wseq (cinfo->regbase, CL_SEQR6, 0x12); /* unlock all extension registers */ 1931/* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1932 /* unlock all extension registers */
1933 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1835 1934
1836 vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* reset blitter */ 1935 /* reset blitter */
1936 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1837 1937
1838 switch (cinfo->btype) { 1938 switch (cinfo->btype) {
1839 case BT_GD5480: 1939 case BT_GD5480:
1840 vga_wseq (cinfo->regbase, CL_SEQRF, 0x98); 1940 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1841 break; 1941 break;
1842 case BT_ALPINE: 1942 case BT_ALPINE:
1843 break; 1943 break;
1844 case BT_SD64: 1944 case BT_SD64:
1845 vga_wseq (cinfo->regbase, CL_SEQRF, 0xb8); 1945 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1846 break; 1946 break;
1847 default: 1947 default:
1848 vga_wseq (cinfo->regbase, CL_SEQR16, 0x0f); 1948 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1849 vga_wseq (cinfo->regbase, CL_SEQRF, 0xb0); 1949 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1850 break; 1950 break;
1851 } 1951 }
1852 } 1952 }
1853 vga_wseq (cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: nothing */ 1953 /* plane mask: nothing */
1854 vga_wseq (cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); /* character map select: doesn't even matter in gx mode */ 1954 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1855 vga_wseq (cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e); /* memory mode: chain-4, no odd/even, ext. memory */ 1955 /* character map select: doesn't even matter in gx mode */
1956 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1957 /* memory mode: chain-4, no odd/even, ext. memory */
1958 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
1856 1959
1857 /* controller-internal base address of video memory */ 1960 /* controller-internal base address of video memory */
1858 if (bi->init_sr07) 1961 if (bi->init_sr07)
1859 vga_wseq (cinfo->regbase, CL_SEQR7, bi->sr07); 1962 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1860 1963
1861 /* vga_wseq (cinfo->regbase, CL_SEQR8, 0x00); *//* EEPROM control: shouldn't be necessary to write to this at all.. */ 1964 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1965 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1862 1966
1863 vga_wseq (cinfo->regbase, CL_SEQR10, 0x00); /* graphics cursor X position (incomplete; position gives rem. 3 bits */ 1967 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1864 vga_wseq (cinfo->regbase, CL_SEQR11, 0x00); /* graphics cursor Y position (..."... ) */ 1968 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1865 vga_wseq (cinfo->regbase, CL_SEQR12, 0x00); /* graphics cursor attributes */ 1969 /* graphics cursor Y position (..."... ) */
1866 vga_wseq (cinfo->regbase, CL_SEQR13, 0x00); /* graphics cursor pattern address */ 1970 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1971 /* graphics cursor attributes */
1972 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1973 /* graphics cursor pattern address */
1974 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1867 1975
1868 /* writing these on a P4 might give problems.. */ 1976 /* writing these on a P4 might give problems.. */
1869 if (cinfo->btype != BT_PICASSO4) { 1977 if (cinfo->btype != BT_PICASSO4) {
1870 vga_wseq (cinfo->regbase, CL_SEQR17, 0x00); /* configuration readback and ext. color */ 1978 /* configuration readback and ext. color */
1871 vga_wseq (cinfo->regbase, CL_SEQR18, 0x02); /* signature generator */ 1979 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1980 /* signature generator */
1981 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1872 } 1982 }
1873 1983
1874 /* MCLK select etc. */ 1984 /* MCLK select etc. */
1875 if (bi->init_sr1f) 1985 if (bi->init_sr1f)
1876 vga_wseq (cinfo->regbase, CL_SEQR1F, bi->sr1f); 1986 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1877 1987
1878 vga_wcrt (cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); /* Screen A preset row scan: none */ 1988 /* Screen A preset row scan: none */
1879 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); /* Text cursor start: disable text cursor */ 1989 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1880 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); /* Text cursor end: - */ 1990 /* Text cursor start: disable text cursor */
1881 vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, 0x00); /* Screen start address high: 0 */ 1991 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1882 vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, 0x00); /* Screen start address low: 0 */ 1992 /* Text cursor end: - */
1883 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); /* text cursor location high: 0 */ 1993 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1884 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); /* text cursor location low: 0 */ 1994 /* Screen start address high: 0 */
1885 1995 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
1886 vga_wcrt (cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); /* Underline Row scanline: - */ 1996 /* Screen start address low: 0 */
1887 vga_wcrt (cinfo->regbase, VGA_CRTC_MODE, 0xc3); /* mode control: timing enable, byte mode, no compat modes */ 1997 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
1888 vga_wcrt (cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00); /* Line Compare: not needed */ 1998 /* text cursor location high: 0 */
1999 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
2000 /* text cursor location low: 0 */
2001 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
2002
2003 /* Underline Row scanline: - */
2004 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
2005 /* mode control: timing enable, byte mode, no compat modes */
2006 vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
2007 /* Line Compare: not needed */
2008 vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
1889 /* ### add 0x40 for text modes with > 30 MHz pixclock */ 2009 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1890 vga_wcrt (cinfo->regbase, CL_CRT1B, 0x02); /* ext. display controls: ext.adr. wrap */ 2010 /* ext. display controls: ext.adr. wrap */
1891 2011 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1892 vga_wgfx (cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); /* Set/Reset registes: - */ 2012
1893 vga_wgfx (cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); /* Set/Reset enable: - */ 2013 /* Set/Reset registes: - */
1894 vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); /* Color Compare: - */ 2014 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1895 vga_wgfx (cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); /* Data Rotate: - */ 2015 /* Set/Reset enable: - */
1896 vga_wgfx (cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); /* Read Map Select: - */ 2016 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1897 vga_wgfx (cinfo->regbase, VGA_GFX_MODE, 0x00); /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */ 2017 /* Color Compare: - */
1898 vga_wgfx (cinfo->regbase, VGA_GFX_MISC, 0x01); /* Miscellaneous: memory map base address, graphics mode */ 2018 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1899 vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); /* Color Don't care: involve all planes */ 2019 /* Data Rotate: - */
1900 vga_wgfx (cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); /* Bit Mask: no mask at all */ 2020 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
2021 /* Read Map Select: - */
2022 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
2023 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
2024 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
2025 /* Miscellaneous: memory map base address, graphics mode */
2026 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
2027 /* Color Don't care: involve all planes */
2028 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
2029 /* Bit Mask: no mask at all */
2030 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1901 if (cinfo->btype == BT_ALPINE) 2031 if (cinfo->btype == BT_ALPINE)
1902 vga_wgfx (cinfo->regbase, CL_GRB, 0x20); /* (5434 can't have bit 3 set for bitblt) */ 2032 /* (5434 can't have bit 3 set for bitblt) */
2033 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1903 else 2034 else
1904 vga_wgfx (cinfo->regbase, CL_GRB, 0x28); /* Graphics controller mode extensions: finer granularity, 8byte data latches */ 2035 /* Graphics controller mode extensions: finer granularity,
1905 2036 * 8byte data latches
1906 vga_wgfx (cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ 2037 */
1907 vga_wgfx (cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ 2038 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1908 vga_wgfx (cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ 2039
1909 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); *//* Background color byte 1: - */ 2040 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1910/* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */ 2041 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1911 2042 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1912 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE0, 0x00); /* Attribute Controller palette registers: "identity mapping" */ 2043 /* Background color byte 1: - */
1913 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE1, 0x01); 2044 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1914 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE2, 0x02); 2045 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1915 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE3, 0x03); 2046
1916 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE4, 0x04); 2047 /* Attribute Controller palette registers: "identity mapping" */
1917 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE5, 0x05); 2048 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1918 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE6, 0x06); 2049 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1919 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE7, 0x07); 2050 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1920 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE8, 0x08); 2051 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1921 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE9, 0x09); 2052 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1922 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); 2053 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1923 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); 2054 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1924 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); 2055 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1925 vga_wattr (cinfo->regbase, VGA_ATC_PALETTED, 0x0d); 2056 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1926 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); 2057 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1927 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); 2058 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1928 2059 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1929 vga_wattr (cinfo->regbase, VGA_ATC_MODE, 0x01); /* Attribute Controller mode: graphics mode */ 2060 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1930 vga_wattr (cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); /* Overscan color reg.: reg. 0 */ 2061 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1931 vga_wattr (cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); /* Color Plane enable: Enable all 4 planes */ 2062 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1932/* ### vga_wattr (cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */ 2063 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1933 vga_wattr (cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); /* Color Select: - */ 2064
1934 2065 /* Attribute Controller mode: graphics mode */
1935 WGen (cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */ 2066 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
2067 /* Overscan color reg.: reg. 0 */
2068 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
2069 /* Color Plane enable: Enable all 4 planes */
2070 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
2071/* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
2072 /* Color Select: - */
2073 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
2074
2075 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1936 2076
1937 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480) 2077 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
1938 WGen (cinfo, VGA_MIS_W, 0xc3); /* polarity (-/-), enable display mem, VGA_CRTC_START_HI i/o base = color */ 2078 /* polarity (-/-), enable display mem,
2079 * VGA_CRTC_START_HI i/o base = color
2080 */
2081 WGen(cinfo, VGA_MIS_W, 0xc3);
1939 2082
1940 vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* BLT Start/status: Blitter reset */ 2083 /* BLT Start/status: Blitter reset */
1941 vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* - " - : "end-of-reset" */ 2084 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
2085 /* - " - : "end-of-reset" */
2086 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1942 2087
1943 /* misc... */ 2088 /* misc... */
1944 WHDR (cinfo, 0); /* Hidden DAC register: - */ 2089 WHDR(cinfo, 0); /* Hidden DAC register: - */
1945 2090
1946 printk (KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n", cinfo->size); 2091 printk(KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n",
1947 DPRINTK ("EXIT\n"); 2092 cinfo->size);
2093 DPRINTK("EXIT\n");
1948 return; 2094 return;
1949} 2095}
1950 2096
1951static void switch_monitor (struct cirrusfb_info *cinfo, int on) 2097static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1952{ 2098{
1953#ifdef CONFIG_ZORRO /* only works on Zorro boards */ 2099#ifdef CONFIG_ZORRO /* only works on Zorro boards */
1954 static int IsOn = 0; /* XXX not ok for multiple boards */ 2100 static int IsOn = 0; /* XXX not ok for multiple boards */
1955 2101
1956 DPRINTK ("ENTER\n"); 2102 DPRINTK("ENTER\n");
1957 2103
1958 if (cinfo->btype == BT_PICASSO4) 2104 if (cinfo->btype == BT_PICASSO4)
1959 return; /* nothing to switch */ 2105 return; /* nothing to switch */
@@ -1963,44 +2109,43 @@ static void switch_monitor (struct cirrusfb_info *cinfo, int on)
1963 return; /* nothing to switch */ 2109 return; /* nothing to switch */
1964 if (cinfo->btype == BT_PICASSO) { 2110 if (cinfo->btype == BT_PICASSO) {
1965 if ((on && !IsOn) || (!on && IsOn)) 2111 if ((on && !IsOn) || (!on && IsOn))
1966 WSFR (cinfo, 0xff); 2112 WSFR(cinfo, 0xff);
1967 2113
1968 DPRINTK ("EXIT\n"); 2114 DPRINTK("EXIT\n");
1969 return; 2115 return;
1970 } 2116 }
1971 if (on) { 2117 if (on) {
1972 switch (cinfo->btype) { 2118 switch (cinfo->btype) {
1973 case BT_SD64: 2119 case BT_SD64:
1974 WSFR (cinfo, cinfo->SFR | 0x21); 2120 WSFR(cinfo, cinfo->SFR | 0x21);
1975 break; 2121 break;
1976 case BT_PICCOLO: 2122 case BT_PICCOLO:
1977 WSFR (cinfo, cinfo->SFR | 0x28); 2123 WSFR(cinfo, cinfo->SFR | 0x28);
1978 break; 2124 break;
1979 case BT_SPECTRUM: 2125 case BT_SPECTRUM:
1980 WSFR (cinfo, 0x6f); 2126 WSFR(cinfo, 0x6f);
1981 break; 2127 break;
1982 default: /* do nothing */ break; 2128 default: /* do nothing */ break;
1983 } 2129 }
1984 } else { 2130 } else {
1985 switch (cinfo->btype) { 2131 switch (cinfo->btype) {
1986 case BT_SD64: 2132 case BT_SD64:
1987 WSFR (cinfo, cinfo->SFR & 0xde); 2133 WSFR(cinfo, cinfo->SFR & 0xde);
1988 break; 2134 break;
1989 case BT_PICCOLO: 2135 case BT_PICCOLO:
1990 WSFR (cinfo, cinfo->SFR & 0xd7); 2136 WSFR(cinfo, cinfo->SFR & 0xd7);
1991 break; 2137 break;
1992 case BT_SPECTRUM: 2138 case BT_SPECTRUM:
1993 WSFR (cinfo, 0x4f); 2139 WSFR(cinfo, 0x4f);
1994 break; 2140 break;
1995 default: /* do nothing */ break; 2141 default: /* do nothing */ break;
1996 } 2142 }
1997 } 2143 }
1998 2144
1999 DPRINTK ("EXIT\n"); 2145 DPRINTK("EXIT\n");
2000#endif /* CONFIG_ZORRO */ 2146#endif /* CONFIG_ZORRO */
2001} 2147}
2002 2148
2003
2004/******************************************/ 2149/******************************************/
2005/* Linux 2.6-style accelerated functions */ 2150/* Linux 2.6-style accelerated functions */
2006/******************************************/ 2151/******************************************/
@@ -2012,15 +2157,17 @@ static void cirrusfb_prim_fillrect(struct cirrusfb_info *cinfo,
2012 u32 color = (cinfo->info->fix.visual == FB_VISUAL_TRUECOLOR) ? 2157 u32 color = (cinfo->info->fix.visual == FB_VISUAL_TRUECOLOR) ?
2013 cinfo->pseudo_palette[region->color] : region->color; 2158 cinfo->pseudo_palette[region->color] : region->color;
2014 2159
2015 if(cinfo->info->var.bits_per_pixel == 1) { 2160 if (cinfo->info->var.bits_per_pixel == 1) {
2016 cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel, 2161 cirrusfb_RectFill(cinfo->regbase,
2162 cinfo->info->var.bits_per_pixel,
2017 region->dx / 8, region->dy, 2163 region->dx / 8, region->dy,
2018 region->width / 8, region->height, 2164 region->width / 8, region->height,
2019 color, 2165 color,
2020 cinfo->currentmode.line_length); 2166 cinfo->currentmode.line_length);
2021 } else { 2167 } else {
2022 m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8; 2168 m = (cinfo->info->var.bits_per_pixel + 7) / 8;
2023 cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel, 2169 cirrusfb_RectFill(cinfo->regbase,
2170 cinfo->info->var.bits_per_pixel,
2024 region->dx * m, region->dy, 2171 region->dx * m, region->dy,
2025 region->width * m, region->height, 2172 region->width * m, region->height,
2026 color, 2173 color,
@@ -2029,7 +2176,8 @@ static void cirrusfb_prim_fillrect(struct cirrusfb_info *cinfo,
2029 return; 2176 return;
2030} 2177}
2031 2178
2032static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region) 2179static void cirrusfb_fillrect(struct fb_info *info,
2180 const struct fb_fillrect *region)
2033{ 2181{
2034 struct cirrusfb_info *cinfo = info->par; 2182 struct cirrusfb_info *cinfo = info->par;
2035 struct fb_fillrect modded; 2183 struct fb_fillrect modded;
@@ -2047,12 +2195,14 @@ static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *r
2047 2195
2048 memcpy(&modded, region, sizeof(struct fb_fillrect)); 2196 memcpy(&modded, region, sizeof(struct fb_fillrect));
2049 2197
2050 if(!modded.width || !modded.height || 2198 if (!modded.width || !modded.height ||
2051 modded.dx >= vxres || modded.dy >= vyres) 2199 modded.dx >= vxres || modded.dy >= vyres)
2052 return; 2200 return;
2053 2201
2054 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; 2202 if (modded.dx + modded.width > vxres)
2055 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; 2203 modded.width = vxres - modded.dx;
2204 if (modded.dy + modded.height > vyres)
2205 modded.height = vyres - modded.dy;
2056 2206
2057 cirrusfb_prim_fillrect(cinfo, &modded); 2207 cirrusfb_prim_fillrect(cinfo, &modded);
2058} 2208}
@@ -2061,14 +2211,14 @@ static void cirrusfb_prim_copyarea(struct cirrusfb_info *cinfo,
2061 const struct fb_copyarea *area) 2211 const struct fb_copyarea *area)
2062{ 2212{
2063 int m; /* bytes per pixel */ 2213 int m; /* bytes per pixel */
2064 if(cinfo->info->var.bits_per_pixel == 1) { 2214 if (cinfo->info->var.bits_per_pixel == 1) {
2065 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel, 2215 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2066 area->sx / 8, area->sy, 2216 area->sx / 8, area->sy,
2067 area->dx / 8, area->dy, 2217 area->dx / 8, area->dy,
2068 area->width / 8, area->height, 2218 area->width / 8, area->height,
2069 cinfo->currentmode.line_length); 2219 cinfo->currentmode.line_length);
2070 } else { 2220 } else {
2071 m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8; 2221 m = (cinfo->info->var.bits_per_pixel + 7) / 8;
2072 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel, 2222 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2073 area->sx * m, area->sy, 2223 area->sx * m, area->sy,
2074 area->dx * m, area->dy, 2224 area->dx * m, area->dy,
@@ -2078,8 +2228,8 @@ static void cirrusfb_prim_copyarea(struct cirrusfb_info *cinfo,
2078 return; 2228 return;
2079} 2229}
2080 2230
2081 2231static void cirrusfb_copyarea(struct fb_info *info,
2082static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 2232 const struct fb_copyarea *area)
2083{ 2233{
2084 struct cirrusfb_info *cinfo = info->par; 2234 struct cirrusfb_info *cinfo = info->par;
2085 struct fb_copyarea modded; 2235 struct fb_copyarea modded;
@@ -2101,89 +2251,99 @@ static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *ar
2101 vxres = info->var.xres_virtual; 2251 vxres = info->var.xres_virtual;
2102 vyres = info->var.yres_virtual; 2252 vyres = info->var.yres_virtual;
2103 2253
2104 if(!modded.width || !modded.height || 2254 if (!modded.width || !modded.height ||
2105 modded.sx >= vxres || modded.sy >= vyres || 2255 modded.sx >= vxres || modded.sy >= vyres ||
2106 modded.dx >= vxres || modded.dy >= vyres) 2256 modded.dx >= vxres || modded.dy >= vyres)
2107 return; 2257 return;
2108 2258
2109 if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx; 2259 if (modded.sx + modded.width > vxres)
2110 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; 2260 modded.width = vxres - modded.sx;
2111 if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy; 2261 if (modded.dx + modded.width > vxres)
2112 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; 2262 modded.width = vxres - modded.dx;
2263 if (modded.sy + modded.height > vyres)
2264 modded.height = vyres - modded.sy;
2265 if (modded.dy + modded.height > vyres)
2266 modded.height = vyres - modded.dy;
2113 2267
2114 cirrusfb_prim_copyarea(cinfo, &modded); 2268 cirrusfb_prim_copyarea(cinfo, &modded);
2115} 2269}
2116 2270
2117static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image) 2271static void cirrusfb_imageblit(struct fb_info *info,
2272 const struct fb_image *image)
2118{ 2273{
2119 struct cirrusfb_info *cinfo = info->par; 2274 struct cirrusfb_info *cinfo = info->par;
2120 2275
2121 cirrusfb_WaitBLT(cinfo->regbase); 2276 cirrusfb_WaitBLT(cinfo->regbase);
2122 cfb_imageblit(info, image); 2277 cfb_imageblit(info, image);
2123} 2278}
2124 2279
2125
2126#ifdef CONFIG_PPC_PREP 2280#ifdef CONFIG_PPC_PREP
2127#define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000) 2281#define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
2128#define PREP_IO_BASE ((volatile unsigned char *) 0x80000000) 2282#define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
2129static void get_prep_addrs (unsigned long *display, unsigned long *registers) 2283static void get_prep_addrs(unsigned long *display, unsigned long *registers)
2130{ 2284{
2131 DPRINTK ("ENTER\n"); 2285 DPRINTK("ENTER\n");
2132 2286
2133 *display = PREP_VIDEO_BASE; 2287 *display = PREP_VIDEO_BASE;
2134 *registers = (unsigned long) PREP_IO_BASE; 2288 *registers = (unsigned long) PREP_IO_BASE;
2135 2289
2136 DPRINTK ("EXIT\n"); 2290 DPRINTK("EXIT\n");
2137} 2291}
2138 2292
2139#endif /* CONFIG_PPC_PREP */ 2293#endif /* CONFIG_PPC_PREP */
2140 2294
2141
2142#ifdef CONFIG_PCI 2295#ifdef CONFIG_PCI
2143static int release_io_ports = 0; 2296static int release_io_ports;
2144 2297
2145/* Pulled the logic from XFree86 Cirrus driver to get the memory size, 2298/* Pulled the logic from XFree86 Cirrus driver to get the memory size,
2146 * based on the DRAM bandwidth bit and DRAM bank switching bit. This 2299 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
2147 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards 2300 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
2148 * seem to have. */ 2301 * seem to have. */
2149static unsigned int cirrusfb_get_memsize (u8 __iomem *regbase) 2302static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
2150{ 2303{
2151 unsigned long mem; 2304 unsigned long mem;
2152 unsigned char SRF; 2305 unsigned char SRF;
2153 2306
2154 DPRINTK ("ENTER\n"); 2307 DPRINTK("ENTER\n");
2155 2308
2156 SRF = vga_rseq (regbase, CL_SEQRF); 2309 SRF = vga_rseq(regbase, CL_SEQRF);
2157 switch ((SRF & 0x18)) { 2310 switch ((SRF & 0x18)) {
2158 case 0x08: mem = 512 * 1024; break; 2311 case 0x08:
2159 case 0x10: mem = 1024 * 1024; break; 2312 mem = 512 * 1024;
2160 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory 2313 break;
2161 * on the 5430. */ 2314 case 0x10:
2162 case 0x18: mem = 2048 * 1024; break; 2315 mem = 1024 * 1024;
2163 default: printk ("CLgenfb: Unknown memory size!\n"); 2316 break;
2317 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
2318 * on the 5430.
2319 */
2320 case 0x18:
2321 mem = 2048 * 1024;
2322 break;
2323 default:
2324 printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
2164 mem = 1024 * 1024; 2325 mem = 1024 * 1024;
2165 } 2326 }
2166 if (SRF & 0x80) { 2327 if (SRF & 0x80)
2167 /* If DRAM bank switching is enabled, there must be twice as much 2328 /* If DRAM bank switching is enabled, there must be twice as much
2168 * memory installed. (4MB on the 5434) */ 2329 * memory installed. (4MB on the 5434)
2330 */
2169 mem *= 2; 2331 mem *= 2;
2170 } 2332
2171 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */ 2333 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
2172 2334
2173 DPRINTK ("EXIT\n"); 2335 DPRINTK("EXIT\n");
2174 return mem; 2336 return mem;
2175} 2337}
2176 2338
2177 2339static void get_pci_addrs(const struct pci_dev *pdev,
2178 2340 unsigned long *display, unsigned long *registers)
2179static void get_pci_addrs (const struct pci_dev *pdev,
2180 unsigned long *display, unsigned long *registers)
2181{ 2341{
2182 assert (pdev != NULL); 2342 assert(pdev != NULL);
2183 assert (display != NULL); 2343 assert(display != NULL);
2184 assert (registers != NULL); 2344 assert(registers != NULL);
2185 2345
2186 DPRINTK ("ENTER\n"); 2346 DPRINTK("ENTER\n");
2187 2347
2188 *display = 0; 2348 *display = 0;
2189 *registers = 0; 2349 *registers = 0;
@@ -2198,13 +2358,12 @@ static void get_pci_addrs (const struct pci_dev *pdev,
2198 *registers = pci_resource_start(pdev, 1); 2358 *registers = pci_resource_start(pdev, 1);
2199 } 2359 }
2200 2360
2201 assert (*display != 0); 2361 assert(*display != 0);
2202 2362
2203 DPRINTK ("EXIT\n"); 2363 DPRINTK("EXIT\n");
2204} 2364}
2205 2365
2206 2366static void cirrusfb_pci_unmap(struct cirrusfb_info *cinfo)
2207static void cirrusfb_pci_unmap (struct cirrusfb_info *cinfo)
2208{ 2367{
2209 struct pci_dev *pdev = cinfo->pdev; 2368 struct pci_dev *pdev = cinfo->pdev;
2210 2369
@@ -2219,19 +2378,18 @@ static void cirrusfb_pci_unmap (struct cirrusfb_info *cinfo)
2219} 2378}
2220#endif /* CONFIG_PCI */ 2379#endif /* CONFIG_PCI */
2221 2380
2222
2223#ifdef CONFIG_ZORRO 2381#ifdef CONFIG_ZORRO
2224static void __devexit cirrusfb_zorro_unmap (struct cirrusfb_info *cinfo) 2382static void __devexit cirrusfb_zorro_unmap(struct cirrusfb_info *cinfo)
2225{ 2383{
2226 zorro_release_device(cinfo->zdev); 2384 zorro_release_device(cinfo->zdev);
2227 2385
2228 if (cinfo->btype == BT_PICASSO4) { 2386 if (cinfo->btype == BT_PICASSO4) {
2229 cinfo->regbase -= 0x600000; 2387 cinfo->regbase -= 0x600000;
2230 iounmap ((void *)cinfo->regbase); 2388 iounmap((void *)cinfo->regbase);
2231 iounmap ((void *)cinfo->fbmem); 2389 iounmap((void *)cinfo->fbmem);
2232 } else { 2390 } else {
2233 if (zorro_resource_start(cinfo->zdev) > 0x01000000) 2391 if (zorro_resource_start(cinfo->zdev) > 0x01000000)
2234 iounmap ((void *)cinfo->fbmem); 2392 iounmap((void *)cinfo->fbmem);
2235 } 2393 }
2236 framebuffer_release(cinfo->info); 2394 framebuffer_release(cinfo->info);
2237} 2395}
@@ -2267,7 +2425,8 @@ static int cirrusfb_set_fbinfo(struct cirrusfb_info *cinfo)
2267 /* monochrome: only 1 memory plane */ 2425 /* monochrome: only 1 memory plane */
2268 /* 8 bit and above: Use whole memory area */ 2426 /* 8 bit and above: Use whole memory area */
2269 info->fix.smem_start = cinfo->fbmem_phys; 2427 info->fix.smem_start = cinfo->fbmem_phys;
2270 info->fix.smem_len = (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size; 2428 info->fix.smem_len =
2429 (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
2271 info->fix.type = cinfo->currentmode.type; 2430 info->fix.type = cinfo->currentmode.type;
2272 info->fix.type_aux = 0; 2431 info->fix.type_aux = 0;
2273 info->fix.visual = cinfo->currentmode.visual; 2432 info->fix.visual = cinfo->currentmode.visual;
@@ -2292,17 +2451,18 @@ static int cirrusfb_register(struct cirrusfb_info *cinfo)
2292 int err; 2451 int err;
2293 cirrusfb_board_t btype; 2452 cirrusfb_board_t btype;
2294 2453
2295 DPRINTK ("ENTER\n"); 2454 DPRINTK("ENTER\n");
2296 2455
2297 printk (KERN_INFO "cirrusfb: Driver for Cirrus Logic based graphic boards, v" CIRRUSFB_VERSION "\n"); 2456 printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
2457 "graphic boards, v" CIRRUSFB_VERSION "\n");
2298 2458
2299 info = cinfo->info; 2459 info = cinfo->info;
2300 btype = cinfo->btype; 2460 btype = cinfo->btype;
2301 2461
2302 /* sanity checks */ 2462 /* sanity checks */
2303 assert (btype != BT_NONE); 2463 assert(btype != BT_NONE);
2304 2464
2305 DPRINTK ("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem); 2465 DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
2306 2466
2307 /* Make pretend we've set the var so our structures are in a "good" */ 2467 /* Make pretend we've set the var so our structures are in a "good" */
2308 /* state, even though we haven't written the mode to the hw yet... */ 2468 /* state, even though we haven't written the mode to the hw yet... */
@@ -2321,11 +2481,12 @@ static int cirrusfb_register(struct cirrusfb_info *cinfo)
2321 2481
2322 err = register_framebuffer(info); 2482 err = register_framebuffer(info);
2323 if (err < 0) { 2483 if (err < 0) {
2324 printk (KERN_ERR "cirrusfb: could not register fb device; err = %d!\n", err); 2484 printk(KERN_ERR "cirrusfb: could not register "
2485 "fb device; err = %d!\n", err);
2325 goto err_dealloc_cmap; 2486 goto err_dealloc_cmap;
2326 } 2487 }
2327 2488
2328 DPRINTK ("EXIT, returning 0\n"); 2489 DPRINTK("EXIT, returning 0\n");
2329 return 0; 2490 return 0;
2330 2491
2331err_dealloc_cmap: 2492err_dealloc_cmap:
@@ -2335,24 +2496,23 @@ err_unmap_cirrusfb:
2335 return err; 2496 return err;
2336} 2497}
2337 2498
2338static void __devexit cirrusfb_cleanup (struct fb_info *info) 2499static void __devexit cirrusfb_cleanup(struct fb_info *info)
2339{ 2500{
2340 struct cirrusfb_info *cinfo = info->par; 2501 struct cirrusfb_info *cinfo = info->par;
2341 DPRINTK ("ENTER\n"); 2502 DPRINTK("ENTER\n");
2342 2503
2343 switch_monitor (cinfo, 0); 2504 switch_monitor(cinfo, 0);
2344 2505
2345 unregister_framebuffer (info); 2506 unregister_framebuffer(info);
2346 fb_dealloc_cmap (&info->cmap); 2507 fb_dealloc_cmap(&info->cmap);
2347 printk ("Framebuffer unregistered\n"); 2508 printk("Framebuffer unregistered\n");
2348 cinfo->unmap(cinfo); 2509 cinfo->unmap(cinfo);
2349 2510
2350 DPRINTK ("EXIT\n"); 2511 DPRINTK("EXIT\n");
2351} 2512}
2352 2513
2353
2354#ifdef CONFIG_PCI 2514#ifdef CONFIG_PCI
2355static int cirrusfb_pci_register (struct pci_dev *pdev, 2515static int cirrusfb_pci_register(struct pci_dev *pdev,
2356 const struct pci_device_id *ent) 2516 const struct pci_device_id *ent)
2357{ 2517{
2358 struct cirrusfb_info *cinfo; 2518 struct cirrusfb_info *cinfo;
@@ -2379,31 +2539,34 @@ static int cirrusfb_pci_register (struct pci_dev *pdev,
2379 cinfo->pdev = pdev; 2539 cinfo->pdev = pdev;
2380 cinfo->btype = btype = (cirrusfb_board_t) ent->driver_data; 2540 cinfo->btype = btype = (cirrusfb_board_t) ent->driver_data;
2381 2541
2382 DPRINTK (" Found PCI device, base address 0 is 0x%lx, btype set to %d\n", 2542 DPRINTK(" Found PCI device, base address 0 is 0x%lx, btype set to %d\n",
2383 pdev->resource[0].start, btype); 2543 pdev->resource[0].start, btype);
2384 DPRINTK (" base address 1 is 0x%lx\n", pdev->resource[1].start); 2544 DPRINTK(" base address 1 is 0x%lx\n", pdev->resource[1].start);
2385 2545
2386 if(isPReP) { 2546 if (isPReP) {
2387 pci_write_config_dword (pdev, PCI_BASE_ADDRESS_0, 0x00000000); 2547 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2388#ifdef CONFIG_PPC_PREP 2548#ifdef CONFIG_PPC_PREP
2389 get_prep_addrs (&board_addr, &cinfo->fbregs_phys); 2549 get_prep_addrs(&board_addr, &cinfo->fbregs_phys);
2390#endif 2550#endif
2391 /* PReP dies if we ioremap the IO registers, but it works w/out... */ 2551 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2392 cinfo->regbase = (char __iomem *) cinfo->fbregs_phys; 2552 cinfo->regbase = (char __iomem *) cinfo->fbregs_phys;
2393 } else { 2553 } else {
2394 DPRINTK ("Attempt to get PCI info for Cirrus Graphics Card\n"); 2554 DPRINTK("Attempt to get PCI info for Cirrus Graphics Card\n");
2395 get_pci_addrs (pdev, &board_addr, &cinfo->fbregs_phys); 2555 get_pci_addrs(pdev, &board_addr, &cinfo->fbregs_phys);
2396 cinfo->regbase = NULL; /* FIXME: this forces VGA. alternatives? */ 2556 /* FIXME: this forces VGA. alternatives? */
2557 cinfo->regbase = NULL;
2397 } 2558 }
2398 2559
2399 DPRINTK ("Board address: 0x%lx, register address: 0x%lx\n", board_addr, cinfo->fbregs_phys); 2560 DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
2561 board_addr, cinfo->fbregs_phys);
2400 2562
2401 board_size = (btype == BT_GD5480) ? 2563 board_size = (btype == BT_GD5480) ?
2402 32 * MB_ : cirrusfb_get_memsize (cinfo->regbase); 2564 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
2403 2565
2404 ret = pci_request_regions(pdev, "cirrusfb"); 2566 ret = pci_request_regions(pdev, "cirrusfb");
2405 if (ret <0) { 2567 if (ret < 0) {
2406 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n", 2568 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2569 "abort\n",
2407 board_addr); 2570 board_addr);
2408 goto err_release_fb; 2571 goto err_release_fb;
2409 } 2572 }
@@ -2429,8 +2592,9 @@ static int cirrusfb_pci_register (struct pci_dev *pdev,
2429 cinfo->size = board_size; 2592 cinfo->size = board_size;
2430 cinfo->unmap = cirrusfb_pci_unmap; 2593 cinfo->unmap = cirrusfb_pci_unmap;
2431 2594
2432 printk (" RAM (%lu kB) at 0xx%lx, ", cinfo->size / KB_, board_addr); 2595 printk(KERN_INFO " RAM (%lu kB) at 0xx%lx, ",
2433 printk ("Cirrus Logic chipset on PCI bus\n"); 2596 cinfo->size / KB_, board_addr);
2597 printk(KERN_INFO "Cirrus Logic chipset on PCI bus\n");
2434 pci_set_drvdata(pdev, info); 2598 pci_set_drvdata(pdev, info);
2435 2599
2436 ret = cirrusfb_register(cinfo); 2600 ret = cirrusfb_register(cinfo);
@@ -2453,14 +2617,14 @@ err_out:
2453 return ret; 2617 return ret;
2454} 2618}
2455 2619
2456static void __devexit cirrusfb_pci_unregister (struct pci_dev *pdev) 2620static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2457{ 2621{
2458 struct fb_info *info = pci_get_drvdata(pdev); 2622 struct fb_info *info = pci_get_drvdata(pdev);
2459 DPRINTK ("ENTER\n"); 2623 DPRINTK("ENTER\n");
2460 2624
2461 cirrusfb_cleanup (info); 2625 cirrusfb_cleanup(info);
2462 2626
2463 DPRINTK ("EXIT\n"); 2627 DPRINTK("EXIT\n");
2464} 2628}
2465 2629
2466static struct pci_driver cirrusfb_pci_driver = { 2630static struct pci_driver cirrusfb_pci_driver = {
@@ -2477,7 +2641,6 @@ static struct pci_driver cirrusfb_pci_driver = {
2477}; 2641};
2478#endif /* CONFIG_PCI */ 2642#endif /* CONFIG_PCI */
2479 2643
2480
2481#ifdef CONFIG_ZORRO 2644#ifdef CONFIG_ZORRO
2482static int cirrusfb_zorro_register(struct zorro_dev *z, 2645static int cirrusfb_zorro_register(struct zorro_dev *z,
2483 const struct zorro_device_id *ent) 2646 const struct zorro_device_id *ent)
@@ -2498,7 +2661,7 @@ static int cirrusfb_zorro_register(struct zorro_dev *z,
2498 2661
2499 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev); 2662 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2500 if (!info) { 2663 if (!info) {
2501 printk (KERN_ERR "cirrusfb: could not allocate memory\n"); 2664 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2502 ret = -ENOMEM; 2665 ret = -ENOMEM;
2503 goto err_out; 2666 goto err_out;
2504 } 2667 }
@@ -2507,9 +2670,9 @@ static int cirrusfb_zorro_register(struct zorro_dev *z,
2507 cinfo->info = info; 2670 cinfo->info = info;
2508 cinfo->btype = btype; 2671 cinfo->btype = btype;
2509 2672
2510 assert (z > 0); 2673 assert(z > 0);
2511 assert (z2 >= 0); 2674 assert(z2 >= 0);
2512 assert (btype != BT_NONE); 2675 assert(btype != BT_NONE);
2513 2676
2514 cinfo->zdev = z; 2677 cinfo->zdev = z;
2515 board_addr = zorro_resource_start(z); 2678 board_addr = zorro_resource_start(z);
@@ -2517,55 +2680,59 @@ static int cirrusfb_zorro_register(struct zorro_dev *z,
2517 cinfo->size = size; 2680 cinfo->size = size;
2518 2681
2519 if (!zorro_request_device(z, "cirrusfb")) { 2682 if (!zorro_request_device(z, "cirrusfb")) {
2520 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n", 2683 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2684 "abort\n",
2521 board_addr); 2685 board_addr);
2522 ret = -EBUSY; 2686 ret = -EBUSY;
2523 goto err_release_fb; 2687 goto err_release_fb;
2524 } 2688 }
2525 2689
2526 printk (" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr); 2690 printk(" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
2527 2691
2528 ret = -EIO; 2692 ret = -EIO;
2529 2693
2530 if (btype == BT_PICASSO4) { 2694 if (btype == BT_PICASSO4) {
2531 printk (" REG at $%lx\n", board_addr + 0x600000); 2695 printk(KERN_INFO " REG at $%lx\n", board_addr + 0x600000);
2532 2696
2533 /* To be precise, for the P4 this is not the */ 2697 /* To be precise, for the P4 this is not the */
2534 /* begin of the board, but the begin of RAM. */ 2698 /* begin of the board, but the begin of RAM. */
2535 /* for P4, map in its address space in 2 chunks (### TEST! ) */ 2699 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2536 /* (note the ugly hardcoded 16M number) */ 2700 /* (note the ugly hardcoded 16M number) */
2537 cinfo->regbase = ioremap (board_addr, 16777216); 2701 cinfo->regbase = ioremap(board_addr, 16777216);
2538 if (!cinfo->regbase) 2702 if (!cinfo->regbase)
2539 goto err_release_region; 2703 goto err_release_region;
2540 2704
2541 DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase); 2705 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2706 cinfo->regbase);
2542 cinfo->regbase += 0x600000; 2707 cinfo->regbase += 0x600000;
2543 cinfo->fbregs_phys = board_addr + 0x600000; 2708 cinfo->fbregs_phys = board_addr + 0x600000;
2544 2709
2545 cinfo->fbmem_phys = board_addr + 16777216; 2710 cinfo->fbmem_phys = board_addr + 16777216;
2546 cinfo->fbmem = ioremap (cinfo->fbmem_phys, 16777216); 2711 cinfo->fbmem = ioremap(cinfo->fbmem_phys, 16777216);
2547 if (!cinfo->fbmem) 2712 if (!cinfo->fbmem)
2548 goto err_unmap_regbase; 2713 goto err_unmap_regbase;
2549 } else { 2714 } else {
2550 printk (" REG at $%lx\n", (unsigned long) z2->resource.start); 2715 printk(KERN_INFO " REG at $%lx\n",
2716 (unsigned long) z2->resource.start);
2551 2717
2552 cinfo->fbmem_phys = board_addr; 2718 cinfo->fbmem_phys = board_addr;
2553 if (board_addr > 0x01000000) 2719 if (board_addr > 0x01000000)
2554 cinfo->fbmem = ioremap (board_addr, board_size); 2720 cinfo->fbmem = ioremap(board_addr, board_size);
2555 else 2721 else
2556 cinfo->fbmem = (caddr_t) ZTWO_VADDR (board_addr); 2722 cinfo->fbmem = (caddr_t) ZTWO_VADDR(board_addr);
2557 if (!cinfo->fbmem) 2723 if (!cinfo->fbmem)
2558 goto err_release_region; 2724 goto err_release_region;
2559 2725
2560 /* set address for REG area of board */ 2726 /* set address for REG area of board */
2561 cinfo->regbase = (caddr_t) ZTWO_VADDR (z2->resource.start); 2727 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2562 cinfo->fbregs_phys = z2->resource.start; 2728 cinfo->fbregs_phys = z2->resource.start;
2563 2729
2564 DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase); 2730 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2731 cinfo->regbase);
2565 } 2732 }
2566 cinfo->unmap = cirrusfb_zorro_unmap; 2733 cinfo->unmap = cirrusfb_zorro_unmap;
2567 2734
2568 printk (KERN_INFO "Cirrus Logic chipset on Zorro bus\n"); 2735 printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
2569 zorro_set_drvdata(z, info); 2736 zorro_set_drvdata(z, info);
2570 2737
2571 ret = cirrusfb_register(cinfo); 2738 ret = cirrusfb_register(cinfo);
@@ -2592,11 +2759,11 @@ err_out:
2592void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z) 2759void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2593{ 2760{
2594 struct fb_info *info = zorro_get_drvdata(z); 2761 struct fb_info *info = zorro_get_drvdata(z);
2595 DPRINTK ("ENTER\n"); 2762 DPRINTK("ENTER\n");
2596 2763
2597 cirrusfb_cleanup (info); 2764 cirrusfb_cleanup(info);
2598 2765
2599 DPRINTK ("EXIT\n"); 2766 DPRINTK("EXIT\n");
2600} 2767}
2601 2768
2602static struct zorro_driver cirrusfb_zorro_driver = { 2769static struct zorro_driver cirrusfb_zorro_driver = {
@@ -2628,26 +2795,24 @@ static int __init cirrusfb_init(void)
2628 return error; 2795 return error;
2629} 2796}
2630 2797
2631
2632
2633#ifndef MODULE 2798#ifndef MODULE
2634static int __init cirrusfb_setup(char *options) { 2799static int __init cirrusfb_setup(char *options) {
2635 char *this_opt, s[32]; 2800 char *this_opt, s[32];
2636 int i; 2801 int i;
2637 2802
2638 DPRINTK ("ENTER\n"); 2803 DPRINTK("ENTER\n");
2639 2804
2640 if (!options || !*options) 2805 if (!options || !*options)
2641 return 0; 2806 return 0;
2642 2807
2643 while ((this_opt = strsep (&options, ",")) != NULL) { 2808 while ((this_opt = strsep(&options, ",")) != NULL) {
2644 if (!*this_opt) continue; 2809 if (!*this_opt) continue;
2645 2810
2646 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt); 2811 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
2647 2812
2648 for (i = 0; i < NUM_TOTAL_MODES; i++) { 2813 for (i = 0; i < NUM_TOTAL_MODES; i++) {
2649 sprintf (s, "mode:%s", cirrusfb_predefined[i].name); 2814 sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
2650 if (strcmp (this_opt, s) == 0) 2815 if (strcmp(this_opt, s) == 0)
2651 cirrusfb_def_mode = i; 2816 cirrusfb_def_mode = i;
2652 } 2817 }
2653 if (!strcmp(this_opt, "noaccel")) 2818 if (!strcmp(this_opt, "noaccel"))
@@ -2657,7 +2822,6 @@ static int __init cirrusfb_setup(char *options) {
2657} 2822}
2658#endif 2823#endif
2659 2824
2660
2661 /* 2825 /*
2662 * Modularization 2826 * Modularization
2663 */ 2827 */
@@ -2666,7 +2830,7 @@ MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2666MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips"); 2830MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2667MODULE_LICENSE("GPL"); 2831MODULE_LICENSE("GPL");
2668 2832
2669static void __exit cirrusfb_exit (void) 2833static void __exit cirrusfb_exit(void)
2670{ 2834{
2671#ifdef CONFIG_PCI 2835#ifdef CONFIG_PCI
2672 pci_unregister_driver(&cirrusfb_pci_driver); 2836 pci_unregister_driver(&cirrusfb_pci_driver);
@@ -2682,66 +2846,67 @@ module_init(cirrusfb_init);
2682module_exit(cirrusfb_exit); 2846module_exit(cirrusfb_exit);
2683#endif 2847#endif
2684 2848
2685
2686/**********************************************************************/ 2849/**********************************************************************/
2687/* about the following functions - I have used the same names for the */ 2850/* about the following functions - I have used the same names for the */
2688/* functions as Markus Wild did in his Retina driver for NetBSD as */ 2851/* functions as Markus Wild did in his Retina driver for NetBSD as */
2689/* they just made sense for this purpose. Apart from that, I wrote */ 2852/* they just made sense for this purpose. Apart from that, I wrote */
2690/* these functions myself. */ 2853/* these functions myself. */
2691/**********************************************************************/ 2854/**********************************************************************/
2692 2855
2693/*** WGen() - write into one of the external/general registers ***/ 2856/*** WGen() - write into one of the external/general registers ***/
2694static void WGen (const struct cirrusfb_info *cinfo, 2857static void WGen(const struct cirrusfb_info *cinfo,
2695 int regnum, unsigned char val) 2858 int regnum, unsigned char val)
2696{ 2859{
2697 unsigned long regofs = 0; 2860 unsigned long regofs = 0;
2698 2861
2699 if (cinfo->btype == BT_PICASSO) { 2862 if (cinfo->btype == BT_PICASSO) {
2700 /* Picasso II specific hack */ 2863 /* Picasso II specific hack */
2701/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */ 2864/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2865 regnum == CL_VSSM2) */
2702 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D) 2866 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2703 regofs = 0xfff; 2867 regofs = 0xfff;
2704 } 2868 }
2705 2869
2706 vga_w (cinfo->regbase, regofs + regnum, val); 2870 vga_w(cinfo->regbase, regofs + regnum, val);
2707} 2871}
2708 2872
2709/*** RGen() - read out one of the external/general registers ***/ 2873/*** RGen() - read out one of the external/general registers ***/
2710static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum) 2874static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2711{ 2875{
2712 unsigned long regofs = 0; 2876 unsigned long regofs = 0;
2713 2877
2714 if (cinfo->btype == BT_PICASSO) { 2878 if (cinfo->btype == BT_PICASSO) {
2715 /* Picasso II specific hack */ 2879 /* Picasso II specific hack */
2716/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */ 2880/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2881 regnum == CL_VSSM2) */
2717 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D) 2882 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2718 regofs = 0xfff; 2883 regofs = 0xfff;
2719 } 2884 }
2720 2885
2721 return vga_r (cinfo->regbase, regofs + regnum); 2886 return vga_r(cinfo->regbase, regofs + regnum);
2722} 2887}
2723 2888
2724/*** AttrOn() - turn on VideoEnable for Attribute controller ***/ 2889/*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2725static void AttrOn (const struct cirrusfb_info *cinfo) 2890static void AttrOn(const struct cirrusfb_info *cinfo)
2726{ 2891{
2727 assert (cinfo != NULL); 2892 assert(cinfo != NULL);
2728 2893
2729 DPRINTK ("ENTER\n"); 2894 DPRINTK("ENTER\n");
2730 2895
2731 if (vga_rcrt (cinfo->regbase, CL_CRT24) & 0x80) { 2896 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2732 /* if we're just in "write value" mode, write back the */ 2897 /* if we're just in "write value" mode, write back the */
2733 /* same value as before to not modify anything */ 2898 /* same value as before to not modify anything */
2734 vga_w (cinfo->regbase, VGA_ATT_IW, 2899 vga_w(cinfo->regbase, VGA_ATT_IW,
2735 vga_r (cinfo->regbase, VGA_ATT_R)); 2900 vga_r(cinfo->regbase, VGA_ATT_R));
2736 } 2901 }
2737 /* turn on video bit */ 2902 /* turn on video bit */
2738/* vga_w (cinfo->regbase, VGA_ATT_IW, 0x20); */ 2903/* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2739 vga_w (cinfo->regbase, VGA_ATT_IW, 0x33); 2904 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2740 2905
2741 /* dummy write on Reg0 to be on "write index" mode next time */ 2906 /* dummy write on Reg0 to be on "write index" mode next time */
2742 vga_w (cinfo->regbase, VGA_ATT_IW, 0x00); 2907 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2743 2908
2744 DPRINTK ("EXIT\n"); 2909 DPRINTK("EXIT\n");
2745} 2910}
2746 2911
2747/*** WHDR() - write into the Hidden DAC register ***/ 2912/*** WHDR() - write into the Hidden DAC register ***/
@@ -2750,119 +2915,115 @@ static void AttrOn (const struct cirrusfb_info *cinfo)
2750 * registers of their functional group) here is a specialized routine for 2915 * registers of their functional group) here is a specialized routine for
2751 * accessing the HDR 2916 * accessing the HDR
2752 */ 2917 */
2753static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val) 2918static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2754{ 2919{
2755 unsigned char dummy; 2920 unsigned char dummy;
2756 2921
2757 if (cinfo->btype == BT_PICASSO) { 2922 if (cinfo->btype == BT_PICASSO) {
2758 /* Klaus' hint for correct access to HDR on some boards */ 2923 /* Klaus' hint for correct access to HDR on some boards */
2759 /* first write 0 to pixel mask (3c6) */ 2924 /* first write 0 to pixel mask (3c6) */
2760 WGen (cinfo, VGA_PEL_MSK, 0x00); 2925 WGen(cinfo, VGA_PEL_MSK, 0x00);
2761 udelay (200); 2926 udelay(200);
2762 /* next read dummy from pixel address (3c8) */ 2927 /* next read dummy from pixel address (3c8) */
2763 dummy = RGen (cinfo, VGA_PEL_IW); 2928 dummy = RGen(cinfo, VGA_PEL_IW);
2764 udelay (200); 2929 udelay(200);
2765 } 2930 }
2766 /* now do the usual stuff to access the HDR */ 2931 /* now do the usual stuff to access the HDR */
2767 2932
2768 dummy = RGen (cinfo, VGA_PEL_MSK); 2933 dummy = RGen(cinfo, VGA_PEL_MSK);
2769 udelay (200); 2934 udelay(200);
2770 dummy = RGen (cinfo, VGA_PEL_MSK); 2935 dummy = RGen(cinfo, VGA_PEL_MSK);
2771 udelay (200); 2936 udelay(200);
2772 dummy = RGen (cinfo, VGA_PEL_MSK); 2937 dummy = RGen(cinfo, VGA_PEL_MSK);
2773 udelay (200); 2938 udelay(200);
2774 dummy = RGen (cinfo, VGA_PEL_MSK); 2939 dummy = RGen(cinfo, VGA_PEL_MSK);
2775 udelay (200); 2940 udelay(200);
2776 2941
2777 WGen (cinfo, VGA_PEL_MSK, val); 2942 WGen(cinfo, VGA_PEL_MSK, val);
2778 udelay (200); 2943 udelay(200);
2779 2944
2780 if (cinfo->btype == BT_PICASSO) { 2945 if (cinfo->btype == BT_PICASSO) {
2781 /* now first reset HDR access counter */ 2946 /* now first reset HDR access counter */
2782 dummy = RGen (cinfo, VGA_PEL_IW); 2947 dummy = RGen(cinfo, VGA_PEL_IW);
2783 udelay (200); 2948 udelay(200);
2784 2949
2785 /* and at the end, restore the mask value */ 2950 /* and at the end, restore the mask value */
2786 /* ## is this mask always 0xff? */ 2951 /* ## is this mask always 0xff? */
2787 WGen (cinfo, VGA_PEL_MSK, 0xff); 2952 WGen(cinfo, VGA_PEL_MSK, 0xff);
2788 udelay (200); 2953 udelay(200);
2789 } 2954 }
2790} 2955}
2791 2956
2792
2793/*** WSFR() - write to the "special function register" (SFR) ***/ 2957/*** WSFR() - write to the "special function register" (SFR) ***/
2794static void WSFR (struct cirrusfb_info *cinfo, unsigned char val) 2958static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2795{ 2959{
2796#ifdef CONFIG_ZORRO 2960#ifdef CONFIG_ZORRO
2797 assert (cinfo->regbase != NULL); 2961 assert(cinfo->regbase != NULL);
2798 cinfo->SFR = val; 2962 cinfo->SFR = val;
2799 z_writeb (val, cinfo->regbase + 0x8000); 2963 z_writeb(val, cinfo->regbase + 0x8000);
2800#endif 2964#endif
2801} 2965}
2802 2966
2803/* The Picasso has a second register for switching the monitor bit */ 2967/* The Picasso has a second register for switching the monitor bit */
2804static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val) 2968static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2805{ 2969{
2806#ifdef CONFIG_ZORRO 2970#ifdef CONFIG_ZORRO
2807 /* writing an arbitrary value to this one causes the monitor switcher */ 2971 /* writing an arbitrary value to this one causes the monitor switcher */
2808 /* to flip to Amiga display */ 2972 /* to flip to Amiga display */
2809 assert (cinfo->regbase != NULL); 2973 assert(cinfo->regbase != NULL);
2810 cinfo->SFR = val; 2974 cinfo->SFR = val;
2811 z_writeb (val, cinfo->regbase + 0x9000); 2975 z_writeb(val, cinfo->regbase + 0x9000);
2812#endif 2976#endif
2813} 2977}
2814 2978
2815
2816/*** WClut - set CLUT entry (range: 0..63) ***/ 2979/*** WClut - set CLUT entry (range: 0..63) ***/
2817static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red, 2980static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2818 unsigned char green, unsigned char blue) 2981 unsigned char green, unsigned char blue)
2819{ 2982{
2820 unsigned int data = VGA_PEL_D; 2983 unsigned int data = VGA_PEL_D;
2821 2984
2822 /* address write mode register is not translated.. */ 2985 /* address write mode register is not translated.. */
2823 vga_w (cinfo->regbase, VGA_PEL_IW, regnum); 2986 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2824 2987
2825 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || 2988 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2826 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) { 2989 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2827 /* but DAC data register IS, at least for Picasso II */ 2990 /* but DAC data register IS, at least for Picasso II */
2828 if (cinfo->btype == BT_PICASSO) 2991 if (cinfo->btype == BT_PICASSO)
2829 data += 0xfff; 2992 data += 0xfff;
2830 vga_w (cinfo->regbase, data, red); 2993 vga_w(cinfo->regbase, data, red);
2831 vga_w (cinfo->regbase, data, green); 2994 vga_w(cinfo->regbase, data, green);
2832 vga_w (cinfo->regbase, data, blue); 2995 vga_w(cinfo->regbase, data, blue);
2833 } else { 2996 } else {
2834 vga_w (cinfo->regbase, data, blue); 2997 vga_w(cinfo->regbase, data, blue);
2835 vga_w (cinfo->regbase, data, green); 2998 vga_w(cinfo->regbase, data, green);
2836 vga_w (cinfo->regbase, data, red); 2999 vga_w(cinfo->regbase, data, red);
2837 } 3000 }
2838} 3001}
2839 3002
2840
2841#if 0 3003#if 0
2842/*** RClut - read CLUT entry (range 0..63) ***/ 3004/*** RClut - read CLUT entry (range 0..63) ***/
2843static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red, 3005static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2844 unsigned char *green, unsigned char *blue) 3006 unsigned char *green, unsigned char *blue)
2845{ 3007{
2846 unsigned int data = VGA_PEL_D; 3008 unsigned int data = VGA_PEL_D;
2847 3009
2848 vga_w (cinfo->regbase, VGA_PEL_IR, regnum); 3010 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2849 3011
2850 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || 3012 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2851 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) { 3013 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2852 if (cinfo->btype == BT_PICASSO) 3014 if (cinfo->btype == BT_PICASSO)
2853 data += 0xfff; 3015 data += 0xfff;
2854 *red = vga_r (cinfo->regbase, data); 3016 *red = vga_r(cinfo->regbase, data);
2855 *green = vga_r (cinfo->regbase, data); 3017 *green = vga_r(cinfo->regbase, data);
2856 *blue = vga_r (cinfo->regbase, data); 3018 *blue = vga_r(cinfo->regbase, data);
2857 } else { 3019 } else {
2858 *blue = vga_r (cinfo->regbase, data); 3020 *blue = vga_r(cinfo->regbase, data);
2859 *green = vga_r (cinfo->regbase, data); 3021 *green = vga_r(cinfo->regbase, data);
2860 *red = vga_r (cinfo->regbase, data); 3022 *red = vga_r(cinfo->regbase, data);
2861 } 3023 }
2862} 3024}
2863#endif 3025#endif
2864 3026
2865
2866/******************************************************************* 3027/*******************************************************************
2867 cirrusfb_WaitBLT() 3028 cirrusfb_WaitBLT()
2868 3029
@@ -2870,10 +3031,10 @@ static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned c
2870*********************************************************************/ 3031*********************************************************************/
2871 3032
2872/* FIXME: use interrupts instead */ 3033/* FIXME: use interrupts instead */
2873static void cirrusfb_WaitBLT (u8 __iomem *regbase) 3034static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2874{ 3035{
2875 /* now busy-wait until we're done */ 3036 /* now busy-wait until we're done */
2876 while (vga_rgfx (regbase, CL_GR31) & 0x08) 3037 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2877 /* do nothing */ ; 3038 /* do nothing */ ;
2878} 3039}
2879 3040
@@ -2883,15 +3044,17 @@ static void cirrusfb_WaitBLT (u8 __iomem *regbase)
2883 perform accelerated "scrolling" 3044 perform accelerated "scrolling"
2884********************************************************************/ 3045********************************************************************/
2885 3046
2886static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel, 3047static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2887 u_short curx, u_short cury, u_short destx, u_short desty, 3048 u_short curx, u_short cury,
2888 u_short width, u_short height, u_short line_length) 3049 u_short destx, u_short desty,
3050 u_short width, u_short height,
3051 u_short line_length)
2889{ 3052{
2890 u_short nwidth, nheight; 3053 u_short nwidth, nheight;
2891 u_long nsrc, ndest; 3054 u_long nsrc, ndest;
2892 u_char bltmode; 3055 u_char bltmode;
2893 3056
2894 DPRINTK ("ENTER\n"); 3057 DPRINTK("ENTER\n");
2895 3058
2896 nwidth = width - 1; 3059 nwidth = width - 1;
2897 nheight = height - 1; 3060 nheight = height - 1;
@@ -2911,9 +3074,13 @@ static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
2911 nsrc = (cury * line_length) + curx; 3074 nsrc = (cury * line_length) + curx;
2912 ndest = (desty * line_length) + destx; 3075 ndest = (desty * line_length) + destx;
2913 } else { 3076 } else {
2914 /* this means start addresses are at the end, counting backwards */ 3077 /* this means start addresses are at the end,
2915 nsrc = cury * line_length + curx + nheight * line_length + nwidth; 3078 * counting backwards
2916 ndest = desty * line_length + destx + nheight * line_length + nwidth; 3079 */
3080 nsrc = cury * line_length + curx +
3081 nheight * line_length + nwidth;
3082 ndest = desty * line_length + destx +
3083 nheight * line_length + nwidth;
2917 } 3084 }
2918 3085
2919 /* 3086 /*
@@ -2929,52 +3096,65 @@ static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
2929 start/stop 3096 start/stop
2930 */ 3097 */
2931 3098
2932 cirrusfb_WaitBLT(regbase); 3099 cirrusfb_WaitBLT(regbase);
2933 3100
2934 /* pitch: set to line_length */ 3101 /* pitch: set to line_length */
2935 vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */ 3102 /* dest pitch low */
2936 vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */ 3103 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2937 vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */ 3104 /* dest pitch hi */
2938 vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */ 3105 vga_wgfx(regbase, CL_GR25, line_length >> 8);
3106 /* source pitch low */
3107 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
3108 /* source pitch hi */
3109 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2939 3110
2940 /* BLT width: actual number of pixels - 1 */ 3111 /* BLT width: actual number of pixels - 1 */
2941 vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */ 3112 /* BLT width low */
2942 vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */ 3113 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
3114 /* BLT width hi */
3115 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2943 3116
2944 /* BLT height: actual number of lines -1 */ 3117 /* BLT height: actual number of lines -1 */
2945 vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */ 3118 /* BLT height low */
2946 vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */ 3119 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
3120 /* BLT width hi */
3121 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2947 3122
2948 /* BLT destination */ 3123 /* BLT destination */
2949 vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */ 3124 /* BLT dest low */
2950 vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */ 3125 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2951 vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */ 3126 /* BLT dest mid */
3127 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3128 /* BLT dest hi */
3129 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2952 3130
2953 /* BLT source */ 3131 /* BLT source */
2954 vga_wgfx (regbase, CL_GR2C, (u_char) (nsrc & 0xff)); /* BLT src low */ 3132 /* BLT src low */
2955 vga_wgfx (regbase, CL_GR2D, (u_char) (nsrc >> 8)); /* BLT src mid */ 3133 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2956 vga_wgfx (regbase, CL_GR2E, (u_char) (nsrc >> 16)); /* BLT src hi */ 3134 /* BLT src mid */
3135 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
3136 /* BLT src hi */
3137 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2957 3138
2958 /* BLT mode */ 3139 /* BLT mode */
2959 vga_wgfx (regbase, CL_GR30, bltmode); /* BLT mode */ 3140 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2960 3141
2961 /* BLT ROP: SrcCopy */ 3142 /* BLT ROP: SrcCopy */
2962 vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */ 3143 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2963 3144
2964 /* and finally: GO! */ 3145 /* and finally: GO! */
2965 vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */ 3146 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2966 3147
2967 DPRINTK ("EXIT\n"); 3148 DPRINTK("EXIT\n");
2968} 3149}
2969 3150
2970
2971/******************************************************************* 3151/*******************************************************************
2972 cirrusfb_RectFill() 3152 cirrusfb_RectFill()
2973 3153
2974 perform accelerated rectangle fill 3154 perform accelerated rectangle fill
2975********************************************************************/ 3155********************************************************************/
2976 3156
2977static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel, 3157static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2978 u_short x, u_short y, u_short width, u_short height, 3158 u_short x, u_short y, u_short width, u_short height,
2979 u_char color, u_short line_length) 3159 u_char color, u_short line_length)
2980{ 3160{
@@ -2982,93 +3162,95 @@ static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel,
2982 u_long ndest; 3162 u_long ndest;
2983 u_char op; 3163 u_char op;
2984 3164
2985 DPRINTK ("ENTER\n"); 3165 DPRINTK("ENTER\n");
2986 3166
2987 nwidth = width - 1; 3167 nwidth = width - 1;
2988 nheight = height - 1; 3168 nheight = height - 1;
2989 3169
2990 ndest = (y * line_length) + x; 3170 ndest = (y * line_length) + x;
2991 3171
2992 cirrusfb_WaitBLT(regbase); 3172 cirrusfb_WaitBLT(regbase);
2993 3173
2994 /* pitch: set to line_length */ 3174 /* pitch: set to line_length */
2995 vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */ 3175 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2996 vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */ 3176 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
2997 vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */ 3177 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2998 vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */ 3178 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
2999 3179
3000 /* BLT width: actual number of pixels - 1 */ 3180 /* BLT width: actual number of pixels - 1 */
3001 vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */ 3181 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
3002 vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */ 3182 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
3003 3183
3004 /* BLT height: actual number of lines -1 */ 3184 /* BLT height: actual number of lines -1 */
3005 vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */ 3185 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
3006 vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */ 3186 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
3007 3187
3008 /* BLT destination */ 3188 /* BLT destination */
3009 vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */ 3189 /* BLT dest low */
3010 vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */ 3190 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
3011 vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */ 3191 /* BLT dest mid */
3192 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3193 /* BLT dest hi */
3194 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
3012 3195
3013 /* BLT source: set to 0 (is a dummy here anyway) */ 3196 /* BLT source: set to 0 (is a dummy here anyway) */
3014 vga_wgfx (regbase, CL_GR2C, 0x00); /* BLT src low */ 3197 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
3015 vga_wgfx (regbase, CL_GR2D, 0x00); /* BLT src mid */ 3198 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
3016 vga_wgfx (regbase, CL_GR2E, 0x00); /* BLT src hi */ 3199 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
3017 3200
3018 /* This is a ColorExpand Blt, using the */ 3201 /* This is a ColorExpand Blt, using the */
3019 /* same color for foreground and background */ 3202 /* same color for foreground and background */
3020 vga_wgfx (regbase, VGA_GFX_SR_VALUE, color); /* foreground color */ 3203 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
3021 vga_wgfx (regbase, VGA_GFX_SR_ENABLE, color); /* background color */ 3204 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
3022 3205
3023 op = 0xc0; 3206 op = 0xc0;
3024 if (bits_per_pixel == 16) { 3207 if (bits_per_pixel == 16) {
3025 vga_wgfx (regbase, CL_GR10, color); /* foreground color */ 3208 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3026 vga_wgfx (regbase, CL_GR11, color); /* background color */ 3209 vga_wgfx(regbase, CL_GR11, color); /* background color */
3027 op = 0x50; 3210 op = 0x50;
3028 op = 0xd0; 3211 op = 0xd0;
3029 } else if (bits_per_pixel == 32) { 3212 } else if (bits_per_pixel == 32) {
3030 vga_wgfx (regbase, CL_GR10, color); /* foreground color */ 3213 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3031 vga_wgfx (regbase, CL_GR11, color); /* background color */ 3214 vga_wgfx(regbase, CL_GR11, color); /* background color */
3032 vga_wgfx (regbase, CL_GR12, color); /* foreground color */ 3215 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
3033 vga_wgfx (regbase, CL_GR13, color); /* background color */ 3216 vga_wgfx(regbase, CL_GR13, color); /* background color */
3034 vga_wgfx (regbase, CL_GR14, 0); /* foreground color */ 3217 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
3035 vga_wgfx (regbase, CL_GR15, 0); /* background color */ 3218 vga_wgfx(regbase, CL_GR15, 0); /* background color */
3036 op = 0x50; 3219 op = 0x50;
3037 op = 0xf0; 3220 op = 0xf0;
3038 } 3221 }
3039 /* BLT mode: color expand, Enable 8x8 copy (faster?) */ 3222 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
3040 vga_wgfx (regbase, CL_GR30, op); /* BLT mode */ 3223 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
3041 3224
3042 /* BLT ROP: SrcCopy */ 3225 /* BLT ROP: SrcCopy */
3043 vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */ 3226 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
3044 3227
3045 /* and finally: GO! */ 3228 /* and finally: GO! */
3046 vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */ 3229 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3047 3230
3048 DPRINTK ("EXIT\n"); 3231 DPRINTK("EXIT\n");
3049} 3232}
3050 3233
3051
3052/************************************************************************** 3234/**************************************************************************
3053 * bestclock() - determine closest possible clock lower(?) than the 3235 * bestclock() - determine closest possible clock lower(?) than the
3054 * desired pixel clock 3236 * desired pixel clock
3055 **************************************************************************/ 3237 **************************************************************************/
3056static void bestclock (long freq, long *best, long *nom, 3238static void bestclock(long freq, long *best, long *nom,
3057 long *den, long *div, long maxfreq) 3239 long *den, long *div, long maxfreq)
3058{ 3240{
3059 long n, h, d, f; 3241 long n, h, d, f;
3060 3242
3061 assert (best != NULL); 3243 assert(best != NULL);
3062 assert (nom != NULL); 3244 assert(nom != NULL);
3063 assert (den != NULL); 3245 assert(den != NULL);
3064 assert (div != NULL); 3246 assert(div != NULL);
3065 assert (maxfreq > 0); 3247 assert(maxfreq > 0);
3066 3248
3067 *nom = 0; 3249 *nom = 0;
3068 *den = 0; 3250 *den = 0;
3069 *div = 0; 3251 *div = 0;
3070 3252
3071 DPRINTK ("ENTER\n"); 3253 DPRINTK("ENTER\n");
3072 3254
3073 if (freq < 8000) 3255 if (freq < 8000)
3074 freq = 8000; 3256 freq = 8000;
@@ -3085,7 +3267,7 @@ static void bestclock (long freq, long *best, long *nom,
3085 if (d > 31) 3267 if (d > 31)
3086 d = (d / 2) * 2; 3268 d = (d / 2) * 2;
3087 h = (14318 * n) / d; 3269 h = (14318 * n) / d;
3088 if (abs (h - freq) < abs (*best - freq)) { 3270 if (abs(h - freq) < abs(*best - freq)) {
3089 *best = h; 3271 *best = h;
3090 *nom = n; 3272 *nom = n;
3091 if (d < 32) { 3273 if (d < 32) {
@@ -3102,7 +3284,7 @@ static void bestclock (long freq, long *best, long *nom,
3102 if (d > 31) 3284 if (d > 31)
3103 d = (d / 2) * 2; 3285 d = (d / 2) * 2;
3104 h = (14318 * n) / d; 3286 h = (14318 * n) / d;
3105 if (abs (h - freq) < abs (*best - freq)) { 3287 if (abs(h - freq) < abs(*best - freq)) {
3106 *best = h; 3288 *best = h;
3107 *nom = n; 3289 *nom = n;
3108 if (d < 32) { 3290 if (d < 32) {
@@ -3116,14 +3298,13 @@ static void bestclock (long freq, long *best, long *nom,
3116 } 3298 }
3117 } 3299 }
3118 3300
3119 DPRINTK ("Best possible values for given frequency:\n"); 3301 DPRINTK("Best possible values for given frequency:\n");
3120 DPRINTK (" best: %ld kHz nom: %ld den: %ld div: %ld\n", 3302 DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %ld\n",
3121 freq, *nom, *den, *div); 3303 freq, *nom, *den, *div);
3122 3304
3123 DPRINTK ("EXIT\n"); 3305 DPRINTK("EXIT\n");
3124} 3306}
3125 3307
3126
3127/* ------------------------------------------------------------------------- 3308/* -------------------------------------------------------------------------
3128 * 3309 *
3129 * debugging functions 3310 * debugging functions
@@ -3145,21 +3326,20 @@ static void bestclock (long freq, long *best, long *nom,
3145 */ 3326 */
3146 3327
3147static 3328static
3148void cirrusfb_dbg_print_byte (const char *name, unsigned char val) 3329void cirrusfb_dbg_print_byte(const char *name, unsigned char val)
3149{ 3330{
3150 DPRINTK ("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n", 3331 DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
3151 name, val, 3332 name, val,
3152 val & 0x80 ? '1' : '0', 3333 val & 0x80 ? '1' : '0',
3153 val & 0x40 ? '1' : '0', 3334 val & 0x40 ? '1' : '0',
3154 val & 0x20 ? '1' : '0', 3335 val & 0x20 ? '1' : '0',
3155 val & 0x10 ? '1' : '0', 3336 val & 0x10 ? '1' : '0',
3156 val & 0x08 ? '1' : '0', 3337 val & 0x08 ? '1' : '0',
3157 val & 0x04 ? '1' : '0', 3338 val & 0x04 ? '1' : '0',
3158 val & 0x02 ? '1' : '0', 3339 val & 0x02 ? '1' : '0',
3159 val & 0x01 ? '1' : '0'); 3340 val & 0x01 ? '1' : '0');
3160} 3341}
3161 3342
3162
3163/** 3343/**
3164 * cirrusfb_dbg_print_regs 3344 * cirrusfb_dbg_print_regs
3165 * @base: If using newmmio, the newmmio base address, otherwise %NULL 3345 * @base: If using newmmio, the newmmio base address, otherwise %NULL
@@ -3172,25 +3352,26 @@ void cirrusfb_dbg_print_byte (const char *name, unsigned char val)
3172 */ 3352 */
3173 3353
3174static 3354static
3175void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...) 3355void cirrusfb_dbg_print_regs(caddr_t regbase,
3356 cirrusfb_dbg_reg_class_t reg_class, ...)
3176{ 3357{
3177 va_list list; 3358 va_list list;
3178 unsigned char val = 0; 3359 unsigned char val = 0;
3179 unsigned reg; 3360 unsigned reg;
3180 char *name; 3361 char *name;
3181 3362
3182 va_start (list, reg_class); 3363 va_start(list, reg_class);
3183 3364
3184 name = va_arg (list, char *); 3365 name = va_arg(list, char *);
3185 while (name != NULL) { 3366 while (name != NULL) {
3186 reg = va_arg (list, int); 3367 reg = va_arg(list, int);
3187 3368
3188 switch (reg_class) { 3369 switch (reg_class) {
3189 case CRT: 3370 case CRT:
3190 val = vga_rcrt (regbase, (unsigned char) reg); 3371 val = vga_rcrt(regbase, (unsigned char) reg);
3191 break; 3372 break;
3192 case SEQ: 3373 case SEQ:
3193 val = vga_rseq (regbase, (unsigned char) reg); 3374 val = vga_rseq(regbase, (unsigned char) reg);
3194 break; 3375 break;
3195 default: 3376 default:
3196 /* should never occur */ 3377 /* should never occur */
@@ -3198,15 +3379,14 @@ void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_clas
3198 break; 3379 break;
3199 } 3380 }
3200 3381
3201 cirrusfb_dbg_print_byte (name, val); 3382 cirrusfb_dbg_print_byte(name, val);
3202 3383
3203 name = va_arg (list, char *); 3384 name = va_arg(list, char *);
3204 } 3385 }
3205 3386
3206 va_end (list); 3387 va_end(list);
3207} 3388}
3208 3389
3209
3210/** 3390/**
3211 * cirrusfb_dump 3391 * cirrusfb_dump
3212 * @cirrusfbinfo: 3392 * @cirrusfbinfo:
@@ -3214,13 +3394,11 @@ void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_clas
3214 * DESCRIPTION: 3394 * DESCRIPTION:
3215 */ 3395 */
3216 3396
3217static 3397static void cirrusfb_dump(void)
3218void cirrusfb_dump (void)
3219{ 3398{
3220 cirrusfb_dbg_reg_dump (NULL); 3399 cirrusfb_dbg_reg_dump(NULL);
3221} 3400}
3222 3401
3223
3224/** 3402/**
3225 * cirrusfb_dbg_reg_dump 3403 * cirrusfb_dbg_reg_dump
3226 * @base: If using newmmio, the newmmio base address, otherwise %NULL 3404 * @base: If using newmmio, the newmmio base address, otherwise %NULL
@@ -3232,11 +3410,11 @@ void cirrusfb_dump (void)
3232 */ 3410 */
3233 3411
3234static 3412static
3235void cirrusfb_dbg_reg_dump (caddr_t regbase) 3413void cirrusfb_dbg_reg_dump(caddr_t regbase)
3236{ 3414{
3237 DPRINTK ("CIRRUSFB VGA CRTC register dump:\n"); 3415 DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
3238 3416
3239 cirrusfb_dbg_print_regs (regbase, CRT, 3417 cirrusfb_dbg_print_regs(regbase, CRT,
3240 "CR00", 0x00, 3418 "CR00", 0x00,
3241 "CR01", 0x01, 3419 "CR01", 0x01,
3242 "CR02", 0x02, 3420 "CR02", 0x02,
@@ -3286,11 +3464,11 @@ void cirrusfb_dbg_reg_dump (caddr_t regbase)
3286 "CR3F", 0x3F, 3464 "CR3F", 0x3F,
3287 NULL); 3465 NULL);
3288 3466
3289 DPRINTK ("\n"); 3467 DPRINTK("\n");
3290 3468
3291 DPRINTK ("CIRRUSFB VGA SEQ register dump:\n"); 3469 DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
3292 3470
3293 cirrusfb_dbg_print_regs (regbase, SEQ, 3471 cirrusfb_dbg_print_regs(regbase, SEQ,
3294 "SR00", 0x00, 3472 "SR00", 0x00,
3295 "SR01", 0x01, 3473 "SR01", 0x01,
3296 "SR02", 0x02, 3474 "SR02", 0x02,
@@ -3319,7 +3497,7 @@ void cirrusfb_dbg_reg_dump (caddr_t regbase)
3319 "SR1F", 0x1F, 3497 "SR1F", 0x1F,
3320 NULL); 3498 NULL);
3321 3499
3322 DPRINTK ("\n"); 3500 DPRINTK("\n");
3323} 3501}
3324 3502
3325#endif /* CIRRUSFB_DEBUG */ 3503#endif /* CIRRUSFB_DEBUG */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 17:21:34 -0400