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authorPete Popov <ppopov@embeddedalley.com>2005-04-03 21:06:19 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:01 -0400
commit3b495f2bb749b828499135743b9ddec46e34fda8 (patch)
tree5f787ed9829ef01a457428114ccd3547cf6c88da /drivers/video/au1100fb.h
parent172546bf601356f94f8018af7908a9b7c1c4915c (diff)
Au1100 FB driver uplift for 2.6.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Antonino Daplas <adaplas@pol.net>
Diffstat (limited to 'drivers/video/au1100fb.h')
-rw-r--r--drivers/video/au1100fb.h614
1 files changed, 307 insertions, 307 deletions
diff --git a/drivers/video/au1100fb.h b/drivers/video/au1100fb.h
index 657c560ab73c..2855534dc235 100644
--- a/drivers/video/au1100fb.h
+++ b/drivers/video/au1100fb.h
@@ -30,352 +30,352 @@
30#ifndef _AU1100LCD_H 30#ifndef _AU1100LCD_H
31#define _AU1100LCD_H 31#define _AU1100LCD_H
32 32
33#include <asm/mach-au1x00/au1000.h>
34
35#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
36#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
37#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
38
39#if DEBUG
40#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
41#else
42#define print_dbg(f, arg...) do {} while (0)
43#endif
44
45#if defined(__BIG_ENDIAN)
46#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
47#else
48#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
49#endif
50#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
51
33/********************************************************************/ 52/********************************************************************/
34#define uint32 unsigned long 53
35typedef volatile struct 54/* LCD controller restrictions */
36{ 55#define AU1100_LCD_MAX_XRES 800
37 uint32 lcd_control; 56#define AU1100_LCD_MAX_YRES 600
38 uint32 lcd_intstatus; 57#define AU1100_LCD_MAX_BPP 16
39 uint32 lcd_intenable; 58#define AU1100_LCD_MAX_CLK 48000000
40 uint32 lcd_horztiming; 59#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
41 uint32 lcd_verttiming; 60
42 uint32 lcd_clkcontrol; 61/* Default number of visible screen buffer to allocate */
43 uint32 lcd_dmaaddr0; 62#define AU1100FB_NBR_VIDEO_BUFFERS 4
44 uint32 lcd_dmaaddr1;
45 uint32 lcd_words;
46 uint32 lcd_pwmdiv;
47 uint32 lcd_pwmhi;
48 uint32 reserved[(0x0400-0x002C)/4];
49 uint32 lcd_pallettebase[256];
50
51} AU1100_LCD;
52 63
53/********************************************************************/ 64/********************************************************************/
54 65
55#define AU1100_LCD_ADDR 0xB5000000 66struct au1100fb_panel
67{
68 const char name[25]; /* Full name <vendor>_<model> */
56 69
57/* 70 u32 control_base; /* Mode-independent control values */
58 * Register bit definitions 71 u32 clkcontrol_base; /* Panel pixclock preferences */
59 */
60 72
61/* lcd_control */ 73 u32 horztiming;
62#define LCD_CONTROL_SBPPF (7<<18) 74 u32 verttiming;
63#define LCD_CONTROL_SBPPF_655 (0<<18)
64#define LCD_CONTROL_SBPPF_565 (1<<18)
65#define LCD_CONTROL_SBPPF_556 (2<<18)
66#define LCD_CONTROL_SBPPF_1555 (3<<18)
67#define LCD_CONTROL_SBPPF_5551 (4<<18)
68#define LCD_CONTROL_WP (1<<17)
69#define LCD_CONTROL_WD (1<<16)
70#define LCD_CONTROL_C (1<<15)
71#define LCD_CONTROL_SM (3<<13)
72#define LCD_CONTROL_SM_0 (0<<13)
73#define LCD_CONTROL_SM_90 (1<<13)
74#define LCD_CONTROL_SM_180 (2<<13)
75#define LCD_CONTROL_SM_270 (3<<13)
76#define LCD_CONTROL_DB (1<<12)
77#define LCD_CONTROL_CCO (1<<11)
78#define LCD_CONTROL_DP (1<<10)
79#define LCD_CONTROL_PO (3<<8)
80#define LCD_CONTROL_PO_00 (0<<8)
81#define LCD_CONTROL_PO_01 (1<<8)
82#define LCD_CONTROL_PO_10 (2<<8)
83#define LCD_CONTROL_PO_11 (3<<8)
84#define LCD_CONTROL_MPI (1<<7)
85#define LCD_CONTROL_PT (1<<6)
86#define LCD_CONTROL_PC (1<<5)
87#define LCD_CONTROL_BPP (7<<1)
88#define LCD_CONTROL_BPP_1 (0<<1)
89#define LCD_CONTROL_BPP_2 (1<<1)
90#define LCD_CONTROL_BPP_4 (2<<1)
91#define LCD_CONTROL_BPP_8 (3<<1)
92#define LCD_CONTROL_BPP_12 (4<<1)
93#define LCD_CONTROL_BPP_16 (5<<1)
94#define LCD_CONTROL_GO (1<<0)
95
96/* lcd_intstatus, lcd_intenable */
97#define LCD_INT_SD (1<<7)
98#define LCD_INT_OF (1<<6)
99#define LCD_INT_UF (1<<5)
100#define LCD_INT_SA (1<<3)
101#define LCD_INT_SS (1<<2)
102#define LCD_INT_S1 (1<<1)
103#define LCD_INT_S0 (1<<0)
104
105/* lcd_horztiming */
106#define LCD_HORZTIMING_HN2 (255<<24)
107#define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24)
108#define LCD_HORZTIMING_HN1 (255<<16)
109#define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16)
110#define LCD_HORZTIMING_HPW (63<<10)
111#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10)
112#define LCD_HORZTIMING_PPL (1023<<0)
113#define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0)
114
115/* lcd_verttiming */
116#define LCD_VERTTIMING_VN2 (255<<24)
117#define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24)
118#define LCD_VERTTIMING_VN1 (255<<16)
119#define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16)
120#define LCD_VERTTIMING_VPW (63<<10)
121#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10)
122#define LCD_VERTTIMING_LPP (1023<<0)
123#define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0)
124
125/* lcd_clkcontrol */
126#define LCD_CLKCONTROL_IB (1<<18)
127#define LCD_CLKCONTROL_IC (1<<17)
128#define LCD_CLKCONTROL_IH (1<<16)
129#define LCD_CLKCONTROL_IV (1<<15)
130#define LCD_CLKCONTROL_BF (31<<10)
131#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
132#define LCD_CLKCONTROL_PCD (1023<<0)
133#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
134
135/* lcd_pwmdiv */
136#define LCD_PWMDIV_EN (1<<12)
137#define LCD_PWMDIV_PWMDIV (2047<<0)
138#define LCD_PWMDIV_PWMDIV_N(N) (((N)-1)<<0)
139
140/* lcd_pwmhi */
141#define LCD_PWMHI_PWMHI1 (2047<<12)
142#define LCD_PWMHI_PWMHI1_N(N) ((N)<<12)
143#define LCD_PWMHI_PWMHI0 (2047<<0)
144#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
145
146/* lcd_pallettebase - MONOCHROME */
147#define LCD_PALLETTE_MONO_MI (15<<0)
148#define LCD_PALLETTE_MONO_MI_N(N) ((N)<<0)
149
150/* lcd_pallettebase - COLOR */
151#define LCD_PALLETTE_COLOR_BI (15<<8)
152#define LCD_PALLETTE_COLOR_BI_N(N) ((N)<<8)
153#define LCD_PALLETTE_COLOR_GI (15<<4)
154#define LCD_PALLETTE_COLOR_GI_N(N) ((N)<<4)
155#define LCD_PALLETTE_COLOR_RI (15<<0)
156#define LCD_PALLETTE_COLOR_RI_N(N) ((N)<<0)
157
158/* lcd_palletebase - COLOR TFT PALLETIZED */
159#define LCD_PALLETTE_TFT_DC (65535<<0)
160#define LCD_PALLETTE_TFT_DC_N(N) ((N)<<0)
161 75
162/********************************************************************/ 76 u32 xres; /* Maximum horizontal resolution */
77 u32 yres; /* Maximum vertical resolution */
78 u32 bpp; /* Maximum depth supported */
79};
163 80
164struct known_lcd_panels 81struct au1100fb_regs
165{ 82{
166 uint32 xres; 83 u32 lcd_control;
167 uint32 yres; 84 u32 lcd_intstatus;
168 uint32 bpp; 85 u32 lcd_intenable;
169 unsigned char panel_name[256]; 86 u32 lcd_horztiming;
170 uint32 mode_control; 87 u32 lcd_verttiming;
171 uint32 mode_horztiming; 88 u32 lcd_clkcontrol;
172 uint32 mode_verttiming; 89 u32 lcd_dmaaddr0;
173 uint32 mode_clkcontrol; 90 u32 lcd_dmaaddr1;
174 uint32 mode_pwmdiv; 91 u32 lcd_words;
175 uint32 mode_pwmhi; 92 u32 lcd_pwmdiv;
176 uint32 mode_toyclksrc; 93 u32 lcd_pwmhi;
177 uint32 mode_backlight; 94 u32 reserved[(0x0400-0x002C)/4];
95 u32 lcd_pallettebase[256];
96};
97
98struct au1100fb_device {
99
100 struct fb_info info; /* FB driver info record */
178 101
102 struct au1100fb_panel *panel; /* Panel connected to this device */
103
104 struct au1100fb_regs* regs; /* Registers memory map */
105 size_t regs_len;
106 unsigned int regs_phys;
107
108 unsigned char* fb_mem; /* FrameBuffer memory map */
109 size_t fb_len;
110 dma_addr_t fb_phys;
179}; 111};
180 112
181#if defined(__BIG_ENDIAN) 113/********************************************************************/
182#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11
183#else
184#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00
185#endif
186 114
187/* 115#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
188 * The fb driver assumes that AUX PLL is at 48MHz. That can 116 #define LCD_CONTROL_SBB_BIT 21
189 * cover up to 800x600 resolution; if you need higher resolution, 117 #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
190 * you should modify the driver as needed, not just this structure. 118 #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
119 #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
120 #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
121 #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
122 #define LCD_CONTROL_SBPPF_BIT 18
123 #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
124 #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
125 #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
126 #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
127 #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
128 #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
129 #define LCD_CONTROL_WP (1<<17)
130 #define LCD_CONTROL_WD (1<<16)
131 #define LCD_CONTROL_C (1<<15)
132 #define LCD_CONTROL_SM_BIT 13
133 #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
134 #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
135 #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
136 #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
137 #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
138 #define LCD_CONTROL_DB (1<<12)
139 #define LCD_CONTROL_CCO (1<<11)
140 #define LCD_CONTROL_DP (1<<10)
141 #define LCD_CONTROL_PO_BIT 8
142 #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
143 #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
144 #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
145 #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
146 #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
147 #define LCD_CONTROL_MPI (1<<7)
148 #define LCD_CONTROL_PT (1<<6)
149 #define LCD_CONTROL_PC (1<<5)
150 #define LCD_CONTROL_BPP_BIT 1
151 #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
152 #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
153 #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
154 #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
155 #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
156 #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
157 #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
158 #define LCD_CONTROL_GO (1<<0)
159
160#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
161#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
162 #define LCD_INT_SD (1<<7)
163 #define LCD_INT_OF (1<<6)
164 #define LCD_INT_UF (1<<5)
165 #define LCD_INT_SA (1<<3)
166 #define LCD_INT_SS (1<<2)
167 #define LCD_INT_S1 (1<<1)
168 #define LCD_INT_S0 (1<<0)
169
170#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
171 #define LCD_HORZTIMING_HN2_BIT 24
172 #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
173 #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
174 #define LCD_HORZTIMING_HN1_BIT 16
175 #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
176 #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
177 #define LCD_HORZTIMING_HPW_BIT 10
178 #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
179 #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
180 #define LCD_HORZTIMING_PPL_BIT 0
181 #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
182 #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
183
184#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
185 #define LCD_VERTTIMING_VN2_BIT 24
186 #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
187 #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
188 #define LCD_VERTTIMING_VN1_BIT 16
189 #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
190 #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
191 #define LCD_VERTTIMING_VPW_BIT 10
192 #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
193 #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
194 #define LCD_VERTTIMING_LPP_BIT 0
195 #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
196 #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
197
198#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
199 #define LCD_CLKCONTROL_IB (1<<18)
200 #define LCD_CLKCONTROL_IC (1<<17)
201 #define LCD_CLKCONTROL_IH (1<<16)
202 #define LCD_CLKCONTROL_IV (1<<15)
203 #define LCD_CLKCONTROL_BF_BIT 10
204 #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
205 #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
206 #define LCD_CLKCONTROL_PCD_BIT 0
207 #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
208 #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
209
210#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
211#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
212 #define LCD_DMA_SA_BIT 5
213 #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
214 #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
215
216#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
217 #define LCD_WRD_WRDS_BIT 0
218 #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
219 #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
220
221#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
222 #define LCD_PWMDIV_EN (1<<12)
223 #define LCD_PWMDIV_PWMDIV_BIT 0
224 #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
225 #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
226
227#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
228 #define LCD_PWMHI_PWMHI1_BIT 12
229 #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
230 #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
231 #define LCD_PWMHI_PWMHI0_BIT 0
232 #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
233 #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
234
235#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
236 #define LCD_PALLETTE_MONO_MI_BIT 0
237 #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
238 #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
239
240 #define LCD_PALLETTE_COLOR_RI_BIT 8
241 #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
242 #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
243 #define LCD_PALLETTE_COLOR_GI_BIT 4
244 #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
245 #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
246 #define LCD_PALLETTE_COLOR_BI_BIT 0
247 #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
248 #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
249
250 #define LCD_PALLETTE_TFT_DC_BIT 0
251 #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
252 #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
253
254/********************************************************************/
255
256/* List of panels known to work with the AU1100 LCD controller.
257 * To add a new panel, enter the same specifications as the
258 * Generic_TFT one, and MAKE SURE that it doesn't conflicts
259 * with the controller restrictions. Restrictions are:
260 *
261 * STN color panels: max_bpp <= 12
262 * STN mono panels: max_bpp <= 4
263 * TFT panels: max_bpp <= 16
264 * max_xres <= 800
265 * max_yres <= 600
191 */ 266 */
192struct known_lcd_panels panels[] = 267static struct au1100fb_panel known_lcd_panels[] =
193{ 268{
194 { /* 0: Pb1100 LCDA: Sharp 320x240 TFT panel */ 269 /* 800x600x16bpp CRT */
195 320, /* xres */ 270 [0] = {
196 240, /* yres */ 271 .name = "CRT_800x600_16",
197 16, /* bpp */ 272 .xres = 800,
198 273 .yres = 600,
199 "Sharp_320x240_16", 274 .bpp = 16,
200 /* mode_control */ 275 .control_base = 0x0004886A |
276 LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
277 LCD_CONTROL_BPP_16,
278 .clkcontrol_base = 0x00020000,
279 .horztiming = 0x005aff1f,
280 .verttiming = 0x16000e57,
281 },
282 /* just the standard LCD */
283 [1] = {
284 .name = "WWPC LCD",
285 .xres = 240,
286 .yres = 320,
287 .bpp = 16,
288 .control_base = 0x0006806A,
289 .horztiming = 0x0A1010EF,
290 .verttiming = 0x0301013F,
291 .clkcontrol_base = 0x00018001,
292 },
293 /* Sharp 320x240 TFT panel */
294 [2] = {
295 .name = "Sharp_LQ038Q5DR01",
296 .xres = 320,
297 .yres = 240,
298 .bpp = 16,
299 .control_base =
201 ( LCD_CONTROL_SBPPF_565 300 ( LCD_CONTROL_SBPPF_565
202 /*LCD_CONTROL_WP*/
203 /*LCD_CONTROL_WD*/
204 | LCD_CONTROL_C 301 | LCD_CONTROL_C
205 | LCD_CONTROL_SM_0 302 | LCD_CONTROL_SM_0
206 /*LCD_CONTROL_DB*/ 303 | LCD_CONTROL_DEFAULT_PO
207 /*LCD_CONTROL_CCO*/
208 /*LCD_CONTROL_DP*/
209 | LCD_DEFAULT_PIX_FORMAT
210 /*LCD_CONTROL_MPI*/
211 | LCD_CONTROL_PT 304 | LCD_CONTROL_PT
212 | LCD_CONTROL_PC 305 | LCD_CONTROL_PC
213 | LCD_CONTROL_BPP_16 ), 306 | LCD_CONTROL_BPP_16 ),
214 307 .horztiming =
215 /* mode_horztiming */
216 ( LCD_HORZTIMING_HN2_N(8) 308 ( LCD_HORZTIMING_HN2_N(8)
217 | LCD_HORZTIMING_HN1_N(60) 309 | LCD_HORZTIMING_HN1_N(60)
218 | LCD_HORZTIMING_HPW_N(12) 310 | LCD_HORZTIMING_HPW_N(12)
219 | LCD_HORZTIMING_PPL_N(320) ), 311 | LCD_HORZTIMING_PPL_N(320) ),
220 312 .verttiming =
221 /* mode_verttiming */
222 ( LCD_VERTTIMING_VN2_N(5) 313 ( LCD_VERTTIMING_VN2_N(5)
223 | LCD_VERTTIMING_VN1_N(17) 314 | LCD_VERTTIMING_VN1_N(17)
224 | LCD_VERTTIMING_VPW_N(1) 315 | LCD_VERTTIMING_VPW_N(1)
225 | LCD_VERTTIMING_LPP_N(240) ), 316 | LCD_VERTTIMING_LPP_N(240) ),
226 317 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
227 /* mode_clkcontrol */
228 ( 0
229 /*LCD_CLKCONTROL_IB*/
230 /*LCD_CLKCONTROL_IC*/
231 /*LCD_CLKCONTROL_IH*/
232 /*LCD_CLKCONTROL_IV*/
233 | LCD_CLKCONTROL_PCD_N(1) ),
234
235 /* mode_pwmdiv */
236 0,
237
238 /* mode_pwmhi */
239 0,
240
241 /* mode_toyclksrc */
242 ((1<<7) | (1<<6) | (1<<5)),
243
244 /* mode_backlight */
245 6
246 }, 318 },
247 319
248 { /* 1: Pb1100 LCDC 640x480 TFT panel */ 320 /* Hitachi SP14Q005 and possibly others */
249 640, /* xres */ 321 [3] = {
250 480, /* yres */ 322 .name = "Hitachi_SP14Qxxx",
251 16, /* bpp */ 323 .xres = 320,
252 324 .yres = 240,
253 "Generic_640x480_16", 325 .bpp = 4,
254 326 .control_base =
255 /* mode_control */ 327 ( LCD_CONTROL_C
256 0x004806a | LCD_DEFAULT_PIX_FORMAT, 328 | LCD_CONTROL_BPP_4 ),
257 329 .horztiming =
258 /* mode_horztiming */ 330 ( LCD_HORZTIMING_HN2_N(1)
259 0x3434d67f, 331 | LCD_HORZTIMING_HN1_N(1)
260 332 | LCD_HORZTIMING_HPW_N(1)
261 /* mode_verttiming */ 333 | LCD_HORZTIMING_PPL_N(320) ),
262 0x0e0e39df, 334 .verttiming =
263 335 ( LCD_VERTTIMING_VN2_N(1)
264 /* mode_clkcontrol */ 336 | LCD_VERTTIMING_VN1_N(1)
265 ( 0 337 | LCD_VERTTIMING_VPW_N(1)
266 /*LCD_CLKCONTROL_IB*/ 338 | LCD_VERTTIMING_LPP_N(240) ),
267 /*LCD_CLKCONTROL_IC*/ 339 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
268 /*LCD_CLKCONTROL_IH*/
269 /*LCD_CLKCONTROL_IV*/
270 | LCD_CLKCONTROL_PCD_N(1) ),
271
272 /* mode_pwmdiv */
273 0,
274
275 /* mode_pwmhi */
276 0,
277
278 /* mode_toyclksrc */
279 ((1<<7) | (1<<6) | (0<<5)),
280
281 /* mode_backlight */
282 7
283 }, 340 },
284 341
285 { /* 2: Pb1100 LCDB 640x480 PrimeView TFT panel */ 342 /* Generic 640x480 TFT panel */
286 640, /* xres */ 343 [4] = {
287 480, /* yres */ 344 .name = "TFT_640x480_16",
288 16, /* bpp */ 345 .xres = 640,
289 346 .yres = 480,
290 "PrimeView_640x480_16", 347 .bpp = 16,
291 348 .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
292 /* mode_control */ 349 .horztiming = 0x3434d67f,
293 0x0004886a | LCD_DEFAULT_PIX_FORMAT, 350 .verttiming = 0x0e0e39df,
294 351 .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
295 /* mode_horztiming */
296 0x0e4bfe7f,
297
298 /* mode_verttiming */
299 0x210805df,
300
301 /* mode_clkcontrol */
302 0x00038001,
303
304 /* mode_pwmdiv */
305 0,
306
307 /* mode_pwmhi */
308 0,
309
310 /* mode_toyclksrc */
311 ((1<<7) | (1<<6) | (0<<5)),
312
313 /* mode_backlight */
314 7
315 }, 352 },
316 353
317 { /* 3: Pb1100 800x600x16bpp NEON CRT */ 354 /* Pb1100 LCDB 640x480 PrimeView TFT panel */
318 800, /* xres */ 355 [5] = {
319 600, /* yres */ 356 .name = "PrimeView_640x480_16",
320 16, /* bpp */ 357 .xres = 640,
321 358 .yres = 480,
322 "NEON_800x600_16", 359 .bpp = 16,
323 360 .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
324 /* mode_control */ 361 .horztiming = 0x0e4bfe7f,
325 0x0004886A | LCD_DEFAULT_PIX_FORMAT, 362 .verttiming = 0x210805df,
326 363 .clkcontrol_base = 0x00038001,
327 /* mode_horztiming */
328 0x005AFF1F,
329
330 /* mode_verttiming */
331 0x16000E57,
332
333 /* mode_clkcontrol */
334 0x00020000,
335
336 /* mode_pwmdiv */
337 0,
338
339 /* mode_pwmhi */
340 0,
341
342 /* mode_toyclksrc */
343 ((1<<7) | (1<<6) | (0<<5)),
344
345 /* mode_backlight */
346 7
347 }, 364 },
365};
348 366
349 { /* 4: Pb1100 640x480x16bpp NEON CRT */ 367struct au1100fb_drv_info {
350 640, /* xres */ 368 int panel_idx;
351 480, /* yres */ 369 char *opt_mode;
352 16, /* bpp */ 370};
353
354 "NEON_640x480_16",
355
356 /* mode_control */
357 0x0004886A | LCD_DEFAULT_PIX_FORMAT,
358
359 /* mode_horztiming */
360 0x0052E27F,
361
362 /* mode_verttiming */
363 0x18000DDF,
364
365 /* mode_clkcontrol */
366 0x00020000,
367 371
368 /* mode_pwmdiv */ 372/********************************************************************/
369 0,
370 373
371 /* mode_pwmhi */ 374/* Inline helpers */
372 0,
373 375
374 /* mode_toyclksrc */ 376#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
375 ((1<<7) | (1<<6) | (0<<5)), 377#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
378#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
379#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
376 380
377 /* mode_backlight */
378 7
379 },
380};
381#endif /* _AU1100LCD_H */ 381#endif /* _AU1100LCD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 13:46:02 -0400