diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/au1100fb.h |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'drivers/video/au1100fb.h')
-rw-r--r-- | drivers/video/au1100fb.h | 381 |
1 files changed, 381 insertions, 0 deletions
diff --git a/drivers/video/au1100fb.h b/drivers/video/au1100fb.h new file mode 100644 index 000000000000..657c560ab73c --- /dev/null +++ b/drivers/video/au1100fb.h | |||
@@ -0,0 +1,381 @@ | |||
1 | /* | ||
2 | * BRIEF MODULE DESCRIPTION | ||
3 | * Hardware definitions for the Au1100 LCD controller | ||
4 | * | ||
5 | * Copyright 2002 MontaVista Software | ||
6 | * Copyright 2002 Alchemy Semiconductor | ||
7 | * Author: Alchemy Semiconductor, MontaVista Software | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | * | ||
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License along | ||
26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
28 | */ | ||
29 | |||
30 | #ifndef _AU1100LCD_H | ||
31 | #define _AU1100LCD_H | ||
32 | |||
33 | /********************************************************************/ | ||
34 | #define uint32 unsigned long | ||
35 | typedef volatile struct | ||
36 | { | ||
37 | uint32 lcd_control; | ||
38 | uint32 lcd_intstatus; | ||
39 | uint32 lcd_intenable; | ||
40 | uint32 lcd_horztiming; | ||
41 | uint32 lcd_verttiming; | ||
42 | uint32 lcd_clkcontrol; | ||
43 | uint32 lcd_dmaaddr0; | ||
44 | uint32 lcd_dmaaddr1; | ||
45 | uint32 lcd_words; | ||
46 | uint32 lcd_pwmdiv; | ||
47 | uint32 lcd_pwmhi; | ||
48 | uint32 reserved[(0x0400-0x002C)/4]; | ||
49 | uint32 lcd_pallettebase[256]; | ||
50 | |||
51 | } AU1100_LCD; | ||
52 | |||
53 | /********************************************************************/ | ||
54 | |||
55 | #define AU1100_LCD_ADDR 0xB5000000 | ||
56 | |||
57 | /* | ||
58 | * Register bit definitions | ||
59 | */ | ||
60 | |||
61 | /* lcd_control */ | ||
62 | #define LCD_CONTROL_SBPPF (7<<18) | ||
63 | #define LCD_CONTROL_SBPPF_655 (0<<18) | ||
64 | #define LCD_CONTROL_SBPPF_565 (1<<18) | ||
65 | #define LCD_CONTROL_SBPPF_556 (2<<18) | ||
66 | #define LCD_CONTROL_SBPPF_1555 (3<<18) | ||
67 | #define LCD_CONTROL_SBPPF_5551 (4<<18) | ||
68 | #define LCD_CONTROL_WP (1<<17) | ||
69 | #define LCD_CONTROL_WD (1<<16) | ||
70 | #define LCD_CONTROL_C (1<<15) | ||
71 | #define LCD_CONTROL_SM (3<<13) | ||
72 | #define LCD_CONTROL_SM_0 (0<<13) | ||
73 | #define LCD_CONTROL_SM_90 (1<<13) | ||
74 | #define LCD_CONTROL_SM_180 (2<<13) | ||
75 | #define LCD_CONTROL_SM_270 (3<<13) | ||
76 | #define LCD_CONTROL_DB (1<<12) | ||
77 | #define LCD_CONTROL_CCO (1<<11) | ||
78 | #define LCD_CONTROL_DP (1<<10) | ||
79 | #define LCD_CONTROL_PO (3<<8) | ||
80 | #define LCD_CONTROL_PO_00 (0<<8) | ||
81 | #define LCD_CONTROL_PO_01 (1<<8) | ||
82 | #define LCD_CONTROL_PO_10 (2<<8) | ||
83 | #define LCD_CONTROL_PO_11 (3<<8) | ||
84 | #define LCD_CONTROL_MPI (1<<7) | ||
85 | #define LCD_CONTROL_PT (1<<6) | ||
86 | #define LCD_CONTROL_PC (1<<5) | ||
87 | #define LCD_CONTROL_BPP (7<<1) | ||
88 | #define LCD_CONTROL_BPP_1 (0<<1) | ||
89 | #define LCD_CONTROL_BPP_2 (1<<1) | ||
90 | #define LCD_CONTROL_BPP_4 (2<<1) | ||
91 | #define LCD_CONTROL_BPP_8 (3<<1) | ||
92 | #define LCD_CONTROL_BPP_12 (4<<1) | ||
93 | #define LCD_CONTROL_BPP_16 (5<<1) | ||
94 | #define LCD_CONTROL_GO (1<<0) | ||
95 | |||
96 | /* lcd_intstatus, lcd_intenable */ | ||
97 | #define LCD_INT_SD (1<<7) | ||
98 | #define LCD_INT_OF (1<<6) | ||
99 | #define LCD_INT_UF (1<<5) | ||
100 | #define LCD_INT_SA (1<<3) | ||
101 | #define LCD_INT_SS (1<<2) | ||
102 | #define LCD_INT_S1 (1<<1) | ||
103 | #define LCD_INT_S0 (1<<0) | ||
104 | |||
105 | /* lcd_horztiming */ | ||
106 | #define LCD_HORZTIMING_HN2 (255<<24) | ||
107 | #define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24) | ||
108 | #define LCD_HORZTIMING_HN1 (255<<16) | ||
109 | #define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16) | ||
110 | #define LCD_HORZTIMING_HPW (63<<10) | ||
111 | #define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10) | ||
112 | #define LCD_HORZTIMING_PPL (1023<<0) | ||
113 | #define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0) | ||
114 | |||
115 | /* lcd_verttiming */ | ||
116 | #define LCD_VERTTIMING_VN2 (255<<24) | ||
117 | #define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24) | ||
118 | #define LCD_VERTTIMING_VN1 (255<<16) | ||
119 | #define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16) | ||
120 | #define LCD_VERTTIMING_VPW (63<<10) | ||
121 | #define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10) | ||
122 | #define LCD_VERTTIMING_LPP (1023<<0) | ||
123 | #define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0) | ||
124 | |||
125 | /* lcd_clkcontrol */ | ||
126 | #define LCD_CLKCONTROL_IB (1<<18) | ||
127 | #define LCD_CLKCONTROL_IC (1<<17) | ||
128 | #define LCD_CLKCONTROL_IH (1<<16) | ||
129 | #define LCD_CLKCONTROL_IV (1<<15) | ||
130 | #define LCD_CLKCONTROL_BF (31<<10) | ||
131 | #define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10) | ||
132 | #define LCD_CLKCONTROL_PCD (1023<<0) | ||
133 | #define LCD_CLKCONTROL_PCD_N(N) ((N)<<0) | ||
134 | |||
135 | /* lcd_pwmdiv */ | ||
136 | #define LCD_PWMDIV_EN (1<<12) | ||
137 | #define LCD_PWMDIV_PWMDIV (2047<<0) | ||
138 | #define LCD_PWMDIV_PWMDIV_N(N) (((N)-1)<<0) | ||
139 | |||
140 | /* lcd_pwmhi */ | ||
141 | #define LCD_PWMHI_PWMHI1 (2047<<12) | ||
142 | #define LCD_PWMHI_PWMHI1_N(N) ((N)<<12) | ||
143 | #define LCD_PWMHI_PWMHI0 (2047<<0) | ||
144 | #define LCD_PWMHI_PWMHI0_N(N) ((N)<<0) | ||
145 | |||
146 | /* lcd_pallettebase - MONOCHROME */ | ||
147 | #define LCD_PALLETTE_MONO_MI (15<<0) | ||
148 | #define LCD_PALLETTE_MONO_MI_N(N) ((N)<<0) | ||
149 | |||
150 | /* lcd_pallettebase - COLOR */ | ||
151 | #define LCD_PALLETTE_COLOR_BI (15<<8) | ||
152 | #define LCD_PALLETTE_COLOR_BI_N(N) ((N)<<8) | ||
153 | #define LCD_PALLETTE_COLOR_GI (15<<4) | ||
154 | #define LCD_PALLETTE_COLOR_GI_N(N) ((N)<<4) | ||
155 | #define LCD_PALLETTE_COLOR_RI (15<<0) | ||
156 | #define LCD_PALLETTE_COLOR_RI_N(N) ((N)<<0) | ||
157 | |||
158 | /* lcd_palletebase - COLOR TFT PALLETIZED */ | ||
159 | #define LCD_PALLETTE_TFT_DC (65535<<0) | ||
160 | #define LCD_PALLETTE_TFT_DC_N(N) ((N)<<0) | ||
161 | |||
162 | /********************************************************************/ | ||
163 | |||
164 | struct known_lcd_panels | ||
165 | { | ||
166 | uint32 xres; | ||
167 | uint32 yres; | ||
168 | uint32 bpp; | ||
169 | unsigned char panel_name[256]; | ||
170 | uint32 mode_control; | ||
171 | uint32 mode_horztiming; | ||
172 | uint32 mode_verttiming; | ||
173 | uint32 mode_clkcontrol; | ||
174 | uint32 mode_pwmdiv; | ||
175 | uint32 mode_pwmhi; | ||
176 | uint32 mode_toyclksrc; | ||
177 | uint32 mode_backlight; | ||
178 | |||
179 | }; | ||
180 | |||
181 | #if defined(__BIG_ENDIAN) | ||
182 | #define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11 | ||
183 | #else | ||
184 | #define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00 | ||
185 | #endif | ||
186 | |||
187 | /* | ||
188 | * The fb driver assumes that AUX PLL is at 48MHz. That can | ||
189 | * cover up to 800x600 resolution; if you need higher resolution, | ||
190 | * you should modify the driver as needed, not just this structure. | ||
191 | */ | ||
192 | struct known_lcd_panels panels[] = | ||
193 | { | ||
194 | { /* 0: Pb1100 LCDA: Sharp 320x240 TFT panel */ | ||
195 | 320, /* xres */ | ||
196 | 240, /* yres */ | ||
197 | 16, /* bpp */ | ||
198 | |||
199 | "Sharp_320x240_16", | ||
200 | /* mode_control */ | ||
201 | ( LCD_CONTROL_SBPPF_565 | ||
202 | /*LCD_CONTROL_WP*/ | ||
203 | /*LCD_CONTROL_WD*/ | ||
204 | | LCD_CONTROL_C | ||
205 | | LCD_CONTROL_SM_0 | ||
206 | /*LCD_CONTROL_DB*/ | ||
207 | /*LCD_CONTROL_CCO*/ | ||
208 | /*LCD_CONTROL_DP*/ | ||
209 | | LCD_DEFAULT_PIX_FORMAT | ||
210 | /*LCD_CONTROL_MPI*/ | ||
211 | | LCD_CONTROL_PT | ||
212 | | LCD_CONTROL_PC | ||
213 | | LCD_CONTROL_BPP_16 ), | ||
214 | |||
215 | /* mode_horztiming */ | ||
216 | ( LCD_HORZTIMING_HN2_N(8) | ||
217 | | LCD_HORZTIMING_HN1_N(60) | ||
218 | | LCD_HORZTIMING_HPW_N(12) | ||
219 | | LCD_HORZTIMING_PPL_N(320) ), | ||
220 | |||
221 | /* mode_verttiming */ | ||
222 | ( LCD_VERTTIMING_VN2_N(5) | ||
223 | | LCD_VERTTIMING_VN1_N(17) | ||
224 | | LCD_VERTTIMING_VPW_N(1) | ||
225 | | LCD_VERTTIMING_LPP_N(240) ), | ||
226 | |||
227 | /* mode_clkcontrol */ | ||
228 | ( 0 | ||
229 | /*LCD_CLKCONTROL_IB*/ | ||
230 | /*LCD_CLKCONTROL_IC*/ | ||
231 | /*LCD_CLKCONTROL_IH*/ | ||
232 | /*LCD_CLKCONTROL_IV*/ | ||
233 | | LCD_CLKCONTROL_PCD_N(1) ), | ||
234 | |||
235 | /* mode_pwmdiv */ | ||
236 | 0, | ||
237 | |||
238 | /* mode_pwmhi */ | ||
239 | 0, | ||
240 | |||
241 | /* mode_toyclksrc */ | ||
242 | ((1<<7) | (1<<6) | (1<<5)), | ||
243 | |||
244 | /* mode_backlight */ | ||
245 | 6 | ||
246 | }, | ||
247 | |||
248 | { /* 1: Pb1100 LCDC 640x480 TFT panel */ | ||
249 | 640, /* xres */ | ||
250 | 480, /* yres */ | ||
251 | 16, /* bpp */ | ||
252 | |||
253 | "Generic_640x480_16", | ||
254 | |||
255 | /* mode_control */ | ||
256 | 0x004806a | LCD_DEFAULT_PIX_FORMAT, | ||
257 | |||
258 | /* mode_horztiming */ | ||
259 | 0x3434d67f, | ||
260 | |||
261 | /* mode_verttiming */ | ||
262 | 0x0e0e39df, | ||
263 | |||
264 | /* mode_clkcontrol */ | ||
265 | ( 0 | ||
266 | /*LCD_CLKCONTROL_IB*/ | ||
267 | /*LCD_CLKCONTROL_IC*/ | ||
268 | /*LCD_CLKCONTROL_IH*/ | ||
269 | /*LCD_CLKCONTROL_IV*/ | ||
270 | | LCD_CLKCONTROL_PCD_N(1) ), | ||
271 | |||
272 | /* mode_pwmdiv */ | ||
273 | 0, | ||
274 | |||
275 | /* mode_pwmhi */ | ||
276 | 0, | ||
277 | |||
278 | /* mode_toyclksrc */ | ||
279 | ((1<<7) | (1<<6) | (0<<5)), | ||
280 | |||
281 | /* mode_backlight */ | ||
282 | 7 | ||
283 | }, | ||
284 | |||
285 | { /* 2: Pb1100 LCDB 640x480 PrimeView TFT panel */ | ||
286 | 640, /* xres */ | ||
287 | 480, /* yres */ | ||
288 | 16, /* bpp */ | ||
289 | |||
290 | "PrimeView_640x480_16", | ||
291 | |||
292 | /* mode_control */ | ||
293 | 0x0004886a | LCD_DEFAULT_PIX_FORMAT, | ||
294 | |||
295 | /* mode_horztiming */ | ||
296 | 0x0e4bfe7f, | ||
297 | |||
298 | /* mode_verttiming */ | ||
299 | 0x210805df, | ||
300 | |||
301 | /* mode_clkcontrol */ | ||
302 | 0x00038001, | ||
303 | |||
304 | /* mode_pwmdiv */ | ||
305 | 0, | ||
306 | |||
307 | /* mode_pwmhi */ | ||
308 | 0, | ||
309 | |||
310 | /* mode_toyclksrc */ | ||
311 | ((1<<7) | (1<<6) | (0<<5)), | ||
312 | |||
313 | /* mode_backlight */ | ||
314 | 7 | ||
315 | }, | ||
316 | |||
317 | { /* 3: Pb1100 800x600x16bpp NEON CRT */ | ||
318 | 800, /* xres */ | ||
319 | 600, /* yres */ | ||
320 | 16, /* bpp */ | ||
321 | |||
322 | "NEON_800x600_16", | ||
323 | |||
324 | /* mode_control */ | ||
325 | 0x0004886A | LCD_DEFAULT_PIX_FORMAT, | ||
326 | |||
327 | /* mode_horztiming */ | ||
328 | 0x005AFF1F, | ||
329 | |||
330 | /* mode_verttiming */ | ||
331 | 0x16000E57, | ||
332 | |||
333 | /* mode_clkcontrol */ | ||
334 | 0x00020000, | ||
335 | |||
336 | /* mode_pwmdiv */ | ||
337 | 0, | ||
338 | |||
339 | /* mode_pwmhi */ | ||
340 | 0, | ||
341 | |||
342 | /* mode_toyclksrc */ | ||
343 | ((1<<7) | (1<<6) | (0<<5)), | ||
344 | |||
345 | /* mode_backlight */ | ||
346 | 7 | ||
347 | }, | ||
348 | |||
349 | { /* 4: Pb1100 640x480x16bpp NEON CRT */ | ||
350 | 640, /* xres */ | ||
351 | 480, /* yres */ | ||
352 | 16, /* bpp */ | ||
353 | |||
354 | "NEON_640x480_16", | ||
355 | |||
356 | /* mode_control */ | ||
357 | 0x0004886A | LCD_DEFAULT_PIX_FORMAT, | ||
358 | |||
359 | /* mode_horztiming */ | ||
360 | 0x0052E27F, | ||
361 | |||
362 | /* mode_verttiming */ | ||
363 | 0x18000DDF, | ||
364 | |||
365 | /* mode_clkcontrol */ | ||
366 | 0x00020000, | ||
367 | |||
368 | /* mode_pwmdiv */ | ||
369 | 0, | ||
370 | |||
371 | /* mode_pwmhi */ | ||
372 | 0, | ||
373 | |||
374 | /* mode_toyclksrc */ | ||
375 | ((1<<7) | (1<<6) | (0<<5)), | ||
376 | |||
377 | /* mode_backlight */ | ||
378 | 7 | ||
379 | }, | ||
380 | }; | ||
381 | #endif /* _AU1100LCD_H */ | ||