radeonfb: accelerate imageblit and other improvements

Implement support for HW color expansion of 1bpp images, along with some
improvements to the FIFO handling and other accel operations.

The offset fixup code is now unnecessary as the fbcon core will call our
set_par upon switch back from KD_GRAPHICS before anything else happens.  I
removed it as it would slow down accel operations.

The fifo wait has been improved to avoid hitting the HW register as often,
and the various accel ops are now performing better caching of register
values.

Overall, this improve accel performances.  The imageblit acceleration does
result in a small overall regression in performances on some machines (on
the order of 5% on some x86), probably becaus the SW path provides a
better bus utilisation, but I decided to ingnore that as the performances
is still very good, and on the other hand, some machines such as some
sparc64 get a 3 fold performance improvement.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David S. Miller <davem@davemloft.net>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 21 insertions, 17 deletions

diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index 3ea1b00fdd22..ea0b5b47acaf 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -336,7 +336,15 @@ struct radeonfb_info {
         int                     mon2_type;
         u8                      *mon2_EDID;
 
-        u32                     dp_gui_master_cntl;
+        /* accel bits */
+        u32                     dp_gui_mc_base;
+        u32                     dp_gui_mc_cache;
+        u32                     dp_cntl_cache;
+        u32                     dp_brush_fg_cache;
+        u32                     dp_brush_bg_cache;
+        u32                     dp_src_fg_cache;
+        u32                     dp_src_bg_cache;
+        u32                     fifo_free;
 
         struct pll_info         pll;
 
@@ -348,6 +356,7 @@ struct radeonfb_info {
         int                     lock_blank;
         int                     dynclk;
         int                     no_schedule;
+        int                     gfx_mode;
         enum radeon_pm_mode     pm_mode;
         reinit_function_ptr     reinit_func;
 
@@ -392,8 +401,14 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 #define INREG16(addr)           readw((rinfo->mmio_base)+addr)
 #define OUTREG16(addr,val)      writew(val, (rinfo->mmio_base)+addr)
+
+#ifdef CONFIG_PPC
+#define INREG(addr)             ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
+#define OUTREG(addr,val)        do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
+#else
 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
+#endif
 
 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
                        u32 val, u32 mask)
@@ -535,17 +550,7 @@ static inline u32 radeon_get_dstbpp(u16 depth)
  * 2D Engine helper routines
  */
 
-static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
-{
-        int i;
-
-        for (i=0; i<2000000; i++) {
-                if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
-                        return;
-                udelay(1);
-        }
-        printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
-}
+extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries);
 
 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 {
@@ -558,7 +563,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
         /* Ensure FIFO is empty, ie, make sure the flush commands
          * has reached the cache
          */
-        _radeon_fifo_wait (rinfo, 64);
+        radeon_fifo_update_and_wait(rinfo, 64);
 
         /* Wait for the flush to complete */
         for (i=0; i < 2000000; i++) {
@@ -570,12 +575,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 }
 
 
-static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
+static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
 {
         int i;
 
         /* ensure FIFO is empty before waiting for idle */
-        _radeon_fifo_wait (rinfo, 64);
+        radeon_fifo_update_and_wait (rinfo, 64);
 
         for (i=0; i<2000000; i++) {
                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
@@ -588,8 +593,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
 }
 
 
-#define radeon_engine_idle()            _radeon_engine_idle(rinfo)
-#define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 #define radeon_msleep(ms)               _radeon_msleep(rinfo,ms)
 
 
@@ -619,6 +622,7 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
 extern int radeonfb_sync(struct fb_info *info);
 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
+extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
 
 /* Other functions */
 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);