radeonfb: misc cleanup of engine and dst cache handling

Fix a couple of incomplete tests of the chip families in the engine
init/reset code and proper initialization of the destination cache mode.
The result should better match what the latest X radeon driver does.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David S. Miller <davem@davemloft.net>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 20 insertions, 13 deletions

diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index ccbfffd12805..3ea1b00fdd22 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -53,6 +53,7 @@ enum radeon_family {
         CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
         CHIP_FAMILY_R420,     /* R420/R423/M18 */
         CHIP_FAMILY_RC410,
+        CHIP_FAMILY_RS400,
         CHIP_FAMILY_RS480,
         CHIP_FAMILY_LAST,
 };
@@ -533,33 +534,39 @@ static inline u32 radeon_get_dstbpp(u16 depth)
 /*
  * 2D Engine helper routines
  */
-static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
+
+static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
 {
         int i;
 
-        /* initiate flush */
-        OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
-                ~RB2D_DC_FLUSH_ALL);
-
-        for (i=0; i < 2000000; i++) {
-                if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
+        for (i=0; i<2000000; i++) {
+                if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
                         return;
                 udelay(1);
         }
-        printk(KERN_ERR "radeonfb: Flush Timeout !\n");
+        printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
 }
 
-
-static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
+static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 {
         int i;
 
-        for (i=0; i<2000000; i++) {
-                if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
+        /* Initiate flush */
+        OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
+                ~RB2D_DC_FLUSH_ALL);
+
+        /* Ensure FIFO is empty, ie, make sure the flush commands
+         * has reached the cache
+         */
+        _radeon_fifo_wait (rinfo, 64);
+
+        /* Wait for the flush to complete */
+        for (i=0; i < 2000000; i++) {
+                if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
                         return;
                 udelay(1);
         }
-        printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
+        printk(KERN_ERR "radeonfb: Flush Timeout !\n");
 }