aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video/aty/radeon_base.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/aty/radeon_base.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/video/aty/radeon_base.c')
-rw-r--r--drivers/video/aty/radeon_base.c2587
1 files changed, 2587 insertions, 0 deletions
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
new file mode 100644
index 000000000000..e8eb124754b1
--- /dev/null
+++ b/drivers/video/aty/radeon_base.c
@@ -0,0 +1,2587 @@
1/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
55#include <linux/config.h>
56#include <linux/module.h>
57#include <linux/moduleparam.h>
58#include <linux/kernel.h>
59#include <linux/errno.h>
60#include <linux/string.h>
61#include <linux/mm.h>
62#include <linux/tty.h>
63#include <linux/slab.h>
64#include <linux/delay.h>
65#include <linux/time.h>
66#include <linux/fb.h>
67#include <linux/ioport.h>
68#include <linux/init.h>
69#include <linux/pci.h>
70#include <linux/vmalloc.h>
71#include <linux/device.h>
72#include <linux/i2c.h>
73
74#include <asm/io.h>
75#include <asm/uaccess.h>
76
77#ifdef CONFIG_PPC_OF
78
79#include <asm/pci-bridge.h>
80#include "../macmodes.h"
81
82#ifdef CONFIG_PMAC_BACKLIGHT
83#include <asm/backlight.h>
84#endif
85
86#ifdef CONFIG_BOOTX_TEXT
87#include <asm/btext.h>
88#endif
89
90#endif /* CONFIG_PPC_OF */
91
92#ifdef CONFIG_MTRR
93#include <asm/mtrr.h>
94#endif
95
96#include <video/radeon.h>
97#include <linux/radeonfb.h>
98
99#include "../edid.h" // MOVE THAT TO include/video
100#include "ati_ids.h"
101#include "radeonfb.h"
102
103#define MAX_MAPPED_VRAM (2048*2048*4)
104#define MIN_MAPPED_VRAM (1024*768*1)
105
106#define CHIP_DEF(id, family, flags) \
107 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
108
109static struct pci_device_id radeonfb_pci_table[] = {
110 /* Mobility M6 */
111 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
112 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
113 /* Radeon VE/7000 */
114 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
115 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
116 /* Radeon IGP320M (U1) */
117 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
118 /* Radeon IGP320 (A3) */
119 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
120 /* IGP330M/340M/350M (U2) */
121 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 /* IGP330/340/350 (A4) */
123 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 /* Mobility 7000 IGP */
125 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
126 /* 7000 IGP (A4+) */
127 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
128 /* 8500 AIW */
129 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
130 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
131 /* 8700/8800 */
132 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
133 /* 8500 */
134 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
135 /* 9100 */
136 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
137 /* Mobility M7 */
138 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 /* 7500 */
141 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
142 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
143 /* Mobility M9 */
144 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
148 /* 9000/Pro */
149 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
150 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
151 /* Mobility 9100 IGP (U3) */
152 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 /* 9100 IGP (A5) */
155 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
156 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 /* Mobility 9200 (M9+) */
158 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
159 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 /* 9200 */
161 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
165 /* 9500 */
166 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
168 /* 9600TX / FireGL Z1 */
169 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
171 /* 9700/9500/Pro/FireGL X1 */
172 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
173 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
176 /* Mobility M10/M11 */
177 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 /* 9600/FireGL T2 */
184 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
190 /* 9800/Pro/FileGL X2 */
191 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
199 /* Newer stuff */
200 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
209 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
210 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
217 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
226 /* Original Radeon/7200 */
227 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
229 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
231 { 0, }
232};
233MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
234
235
236typedef struct {
237 u16 reg;
238 u32 val;
239} reg_val;
240
241
242/* these common regs are cleared before mode setting so they do not
243 * interfere with anything
244 */
245static reg_val common_regs[] = {
246 { OVR_CLR, 0 },
247 { OVR_WID_LEFT_RIGHT, 0 },
248 { OVR_WID_TOP_BOTTOM, 0 },
249 { OV0_SCALE_CNTL, 0 },
250 { SUBPIC_CNTL, 0 },
251 { VIPH_CONTROL, 0 },
252 { I2C_CNTL_1, 0 },
253 { GEN_INT_CNTL, 0 },
254 { CAP0_TRIG_CNTL, 0 },
255 { CAP1_TRIG_CNTL, 0 },
256};
257
258/*
259 * globals
260 */
261
262static char *mode_option;
263static char *monitor_layout;
264static int noaccel = 0;
265static int default_dynclk = -2;
266static int nomodeset = 0;
267static int ignore_edid = 0;
268static int mirror = 0;
269static int panel_yres = 0;
270static int force_dfp = 0;
271static int force_measure_pll = 0;
272#ifdef CONFIG_MTRR
273static int nomtrr = 0;
274#endif
275
276/*
277 * prototypes
278 */
279
280
281#ifdef CONFIG_PPC_OF
282
283#ifdef CONFIG_PMAC_BACKLIGHT
284static int radeon_set_backlight_enable(int on, int level, void *data);
285static int radeon_set_backlight_level(int level, void *data);
286static struct backlight_controller radeon_backlight_controller = {
287 radeon_set_backlight_enable,
288 radeon_set_backlight_level
289};
290#endif /* CONFIG_PMAC_BACKLIGHT */
291
292#endif /* CONFIG_PPC_OF */
293
294static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
295{
296 if (!rinfo->bios_seg)
297 return;
298 pci_unmap_rom(dev, rinfo->bios_seg);
299}
300
301static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
302{
303 void __iomem *rom;
304 u16 dptr;
305 u8 rom_type;
306 size_t rom_size;
307
308 /* If this is a primary card, there is a shadow copy of the
309 * ROM somewhere in the first meg. We will just ignore the copy
310 * and use the ROM directly.
311 */
312
313 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
314 unsigned int temp;
315 temp = INREG(MPP_TB_CONFIG);
316 temp &= 0x00ffffffu;
317 temp |= 0x04 << 24;
318 OUTREG(MPP_TB_CONFIG, temp);
319 temp = INREG(MPP_TB_CONFIG);
320
321 rom = pci_map_rom(dev, &rom_size);
322 if (!rom) {
323 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
324 pci_name(rinfo->pdev));
325 return -ENOMEM;
326 }
327
328 rinfo->bios_seg = rom;
329
330 /* Very simple test to make sure it appeared */
331 if (BIOS_IN16(0) != 0xaa55) {
332 printk(KERN_ERR "radeonfb (%s): Invalid ROM signature %x should be"
333 "0xaa55\n", pci_name(rinfo->pdev), BIOS_IN16(0));
334 goto failed;
335 }
336 /* Look for the PCI data to check the ROM type */
337 dptr = BIOS_IN16(0x18);
338
339 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
340 * for now, until I've verified this works everywhere. The goal here is more
341 * to phase out Open Firmware images.
342 *
343 * Currently, we only look at the first PCI data, we could iteratre and deal with
344 * them all, and we should use fb_bios_start relative to start of image and not
345 * relative start of ROM, but so far, I never found a dual-image ATI card
346 *
347 * typedef struct {
348 * u32 signature; + 0x00
349 * u16 vendor; + 0x04
350 * u16 device; + 0x06
351 * u16 reserved_1; + 0x08
352 * u16 dlen; + 0x0a
353 * u8 drevision; + 0x0c
354 * u8 class_hi; + 0x0d
355 * u16 class_lo; + 0x0e
356 * u16 ilen; + 0x10
357 * u16 irevision; + 0x12
358 * u8 type; + 0x14
359 * u8 indicator; + 0x15
360 * u16 reserved_2; + 0x16
361 * } pci_data_t;
362 */
363 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
364 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
365 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
366 goto anyway;
367 }
368 rom_type = BIOS_IN8(dptr + 0x14);
369 switch(rom_type) {
370 case 0:
371 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
372 break;
373 case 1:
374 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
375 goto failed;
376 case 2:
377 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
378 goto failed;
379 default:
380 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
381 goto failed;
382 }
383 anyway:
384 /* Locate the flat panel infos, do some sanity checking !!! */
385 rinfo->fp_bios_start = BIOS_IN16(0x48);
386 return 0;
387
388 failed:
389 rinfo->bios_seg = NULL;
390 radeon_unmap_ROM(rinfo, dev);
391 return -ENXIO;
392}
393
394#ifdef CONFIG_X86
395static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
396{
397 /* I simplified this code as we used to miss the signatures in
398 * a lot of case. It's now closer to XFree, we just don't check
399 * for signatures at all... Something better will have to be done
400 * if we end up having conflicts
401 */
402 u32 segstart;
403 void __iomem *rom_base = NULL;
404
405 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
406 rom_base = ioremap(segstart, 0x10000);
407 if (rom_base == NULL)
408 return -ENOMEM;
409 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
410 break;
411 iounmap(rom_base);
412 rom_base = NULL;
413 }
414 if (rom_base == NULL)
415 return -ENXIO;
416
417 /* Locate the flat panel infos, do some sanity checking !!! */
418 rinfo->bios_seg = rom_base;
419 rinfo->fp_bios_start = BIOS_IN16(0x48);
420
421 return 0;
422}
423#endif
424
425#ifdef CONFIG_PPC_OF
426/*
427 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
428 * tree. Hopefully, ATI OF driver is kind enough to fill these
429 */
430static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
431{
432 struct device_node *dp = rinfo->of_node;
433 u32 *val;
434
435 if (dp == NULL)
436 return -ENODEV;
437 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
438 if (!val || !*val) {
439 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
440 return -EINVAL;
441 }
442
443 rinfo->pll.ref_clk = (*val) / 10;
444
445 val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
446 if (val && *val)
447 rinfo->pll.sclk = (*val) / 10;
448
449 val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
450 if (val && *val)
451 rinfo->pll.mclk = (*val) / 10;
452
453 return 0;
454}
455#endif /* CONFIG_PPC_OF */
456
457/*
458 * Read PLL infos from chip registers
459 */
460static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
461{
462 unsigned char ppll_div_sel;
463 unsigned Ns, Nm, M;
464 unsigned sclk, mclk, tmp, ref_div;
465 int hTotal, vTotal, num, denom, m, n;
466 unsigned long long hz, vclk;
467 long xtal;
468 struct timeval start_tv, stop_tv;
469 long total_secs, total_usecs;
470 int i;
471
472 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
473 * here, so... --BenH
474 */
475
476 /* Flush PCI buffers ? */
477 tmp = INREG(DEVICE_ID);
478
479 local_irq_disable();
480
481 for(i=0; i<1000000; i++)
482 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
483 break;
484
485 do_gettimeofday(&start_tv);
486
487 for(i=0; i<1000000; i++)
488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
489 break;
490
491 for(i=0; i<1000000; i++)
492 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
493 break;
494
495 do_gettimeofday(&stop_tv);
496
497 local_irq_enable();
498
499 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
500 if (total_secs > 10)
501 return -1;
502 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
503 total_usecs += total_secs * 1000000;
504 if (total_usecs < 0)
505 total_usecs = -total_usecs;
506 hz = 1000000/total_usecs;
507
508 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
509 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
510 vclk = (long long)hTotal * (long long)vTotal * hz;
511
512 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
513 case 0:
514 default:
515 num = 1;
516 denom = 1;
517 break;
518 case 1:
519 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
520 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
521 num = 2*n;
522 denom = 2*m;
523 break;
524 case 2:
525 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
526 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
527 num = 2*n;
528 denom = 2*m;
529 break;
530 }
531
532 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
533 radeon_pll_errata_after_index(rinfo);
534
535 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
536 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
537
538 num *= n;
539 denom *= m;
540
541 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
542 case 1:
543 denom *= 2;
544 break;
545 case 2:
546 denom *= 4;
547 break;
548 case 3:
549 denom *= 8;
550 break;
551 case 4:
552 denom *= 3;
553 break;
554 case 6:
555 denom *= 6;
556 break;
557 case 7:
558 denom *= 12;
559 break;
560 }
561
562 vclk *= denom;
563 do_div(vclk, 1000 * num);
564 xtal = vclk;
565
566 if ((xtal > 26900) && (xtal < 27100))
567 xtal = 2700;
568 else if ((xtal > 14200) && (xtal < 14400))
569 xtal = 1432;
570 else if ((xtal > 29400) && (xtal < 29600))
571 xtal = 2950;
572 else {
573 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
574 return -1;
575 }
576
577 tmp = INPLL(M_SPLL_REF_FB_DIV);
578 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
579
580 Ns = (tmp & 0xff0000) >> 16;
581 Nm = (tmp & 0xff00) >> 8;
582 M = (tmp & 0xff);
583 sclk = round_div((2 * Ns * xtal), (2 * M));
584 mclk = round_div((2 * Nm * xtal), (2 * M));
585
586 /* we're done, hopefully these are sane values */
587 rinfo->pll.ref_clk = xtal;
588 rinfo->pll.ref_div = ref_div;
589 rinfo->pll.sclk = sclk;
590 rinfo->pll.mclk = mclk;
591
592 return 0;
593}
594
595/*
596 * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
597 */
598static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
599{
600 /*
601 * In the case nothing works, these are defaults; they are mostly
602 * incomplete, however. It does provide ppll_max and _min values
603 * even for most other methods, however.
604 */
605 switch (rinfo->chipset) {
606 case PCI_DEVICE_ID_ATI_RADEON_QW:
607 case PCI_DEVICE_ID_ATI_RADEON_QX:
608 rinfo->pll.ppll_max = 35000;
609 rinfo->pll.ppll_min = 12000;
610 rinfo->pll.mclk = 23000;
611 rinfo->pll.sclk = 23000;
612 rinfo->pll.ref_clk = 2700;
613 break;
614 case PCI_DEVICE_ID_ATI_RADEON_QL:
615 case PCI_DEVICE_ID_ATI_RADEON_QN:
616 case PCI_DEVICE_ID_ATI_RADEON_QO:
617 case PCI_DEVICE_ID_ATI_RADEON_Ql:
618 case PCI_DEVICE_ID_ATI_RADEON_BB:
619 rinfo->pll.ppll_max = 35000;
620 rinfo->pll.ppll_min = 12000;
621 rinfo->pll.mclk = 27500;
622 rinfo->pll.sclk = 27500;
623 rinfo->pll.ref_clk = 2700;
624 break;
625 case PCI_DEVICE_ID_ATI_RADEON_Id:
626 case PCI_DEVICE_ID_ATI_RADEON_Ie:
627 case PCI_DEVICE_ID_ATI_RADEON_If:
628 case PCI_DEVICE_ID_ATI_RADEON_Ig:
629 rinfo->pll.ppll_max = 35000;
630 rinfo->pll.ppll_min = 12000;
631 rinfo->pll.mclk = 25000;
632 rinfo->pll.sclk = 25000;
633 rinfo->pll.ref_clk = 2700;
634 break;
635 case PCI_DEVICE_ID_ATI_RADEON_ND:
636 case PCI_DEVICE_ID_ATI_RADEON_NE:
637 case PCI_DEVICE_ID_ATI_RADEON_NF:
638 case PCI_DEVICE_ID_ATI_RADEON_NG:
639 rinfo->pll.ppll_max = 40000;
640 rinfo->pll.ppll_min = 20000;
641 rinfo->pll.mclk = 27000;
642 rinfo->pll.sclk = 27000;
643 rinfo->pll.ref_clk = 2700;
644 break;
645 case PCI_DEVICE_ID_ATI_RADEON_QD:
646 case PCI_DEVICE_ID_ATI_RADEON_QE:
647 case PCI_DEVICE_ID_ATI_RADEON_QF:
648 case PCI_DEVICE_ID_ATI_RADEON_QG:
649 default:
650 rinfo->pll.ppll_max = 35000;
651 rinfo->pll.ppll_min = 12000;
652 rinfo->pll.mclk = 16600;
653 rinfo->pll.sclk = 16600;
654 rinfo->pll.ref_clk = 2700;
655 break;
656 }
657 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
658
659
660#ifdef CONFIG_PPC_OF
661 /*
662 * Retreive PLL infos from Open Firmware first
663 */
664 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
665 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
666 goto found;
667 }
668#endif /* CONFIG_PPC_OF */
669
670 /*
671 * Check out if we have an X86 which gave us some PLL informations
672 * and if yes, retreive them
673 */
674 if (!force_measure_pll && rinfo->bios_seg) {
675 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
676
677 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
678 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
679 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
680 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
681 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
682 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
683
684 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
685 goto found;
686 }
687
688 /*
689 * We didn't get PLL parameters from either OF or BIOS, we try to
690 * probe them
691 */
692 if (radeon_probe_pll_params(rinfo) == 0) {
693 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
694 goto found;
695 }
696
697 /*
698 * Fall back to already-set defaults...
699 */
700 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
701
702found:
703 /*
704 * Some methods fail to retreive SCLK and MCLK values, we apply default
705 * settings in this case (200Mhz). If that really happne often, we could
706 * fetch from registers instead...
707 */
708 if (rinfo->pll.mclk == 0)
709 rinfo->pll.mclk = 20000;
710 if (rinfo->pll.sclk == 0)
711 rinfo->pll.sclk = 20000;
712
713 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
714 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
715 rinfo->pll.ref_div,
716 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
717 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
718 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
719}
720
721static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
722{
723 struct radeonfb_info *rinfo = info->par;
724 struct fb_var_screeninfo v;
725 int nom, den;
726 unsigned int pitch;
727
728 if (radeon_match_mode(rinfo, &v, var))
729 return -EINVAL;
730
731 switch (v.bits_per_pixel) {
732 case 0 ... 8:
733 v.bits_per_pixel = 8;
734 break;
735 case 9 ... 16:
736 v.bits_per_pixel = 16;
737 break;
738 case 17 ... 24:
739#if 0 /* Doesn't seem to work */
740 v.bits_per_pixel = 24;
741 break;
742#endif
743 return -EINVAL;
744 case 25 ... 32:
745 v.bits_per_pixel = 32;
746 break;
747 default:
748 return -EINVAL;
749 }
750
751 switch (var_to_depth(&v)) {
752 case 8:
753 nom = den = 1;
754 v.red.offset = v.green.offset = v.blue.offset = 0;
755 v.red.length = v.green.length = v.blue.length = 8;
756 v.transp.offset = v.transp.length = 0;
757 break;
758 case 15:
759 nom = 2;
760 den = 1;
761 v.red.offset = 10;
762 v.green.offset = 5;
763 v.blue.offset = 0;
764 v.red.length = v.green.length = v.blue.length = 5;
765 v.transp.offset = v.transp.length = 0;
766 break;
767 case 16:
768 nom = 2;
769 den = 1;
770 v.red.offset = 11;
771 v.green.offset = 5;
772 v.blue.offset = 0;
773 v.red.length = 5;
774 v.green.length = 6;
775 v.blue.length = 5;
776 v.transp.offset = v.transp.length = 0;
777 break;
778 case 24:
779 nom = 4;
780 den = 1;
781 v.red.offset = 16;
782 v.green.offset = 8;
783 v.blue.offset = 0;
784 v.red.length = v.blue.length = v.green.length = 8;
785 v.transp.offset = v.transp.length = 0;
786 break;
787 case 32:
788 nom = 4;
789 den = 1;
790 v.red.offset = 16;
791 v.green.offset = 8;
792 v.blue.offset = 0;
793 v.red.length = v.blue.length = v.green.length = 8;
794 v.transp.offset = 24;
795 v.transp.length = 8;
796 break;
797 default:
798 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
799 var->xres, var->yres, var->bits_per_pixel);
800 return -EINVAL;
801 }
802
803 if (v.yres_virtual < v.yres)
804 v.yres_virtual = v.yres;
805 if (v.xres_virtual < v.xres)
806 v.xres_virtual = v.xres;
807
808
809 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
810 * with some panels, though I don't quite like this solution
811 */
812 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
813 v.xres_virtual = v.xres_virtual & ~7ul;
814 } else {
815 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
816 & ~(0x3f)) >> 6;
817 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
818 }
819
820 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
821 return -EINVAL;
822
823 if (v.xres_virtual < v.xres)
824 v.xres = v.xres_virtual;
825
826 if (v.xoffset < 0)
827 v.xoffset = 0;
828 if (v.yoffset < 0)
829 v.yoffset = 0;
830
831 if (v.xoffset > v.xres_virtual - v.xres)
832 v.xoffset = v.xres_virtual - v.xres - 1;
833
834 if (v.yoffset > v.yres_virtual - v.yres)
835 v.yoffset = v.yres_virtual - v.yres - 1;
836
837 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
838 v.transp.offset = v.transp.length =
839 v.transp.msb_right = 0;
840
841 memcpy(var, &v, sizeof(v));
842
843 return 0;
844}
845
846
847static int radeonfb_pan_display (struct fb_var_screeninfo *var,
848 struct fb_info *info)
849{
850 struct radeonfb_info *rinfo = info->par;
851
852 if ((var->xoffset + var->xres > var->xres_virtual)
853 || (var->yoffset + var->yres > var->yres_virtual))
854 return -EINVAL;
855
856 if (rinfo->asleep)
857 return 0;
858
859 radeon_fifo_wait(2);
860 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
861 * var->bits_per_pixel / 8) & ~7);
862 return 0;
863}
864
865
866static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
867 unsigned long arg, struct fb_info *info)
868{
869 struct radeonfb_info *rinfo = info->par;
870 unsigned int tmp;
871 u32 value = 0;
872 int rc;
873
874 switch (cmd) {
875 /*
876 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
877 * and do something better using 2nd CRTC instead of just hackish
878 * routing to second output
879 */
880 case FBIO_RADEON_SET_MIRROR:
881 if (!rinfo->is_mobility)
882 return -EINVAL;
883
884 rc = get_user(value, (__u32 __user *)arg);
885
886 if (rc)
887 return rc;
888
889 radeon_fifo_wait(2);
890 if (value & 0x01) {
891 tmp = INREG(LVDS_GEN_CNTL);
892
893 tmp |= (LVDS_ON | LVDS_BLON);
894 } else {
895 tmp = INREG(LVDS_GEN_CNTL);
896
897 tmp &= ~(LVDS_ON | LVDS_BLON);
898 }
899
900 OUTREG(LVDS_GEN_CNTL, tmp);
901
902 if (value & 0x02) {
903 tmp = INREG(CRTC_EXT_CNTL);
904 tmp |= CRTC_CRT_ON;
905
906 mirror = 1;
907 } else {
908 tmp = INREG(CRTC_EXT_CNTL);
909 tmp &= ~CRTC_CRT_ON;
910
911 mirror = 0;
912 }
913
914 OUTREG(CRTC_EXT_CNTL, tmp);
915
916 return 0;
917 case FBIO_RADEON_GET_MIRROR:
918 if (!rinfo->is_mobility)
919 return -EINVAL;
920
921 tmp = INREG(LVDS_GEN_CNTL);
922 if ((LVDS_ON | LVDS_BLON) & tmp)
923 value |= 0x01;
924
925 tmp = INREG(CRTC_EXT_CNTL);
926 if (CRTC_CRT_ON & tmp)
927 value |= 0x02;
928
929 return put_user(value, (__u32 __user *)arg);
930 default:
931 return -EINVAL;
932 }
933
934 return -EINVAL;
935}
936
937
938int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
939{
940 u32 val;
941 u32 tmp_pix_clks;
942 int unblank = 0;
943
944 if (rinfo->lock_blank)
945 return 0;
946
947 radeon_engine_idle();
948
949 val = INREG(CRTC_EXT_CNTL);
950 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
951 CRTC_VSYNC_DIS);
952 switch (blank) {
953 case FB_BLANK_VSYNC_SUSPEND:
954 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
955 break;
956 case FB_BLANK_HSYNC_SUSPEND:
957 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
958 break;
959 case FB_BLANK_POWERDOWN:
960 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
961 CRTC_HSYNC_DIS);
962 break;
963 case FB_BLANK_NORMAL:
964 val |= CRTC_DISPLAY_DIS;
965 break;
966 case FB_BLANK_UNBLANK:
967 default:
968 unblank = 1;
969 }
970 OUTREG(CRTC_EXT_CNTL, val);
971
972
973 switch (rinfo->mon1_type) {
974 case MT_DFP:
975 if (unblank)
976 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
977 ~(FP_FPON | FP_TMDS_EN));
978 else {
979 if (mode_switch || blank == FB_BLANK_NORMAL)
980 break;
981 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
982 }
983 break;
984 case MT_LCD:
985 del_timer_sync(&rinfo->lvds_timer);
986 val = INREG(LVDS_GEN_CNTL);
987 if (unblank) {
988 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
989 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
990 & (LVDS_DIGON | LVDS_BL_MOD_EN));
991 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
992 OUTREG(LVDS_GEN_CNTL, target_val);
993 else if ((val ^ target_val) != 0) {
994 OUTREG(LVDS_GEN_CNTL, target_val
995 & ~(LVDS_ON | LVDS_BL_MOD_EN));
996 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
997 rinfo->init_state.lvds_gen_cntl |=
998 target_val & LVDS_STATE_MASK;
999 if (mode_switch) {
1000 radeon_msleep(rinfo->panel_info.pwr_delay);
1001 OUTREG(LVDS_GEN_CNTL, target_val);
1002 }
1003 else {
1004 rinfo->pending_lvds_gen_cntl = target_val;
1005 mod_timer(&rinfo->lvds_timer,
1006 jiffies +
1007 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1008 }
1009 }
1010 } else {
1011 val |= LVDS_DISPLAY_DIS;
1012 OUTREG(LVDS_GEN_CNTL, val);
1013
1014 /* We don't do a full switch-off on a simple mode switch */
1015 if (mode_switch || blank == FB_BLANK_NORMAL)
1016 break;
1017
1018 /* Asic bug, when turning off LVDS_ON, we have to make sure
1019 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1020 */
1021 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1022 if (rinfo->is_mobility || rinfo->is_IGP)
1023 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1024 val &= ~(LVDS_BL_MOD_EN);
1025 OUTREG(LVDS_GEN_CNTL, val);
1026 udelay(100);
1027 val &= ~(LVDS_ON | LVDS_EN);
1028 OUTREG(LVDS_GEN_CNTL, val);
1029 val &= ~LVDS_DIGON;
1030 rinfo->pending_lvds_gen_cntl = val;
1031 mod_timer(&rinfo->lvds_timer,
1032 jiffies +
1033 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1034 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1035 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1036 if (rinfo->is_mobility || rinfo->is_IGP)
1037 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1038 }
1039 break;
1040 case MT_CRT:
1041 // todo: powerdown DAC
1042 default:
1043 break;
1044 }
1045
1046 /* let fbcon do a soft blank for us */
1047 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1048}
1049
1050static int radeonfb_blank (int blank, struct fb_info *info)
1051{
1052 struct radeonfb_info *rinfo = info->par;
1053
1054 if (rinfo->asleep)
1055 return 0;
1056
1057 return radeon_screen_blank(rinfo, blank, 0);
1058}
1059
1060static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1061 unsigned blue, unsigned transp, struct fb_info *info)
1062{
1063 struct radeonfb_info *rinfo = info->par;
1064 u32 pindex;
1065 unsigned int i;
1066
1067 if (regno > 255)
1068 return 1;
1069
1070 red >>= 8;
1071 green >>= 8;
1072 blue >>= 8;
1073 rinfo->palette[regno].red = red;
1074 rinfo->palette[regno].green = green;
1075 rinfo->palette[regno].blue = blue;
1076
1077 /* default */
1078 pindex = regno;
1079
1080 if (!rinfo->asleep) {
1081 u32 dac_cntl2, vclk_cntl = 0;
1082
1083 radeon_fifo_wait(9);
1084 if (rinfo->is_mobility) {
1085 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1086 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1087 }
1088
1089 /* Make sure we are on first palette */
1090 if (rinfo->has_CRTC2) {
1091 dac_cntl2 = INREG(DAC_CNTL2);
1092 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1093 OUTREG(DAC_CNTL2, dac_cntl2);
1094 }
1095
1096 if (rinfo->bpp == 16) {
1097 pindex = regno * 8;
1098
1099 if (rinfo->depth == 16 && regno > 63)
1100 return 1;
1101 if (rinfo->depth == 15 && regno > 31)
1102 return 1;
1103
1104 /* For 565, the green component is mixed one order below */
1105 if (rinfo->depth == 16) {
1106 OUTREG(PALETTE_INDEX, pindex>>1);
1107 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1108 (green << 8) | (rinfo->palette[regno>>1].blue));
1109 green = rinfo->palette[regno<<1].green;
1110 }
1111 }
1112
1113 if (rinfo->depth != 16 || regno < 32) {
1114 OUTREG(PALETTE_INDEX, pindex);
1115 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1116 }
1117 if (rinfo->is_mobility)
1118 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1119 }
1120 if (regno < 16) {
1121 u32 *pal = info->pseudo_palette;
1122 switch (rinfo->depth) {
1123 case 15:
1124 pal[regno] = (regno << 10) | (regno << 5) | regno;
1125 break;
1126 case 16:
1127 pal[regno] = (regno << 11) | (regno << 5) | regno;
1128 break;
1129 case 24:
1130 pal[regno] = (regno << 16) | (regno << 8) | regno;
1131 break;
1132 case 32:
1133 i = (regno << 8) | regno;
1134 pal[regno] = (i << 16) | i;
1135 break;
1136 }
1137 }
1138 return 0;
1139}
1140
1141
1142static void radeon_save_state (struct radeonfb_info *rinfo,
1143 struct radeon_regs *save)
1144{
1145 /* CRTC regs */
1146 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1147 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1148 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1149 save->dac_cntl = INREG(DAC_CNTL);
1150 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1151 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1152 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1153 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1154 save->crtc_pitch = INREG(CRTC_PITCH);
1155 save->surface_cntl = INREG(SURFACE_CNTL);
1156
1157 /* FP regs */
1158 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1159 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1160 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1161 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1162 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1163 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1164 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1165 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1166 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1167 save->tmds_crc = INREG(TMDS_CRC);
1168 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1169 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1170
1171 /* PLL regs */
1172 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1173 radeon_pll_errata_after_index(rinfo);
1174 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1175 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1176}
1177
1178
1179static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1180{
1181 int i;
1182
1183 radeon_fifo_wait(20);
1184
1185 /* Workaround from XFree */
1186 if (rinfo->is_mobility) {
1187 /* A temporal workaround for the occational blanking on certain laptop
1188 * panels. This appears to related to the PLL divider registers
1189 * (fail to lock?). It occurs even when all dividers are the same
1190 * with their old settings. In this case we really don't need to
1191 * fiddle with PLL registers. By doing this we can avoid the blanking
1192 * problem with some panels.
1193 */
1194 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1195 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1196 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1197 /* We still have to force a switch to selected PPLL div thanks to
1198 * an XFree86 driver bug which will switch it away in some cases
1199 * even when using UseFDev */
1200 OUTREGP(CLOCK_CNTL_INDEX,
1201 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1202 ~PPLL_DIV_SEL_MASK);
1203 radeon_pll_errata_after_index(rinfo);
1204 radeon_pll_errata_after_data(rinfo);
1205 return;
1206 }
1207 }
1208
1209 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1210 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1211
1212 /* Reset PPLL & enable atomic update */
1213 OUTPLLP(PPLL_CNTL,
1214 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1215 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1216
1217 /* Switch to selected PPLL divider */
1218 OUTREGP(CLOCK_CNTL_INDEX,
1219 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1220 ~PPLL_DIV_SEL_MASK);
1221 radeon_pll_errata_after_index(rinfo);
1222 radeon_pll_errata_after_data(rinfo);
1223
1224 /* Set PPLL ref. div */
1225 if (rinfo->family == CHIP_FAMILY_R300 ||
1226 rinfo->family == CHIP_FAMILY_RS300 ||
1227 rinfo->family == CHIP_FAMILY_R350 ||
1228 rinfo->family == CHIP_FAMILY_RV350) {
1229 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1230 /* When restoring console mode, use saved PPLL_REF_DIV
1231 * setting.
1232 */
1233 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1234 } else {
1235 /* R300 uses ref_div_acc field as real ref divider */
1236 OUTPLLP(PPLL_REF_DIV,
1237 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1238 ~R300_PPLL_REF_DIV_ACC_MASK);
1239 }
1240 } else
1241 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1242
1243 /* Set PPLL divider 3 & post divider*/
1244 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1245 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1246
1247 /* Write update */
1248 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1249 ;
1250 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1251
1252 /* Wait read update complete */
1253 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1254 the cause yet, but this workaround will mask the problem for now.
1255 Other chips usually will pass at the very first test, so the
1256 workaround shouldn't have any effect on them. */
1257 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1258 ;
1259
1260 OUTPLL(HTOTAL_CNTL, 0);
1261
1262 /* Clear reset & atomic update */
1263 OUTPLLP(PPLL_CNTL, 0,
1264 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1265
1266 /* We may want some locking ... oh well */
1267 radeon_msleep(5);
1268
1269 /* Switch back VCLK source to PPLL */
1270 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1271}
1272
1273/*
1274 * Timer function for delayed LVDS panel power up/down
1275 */
1276static void radeon_lvds_timer_func(unsigned long data)
1277{
1278 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1279
1280 radeon_engine_idle();
1281
1282 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1283}
1284
1285/*
1286 * Apply a video mode. This will apply the whole register set, including
1287 * the PLL registers, to the card
1288 */
1289void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1290 int regs_only)
1291{
1292 int i;
1293 int primary_mon = PRIMARY_MONITOR(rinfo);
1294
1295 if (nomodeset)
1296 return;
1297
1298 if (!regs_only)
1299 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1300
1301 radeon_fifo_wait(31);
1302 for (i=0; i<10; i++)
1303 OUTREG(common_regs[i].reg, common_regs[i].val);
1304
1305 /* Apply surface registers */
1306 for (i=0; i<8; i++) {
1307 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1308 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1309 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1310 }
1311
1312 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1313 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1314 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1315 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1316 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1317 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1318 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1319 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1320 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1321 OUTREG(CRTC_OFFSET, 0);
1322 OUTREG(CRTC_OFFSET_CNTL, 0);
1323 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1324 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1325
1326 radeon_write_pll_regs(rinfo, mode);
1327
1328 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1329 radeon_fifo_wait(10);
1330 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1331 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1332 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1333 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1334 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1335 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1336 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1337 OUTREG(TMDS_CRC, mode->tmds_crc);
1338 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1339 }
1340
1341 if (!regs_only)
1342 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1343
1344 radeon_fifo_wait(2);
1345 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1346
1347 return;
1348}
1349
1350/*
1351 * Calculate the PLL values for a given mode
1352 */
1353static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1354 unsigned long freq)
1355{
1356 const struct {
1357 int divider;
1358 int bitvalue;
1359 } *post_div,
1360 post_divs[] = {
1361 { 1, 0 },
1362 { 2, 1 },
1363 { 4, 2 },
1364 { 8, 3 },
1365 { 3, 4 },
1366 { 16, 5 },
1367 { 6, 6 },
1368 { 12, 7 },
1369 { 0, 0 },
1370 };
1371 int fb_div, pll_output_freq = 0;
1372 int uses_dvo = 0;
1373
1374 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1375 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1376 * recent than an r(v)100...
1377 */
1378#if 1
1379 /* XXX I had reports of flicker happening with the cinema display
1380 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1381 * this case. This could just be a bandwidth calculation issue, I
1382 * haven't implemented the bandwidth code yet, but in the meantime,
1383 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1384 * I haven't seen a case were were absolutely needed an odd PLL
1385 * divider. I'll find a better fix once I have more infos on the
1386 * real cause of the problem.
1387 */
1388 while (rinfo->has_CRTC2) {
1389 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1390 u32 disp_output_cntl;
1391 int source;
1392
1393 /* FP2 path not enabled */
1394 if ((fp2_gen_cntl & FP2_ON) == 0)
1395 break;
1396 /* Not all chip revs have the same format for this register,
1397 * extract the source selection
1398 */
1399 if (rinfo->family == CHIP_FAMILY_R200 ||
1400 rinfo->family == CHIP_FAMILY_R300 ||
1401 rinfo->family == CHIP_FAMILY_R350 ||
1402 rinfo->family == CHIP_FAMILY_RV350) {
1403 source = (fp2_gen_cntl >> 10) & 0x3;
1404 /* sourced from transform unit, check for transform unit
1405 * own source
1406 */
1407 if (source == 3) {
1408 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1409 source = (disp_output_cntl >> 12) & 0x3;
1410 }
1411 } else
1412 source = (fp2_gen_cntl >> 13) & 0x1;
1413 /* sourced from CRTC2 -> exit */
1414 if (source == 1)
1415 break;
1416
1417 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1418 uses_dvo = 1;
1419 break;
1420 }
1421#else
1422 uses_dvo = 1;
1423#endif
1424 if (freq > rinfo->pll.ppll_max)
1425 freq = rinfo->pll.ppll_max;
1426 if (freq*12 < rinfo->pll.ppll_min)
1427 freq = rinfo->pll.ppll_min / 12;
1428 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1429 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1430
1431 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1432 pll_output_freq = post_div->divider * freq;
1433 /* If we output to the DVO port (external TMDS), we don't allow an
1434 * odd PLL divider as those aren't supported on this path
1435 */
1436 if (uses_dvo && (post_div->divider & 1))
1437 continue;
1438 if (pll_output_freq >= rinfo->pll.ppll_min &&
1439 pll_output_freq <= rinfo->pll.ppll_max)
1440 break;
1441 }
1442
1443 /* If we fall through the bottom, try the "default value"
1444 given by the terminal post_div->bitvalue */
1445 if ( !post_div->divider ) {
1446 post_div = &post_divs[post_div->bitvalue];
1447 pll_output_freq = post_div->divider * freq;
1448 }
1449 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1450 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1451 pll_output_freq);
1452
1453 /* If we fall through the bottom, try the "default value"
1454 given by the terminal post_div->bitvalue */
1455 if ( !post_div->divider ) {
1456 post_div = &post_divs[post_div->bitvalue];
1457 pll_output_freq = post_div->divider * freq;
1458 }
1459 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1460 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1461 pll_output_freq);
1462
1463 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1464 rinfo->pll.ref_clk);
1465 regs->ppll_ref_div = rinfo->pll.ref_div;
1466 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1467
1468 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1469 RTRACE("fb_div = 0x%x\n", fb_div);
1470 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1471}
1472
1473static int radeonfb_set_par(struct fb_info *info)
1474{
1475 struct radeonfb_info *rinfo = info->par;
1476 struct fb_var_screeninfo *mode = &info->var;
1477 struct radeon_regs *newmode;
1478 int hTotal, vTotal, hSyncStart, hSyncEnd,
1479 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1480 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1481 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1482 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1483 int i, freq;
1484 int format = 0;
1485 int nopllcalc = 0;
1486 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1487 int primary_mon = PRIMARY_MONITOR(rinfo);
1488 int depth = var_to_depth(mode);
1489 int use_rmx = 0;
1490
1491 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1492 if (!newmode)
1493 return -ENOMEM;
1494
1495 /* We always want engine to be idle on a mode switch, even
1496 * if we won't actually change the mode
1497 */
1498 radeon_engine_idle();
1499
1500 hSyncStart = mode->xres + mode->right_margin;
1501 hSyncEnd = hSyncStart + mode->hsync_len;
1502 hTotal = hSyncEnd + mode->left_margin;
1503
1504 vSyncStart = mode->yres + mode->lower_margin;
1505 vSyncEnd = vSyncStart + mode->vsync_len;
1506 vTotal = vSyncEnd + mode->upper_margin;
1507 pixClock = mode->pixclock;
1508
1509 sync = mode->sync;
1510 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1511 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1512
1513 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1514 if (rinfo->panel_info.xres < mode->xres)
1515 mode->xres = rinfo->panel_info.xres;
1516 if (rinfo->panel_info.yres < mode->yres)
1517 mode->yres = rinfo->panel_info.yres;
1518
1519 hTotal = mode->xres + rinfo->panel_info.hblank;
1520 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1521 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1522
1523 vTotal = mode->yres + rinfo->panel_info.vblank;
1524 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1525 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1526
1527 h_sync_pol = !rinfo->panel_info.hAct_high;
1528 v_sync_pol = !rinfo->panel_info.vAct_high;
1529
1530 pixClock = 100000000 / rinfo->panel_info.clock;
1531
1532 if (rinfo->panel_info.use_bios_dividers) {
1533 nopllcalc = 1;
1534 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1535 (rinfo->panel_info.post_divider << 16);
1536 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1537 }
1538 }
1539 dotClock = 1000000000 / pixClock;
1540 freq = dotClock / 10; /* x100 */
1541
1542 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1543 hSyncStart, hSyncEnd, hTotal);
1544 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1545 vSyncStart, vSyncEnd, vTotal);
1546
1547 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1548 vsync_wid = vSyncEnd - vSyncStart;
1549 if (hsync_wid == 0)
1550 hsync_wid = 1;
1551 else if (hsync_wid > 0x3f) /* max */
1552 hsync_wid = 0x3f;
1553
1554 if (vsync_wid == 0)
1555 vsync_wid = 1;
1556 else if (vsync_wid > 0x1f) /* max */
1557 vsync_wid = 0x1f;
1558
1559 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1560 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1561
1562 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1563
1564 format = radeon_get_dstbpp(depth);
1565 bytpp = mode->bits_per_pixel >> 3;
1566
1567 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1568 hsync_fudge = hsync_fudge_fp[format-1];
1569 else
1570 hsync_fudge = hsync_adj_tab[format-1];
1571
1572 hsync_start = hSyncStart - 8 + hsync_fudge;
1573
1574 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1575 (format << 8);
1576
1577 /* Clear auto-center etc... */
1578 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1579 newmode->crtc_more_cntl &= 0xfffffff0;
1580
1581 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1582 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1583 if (mirror)
1584 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1585
1586 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1587 CRTC_INTERLACE_EN);
1588 } else {
1589 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1590 CRTC_CRT_ON;
1591 }
1592
1593 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1594 DAC_8BIT_EN;
1595
1596 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1597 (((mode->xres / 8) - 1) << 16));
1598
1599 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1600 (hsync_wid << 16) | (h_sync_pol << 23));
1601
1602 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1603 ((mode->yres - 1) << 16);
1604
1605 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1606 (vsync_wid << 16) | (v_sync_pol << 23));
1607
1608 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1609 /* We first calculate the engine pitch */
1610 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1611 & ~(0x3f)) >> 6;
1612
1613 /* Then, re-multiply it to get the CRTC pitch */
1614 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1615 } else
1616 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1617
1618 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1619
1620 /*
1621 * It looks like recent chips have a problem with SURFACE_CNTL,
1622 * setting SURF_TRANSLATION_DIS completely disables the
1623 * swapper as well, so we leave it unset now.
1624 */
1625 newmode->surface_cntl = 0;
1626
1627#if defined(__BIG_ENDIAN)
1628
1629 /* Setup swapping on both apertures, though we currently
1630 * only use aperture 0, enabling swapper on aperture 1
1631 * won't harm
1632 */
1633 switch (mode->bits_per_pixel) {
1634 case 16:
1635 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1636 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1637 break;
1638 case 24:
1639 case 32:
1640 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1641 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1642 break;
1643 }
1644#endif
1645
1646 /* Clear surface registers */
1647 for (i=0; i<8; i++) {
1648 newmode->surf_lower_bound[i] = 0;
1649 newmode->surf_upper_bound[i] = 0x1f;
1650 newmode->surf_info[i] = 0;
1651 }
1652
1653 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1654 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1655 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1656 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1657
1658 rinfo->bpp = mode->bits_per_pixel;
1659 rinfo->depth = depth;
1660
1661 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1662 RTRACE("freq = %lu\n", (unsigned long)freq);
1663
1664 /* We use PPLL_DIV_3 */
1665 newmode->clk_cntl_index = 0x300;
1666
1667 /* Calculate PPLL value if necessary */
1668 if (!nopllcalc)
1669 radeon_calc_pll_regs(rinfo, newmode, freq);
1670
1671 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1672
1673 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1674 unsigned int hRatio, vRatio;
1675
1676 if (mode->xres > rinfo->panel_info.xres)
1677 mode->xres = rinfo->panel_info.xres;
1678 if (mode->yres > rinfo->panel_info.yres)
1679 mode->yres = rinfo->panel_info.yres;
1680
1681 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1682 << HORZ_PANEL_SHIFT);
1683 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1684 << VERT_PANEL_SHIFT);
1685
1686 if (mode->xres != rinfo->panel_info.xres) {
1687 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1688 rinfo->panel_info.xres);
1689 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1690 (newmode->fp_horz_stretch &
1691 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1692 HORZ_AUTO_RATIO_INC)));
1693 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1694 HORZ_STRETCH_ENABLE);
1695 use_rmx = 1;
1696 }
1697 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1698
1699 if (mode->yres != rinfo->panel_info.yres) {
1700 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1701 rinfo->panel_info.yres);
1702 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1703 (newmode->fp_vert_stretch &
1704 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1705 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1706 VERT_STRETCH_ENABLE);
1707 use_rmx = 1;
1708 }
1709 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1710
1711 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1712 ~(FP_SEL_CRTC2 |
1713 FP_RMX_HVSYNC_CONTROL_EN |
1714 FP_DFP_SYNC_SEL |
1715 FP_CRT_SYNC_SEL |
1716 FP_CRTC_LOCK_8DOT |
1717 FP_USE_SHADOW_EN |
1718 FP_CRTC_USE_SHADOW_VEND |
1719 FP_CRT_SYNC_ALT));
1720
1721 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1722 FP_CRTC_DONT_SHADOW_HEND |
1723 FP_PANEL_FORMAT);
1724
1725 if (IS_R300_VARIANT(rinfo) ||
1726 (rinfo->family == CHIP_FAMILY_R200)) {
1727 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1728 if (use_rmx)
1729 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1730 else
1731 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1732 } else
1733 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1734
1735 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1736 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1737 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1738 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1739
1740 if (primary_mon == MT_LCD) {
1741 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1742 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1743 } else {
1744 /* DFP */
1745 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1746 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1747 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1748 if (IS_R300_VARIANT(rinfo) ||
1749 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1750 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1751 else
1752 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1753 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1754 }
1755
1756 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1757 (((mode->xres / 8) - 1) << 16));
1758 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1759 ((mode->yres - 1) << 16);
1760 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1761 (hsync_wid << 16) | (h_sync_pol << 23));
1762 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1763 (vsync_wid << 16) | (v_sync_pol << 23));
1764 }
1765
1766 /* do it! */
1767 if (!rinfo->asleep) {
1768 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1769 radeon_write_mode (rinfo, newmode, 0);
1770 /* (re)initialize the engine */
1771 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1772 radeonfb_engine_init (rinfo);
1773 }
1774 /* Update fix */
1775 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1776 info->fix.line_length = rinfo->pitch*64;
1777 else
1778 info->fix.line_length = mode->xres_virtual
1779 * ((mode->bits_per_pixel + 1) / 8);
1780 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1781 : FB_VISUAL_DIRECTCOLOR;
1782
1783#ifdef CONFIG_BOOTX_TEXT
1784 /* Update debug text engine */
1785 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1786 rinfo->depth, info->fix.line_length);
1787#endif
1788
1789 kfree(newmode);
1790 return 0;
1791}
1792
1793
1794static struct fb_ops radeonfb_ops = {
1795 .owner = THIS_MODULE,
1796 .fb_check_var = radeonfb_check_var,
1797 .fb_set_par = radeonfb_set_par,
1798 .fb_setcolreg = radeonfb_setcolreg,
1799 .fb_pan_display = radeonfb_pan_display,
1800 .fb_blank = radeonfb_blank,
1801 .fb_ioctl = radeonfb_ioctl,
1802 .fb_sync = radeonfb_sync,
1803 .fb_fillrect = radeonfb_fillrect,
1804 .fb_copyarea = radeonfb_copyarea,
1805 .fb_imageblit = radeonfb_imageblit,
1806 .fb_cursor = soft_cursor,
1807};
1808
1809
1810static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1811{
1812 struct fb_info *info = rinfo->info;
1813
1814 info->par = rinfo;
1815 info->pseudo_palette = rinfo->pseudo_palette;
1816 info->flags = FBINFO_DEFAULT
1817 | FBINFO_HWACCEL_COPYAREA
1818 | FBINFO_HWACCEL_FILLRECT
1819 | FBINFO_HWACCEL_XPAN
1820 | FBINFO_HWACCEL_YPAN;
1821 info->fbops = &radeonfb_ops;
1822 info->screen_base = rinfo->fb_base;
1823 info->screen_size = rinfo->mapped_vram;
1824 /* Fill fix common fields */
1825 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1826 info->fix.smem_start = rinfo->fb_base_phys;
1827 info->fix.smem_len = rinfo->video_ram;
1828 info->fix.type = FB_TYPE_PACKED_PIXELS;
1829 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1830 info->fix.xpanstep = 8;
1831 info->fix.ypanstep = 1;
1832 info->fix.ywrapstep = 0;
1833 info->fix.type_aux = 0;
1834 info->fix.mmio_start = rinfo->mmio_base_phys;
1835 info->fix.mmio_len = RADEON_REGSIZE;
1836 info->fix.accel = FB_ACCEL_ATI_RADEON;
1837
1838 fb_alloc_cmap(&info->cmap, 256, 0);
1839
1840 if (noaccel)
1841 info->flags |= FBINFO_HWACCEL_DISABLED;
1842
1843 return 0;
1844}
1845
1846
1847#ifdef CONFIG_PMAC_BACKLIGHT
1848
1849/* TODO: Dbl check these tables, we don't go up to full ON backlight
1850 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1851 * having some more official numbers from ATI
1852 */
1853static int backlight_conv_m6[] = {
1854 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1855 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1856};
1857static int backlight_conv_m7[] = {
1858 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1859 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1860};
1861
1862#define BACKLIGHT_LVDS_OFF
1863#undef BACKLIGHT_DAC_OFF
1864
1865/* We turn off the LCD completely instead of just dimming the backlight.
1866 * This provides some greater power saving and the display is useless
1867 * without backlight anyway.
1868 */
1869static int radeon_set_backlight_enable(int on, int level, void *data)
1870{
1871 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1872 u32 lvds_gen_cntl, tmpPixclksCntl;
1873 int* conv_table;
1874
1875 if (rinfo->mon1_type != MT_LCD)
1876 return 0;
1877
1878 /* Pardon me for that hack... maybe some day we can figure
1879 * out in what direction backlight should work on a given
1880 * panel ?
1881 */
1882 if ((rinfo->family == CHIP_FAMILY_RV200 ||
1883 rinfo->family == CHIP_FAMILY_RV250 ||
1884 rinfo->family == CHIP_FAMILY_RV280 ||
1885 rinfo->family == CHIP_FAMILY_RV350) &&
1886 !machine_is_compatible("PowerBook4,3") &&
1887 !machine_is_compatible("PowerBook6,3") &&
1888 !machine_is_compatible("PowerBook6,5"))
1889 conv_table = backlight_conv_m7;
1890 else
1891 conv_table = backlight_conv_m6;
1892
1893 del_timer_sync(&rinfo->lvds_timer);
1894 radeon_engine_idle();
1895
1896 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1897 if (on && (level > BACKLIGHT_OFF)) {
1898 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1899 if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
1900 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
1901 lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
1902 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1903 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1904 lvds_gen_cntl |= (conv_table[level] <<
1905 LVDS_BL_MOD_LEVEL_SHIFT);
1906 lvds_gen_cntl |= LVDS_ON;
1907 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
1908 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
1909 mod_timer(&rinfo->lvds_timer,
1910 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1911 } else {
1912 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1913 lvds_gen_cntl |= (conv_table[level] <<
1914 LVDS_BL_MOD_LEVEL_SHIFT);
1915 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1916 }
1917 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1918 rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
1919 & LVDS_STATE_MASK;
1920 } else {
1921 /* Asic bug, when turning off LVDS_ON, we have to make sure
1922 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1923 */
1924 tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1925 if (rinfo->is_mobility || rinfo->is_IGP)
1926 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1927 lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
1928 lvds_gen_cntl |= (conv_table[0] <<
1929 LVDS_BL_MOD_LEVEL_SHIFT);
1930 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
1931 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1932 udelay(100);
1933 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
1934 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1935 lvds_gen_cntl &= ~(LVDS_DIGON);
1936 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
1937 mod_timer(&rinfo->lvds_timer,
1938 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1939 if (rinfo->is_mobility || rinfo->is_IGP)
1940 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
1941 }
1942 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1943 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
1944
1945 return 0;
1946}
1947
1948
1949static int radeon_set_backlight_level(int level, void *data)
1950{
1951 return radeon_set_backlight_enable(1, level, data);
1952}
1953#endif /* CONFIG_PMAC_BACKLIGHT */
1954
1955
1956/*
1957 * This reconfigure the card's internal memory map. In theory, we'd like
1958 * to setup the card's memory at the same address as it's PCI bus address,
1959 * and the AGP aperture right after that so that system RAM on 32 bits
1960 * machines at least, is directly accessible. However, doing so would
1961 * conflict with the current XFree drivers...
1962 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1963 * on the proper way to set this up and duplicate this here. In the meantime,
1964 * I put the card's memory at 0 in card space and AGP at some random high
1965 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1966 */
1967#ifdef CONFIG_PPC_OF
1968#undef SET_MC_FB_FROM_APERTURE
1969static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1970{
1971 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1972 u32 save_crtc_ext_cntl;
1973 u32 aper_base, aper_size;
1974 u32 agp_base;
1975
1976 /* First, we disable display to avoid interfering */
1977 if (rinfo->has_CRTC2) {
1978 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1979 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1980 }
1981 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1982 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1983
1984 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1985 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1986 mdelay(100);
1987
1988 aper_base = INREG(CONFIG_APER_0_BASE);
1989 aper_size = INREG(CONFIG_APER_SIZE);
1990
1991#ifdef SET_MC_FB_FROM_APERTURE
1992 /* Set framebuffer to be at the same address as set in PCI BAR */
1993 OUTREG(MC_FB_LOCATION,
1994 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1995 rinfo->fb_local_base = aper_base;
1996#else
1997 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1998 rinfo->fb_local_base = 0;
1999#endif
2000 agp_base = aper_base + aper_size;
2001 if (agp_base & 0xf0000000)
2002 agp_base = (aper_base | 0x0fffffff) + 1;
2003
2004 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2005 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
2006 * always the case on PPCs afaik.
2007 */
2008#ifdef SET_MC_FB_FROM_APERTURE
2009 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2010#else
2011 OUTREG(MC_AGP_LOCATION, 0xffffe000);
2012#endif
2013
2014 /* Fixup the display base addresses & engine offsets while we
2015 * are at it as well
2016 */
2017#ifdef SET_MC_FB_FROM_APERTURE
2018 OUTREG(DISPLAY_BASE_ADDR, aper_base);
2019 if (rinfo->has_CRTC2)
2020 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2021 OUTREG(OV0_BASE_ADDR, aper_base);
2022#else
2023 OUTREG(DISPLAY_BASE_ADDR, 0);
2024 if (rinfo->has_CRTC2)
2025 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2026 OUTREG(OV0_BASE_ADDR, 0);
2027#endif
2028 mdelay(100);
2029
2030 /* Restore display settings */
2031 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2032 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2033 if (rinfo->has_CRTC2)
2034 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2035
2036 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2037 aper_base,
2038 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2039 0xffff0000 | (agp_base >> 16));
2040}
2041#endif /* CONFIG_PPC_OF */
2042
2043
2044static void radeon_identify_vram(struct radeonfb_info *rinfo)
2045{
2046 u32 tmp;
2047
2048 /* framebuffer size */
2049 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2050 (rinfo->family == CHIP_FAMILY_RS200) ||
2051 (rinfo->family == CHIP_FAMILY_RS300)) {
2052 u32 tom = INREG(NB_TOM);
2053 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2054
2055 radeon_fifo_wait(6);
2056 OUTREG(MC_FB_LOCATION, tom);
2057 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2058 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2059 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2060
2061 /* This is supposed to fix the crtc2 noise problem. */
2062 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2063
2064 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2065 (rinfo->family == CHIP_FAMILY_RS200)) {
2066 /* This is to workaround the asic bug for RMX, some versions
2067 of BIOS dosen't have this register initialized correctly.
2068 */
2069 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2070 ~CRTC_H_CUTOFF_ACTIVE_EN);
2071 }
2072 } else {
2073 tmp = INREG(CONFIG_MEMSIZE);
2074 }
2075
2076 /* mem size is bits [28:0], mask off the rest */
2077 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2078
2079 /*
2080 * Hack to get around some busted production M6's
2081 * reporting no ram
2082 */
2083 if (rinfo->video_ram == 0) {
2084 switch (rinfo->pdev->device) {
2085 case PCI_CHIP_RADEON_LY:
2086 case PCI_CHIP_RADEON_LZ:
2087 rinfo->video_ram = 8192 * 1024;
2088 break;
2089 default:
2090 break;
2091 }
2092 }
2093
2094
2095 /*
2096 * Now try to identify VRAM type
2097 */
2098 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2099 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2100 rinfo->vram_ddr = 1;
2101 else
2102 rinfo->vram_ddr = 0;
2103
2104 tmp = INREG(MEM_CNTL);
2105 if (IS_R300_VARIANT(rinfo)) {
2106 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2107 switch (tmp) {
2108 case 0: rinfo->vram_width = 64; break;
2109 case 1: rinfo->vram_width = 128; break;
2110 case 2: rinfo->vram_width = 256; break;
2111 default: rinfo->vram_width = 128; break;
2112 }
2113 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2114 (rinfo->family == CHIP_FAMILY_RS100) ||
2115 (rinfo->family == CHIP_FAMILY_RS200)){
2116 if (tmp & RV100_MEM_HALF_MODE)
2117 rinfo->vram_width = 32;
2118 else
2119 rinfo->vram_width = 64;
2120 } else {
2121 if (tmp & MEM_NUM_CHANNELS_MASK)
2122 rinfo->vram_width = 128;
2123 else
2124 rinfo->vram_width = 64;
2125 }
2126
2127 /* This may not be correct, as some cards can have half of channel disabled
2128 * ToDo: identify these cases
2129 */
2130
2131 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2132 pci_name(rinfo->pdev),
2133 rinfo->video_ram / 1024,
2134 rinfo->vram_ddr ? "DDR" : "SDRAM",
2135 rinfo->vram_width);
2136}
2137
2138/*
2139 * Sysfs
2140 */
2141
2142static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2143{
2144 if (off > EDID_LENGTH)
2145 return 0;
2146
2147 if (off + count > EDID_LENGTH)
2148 count = EDID_LENGTH - off;
2149
2150 memcpy(buf, edid + off, count);
2151
2152 return count;
2153}
2154
2155
2156static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2157{
2158 struct device *dev = container_of(kobj, struct device, kobj);
2159 struct pci_dev *pdev = to_pci_dev(dev);
2160 struct fb_info *info = pci_get_drvdata(pdev);
2161 struct radeonfb_info *rinfo = info->par;
2162
2163 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2164}
2165
2166
2167static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2168{
2169 struct device *dev = container_of(kobj, struct device, kobj);
2170 struct pci_dev *pdev = to_pci_dev(dev);
2171 struct fb_info *info = pci_get_drvdata(pdev);
2172 struct radeonfb_info *rinfo = info->par;
2173
2174 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2175}
2176
2177static struct bin_attribute edid1_attr = {
2178 .attr = {
2179 .name = "edid1",
2180 .owner = THIS_MODULE,
2181 .mode = 0444,
2182 },
2183 .size = EDID_LENGTH,
2184 .read = radeon_show_edid1,
2185};
2186
2187static struct bin_attribute edid2_attr = {
2188 .attr = {
2189 .name = "edid2",
2190 .owner = THIS_MODULE,
2191 .mode = 0444,
2192 },
2193 .size = EDID_LENGTH,
2194 .read = radeon_show_edid2,
2195};
2196
2197
2198static int radeonfb_pci_register (struct pci_dev *pdev,
2199 const struct pci_device_id *ent)
2200{
2201 struct fb_info *info;
2202 struct radeonfb_info *rinfo;
2203 int ret;
2204
2205 RTRACE("radeonfb_pci_register BEGIN\n");
2206
2207 /* Enable device in PCI config */
2208 ret = pci_enable_device(pdev);
2209 if (ret < 0) {
2210 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2211 pci_name(pdev));
2212 goto err_out;
2213 }
2214
2215 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2216 if (!info) {
2217 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2218 pci_name(pdev));
2219 ret = -ENOMEM;
2220 goto err_disable;
2221 }
2222 rinfo = info->par;
2223 rinfo->info = info;
2224 rinfo->pdev = pdev;
2225
2226 spin_lock_init(&rinfo->reg_lock);
2227 init_timer(&rinfo->lvds_timer);
2228 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2229 rinfo->lvds_timer.data = (unsigned long)rinfo;
2230
2231 strcpy(rinfo->name, "ATI Radeon XX ");
2232 rinfo->name[11] = ent->device >> 8;
2233 rinfo->name[12] = ent->device & 0xFF;
2234 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2235 rinfo->chipset = pdev->device;
2236 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2237 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2238 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2239
2240 /* Set base addrs */
2241 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2242 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2243
2244 /* request the mem regions */
2245 ret = pci_request_regions(pdev, "radeonfb");
2246 if (ret < 0) {
2247 printk( KERN_ERR "radeonfb (%s): cannot reserve PCI regions."
2248 " Someone already got them?\n", pci_name(rinfo->pdev));
2249 goto err_release_fb;
2250 }
2251
2252 /* map the regions */
2253 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2254 if (!rinfo->mmio_base) {
2255 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", pci_name(rinfo->pdev));
2256 ret = -EIO;
2257 goto err_release_pci;
2258 }
2259
2260 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2261
2262 /*
2263 * Check for errata
2264 */
2265 rinfo->errata = 0;
2266 if (rinfo->family == CHIP_FAMILY_R300 &&
2267 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2268 == CFG_ATI_REV_A11)
2269 rinfo->errata |= CHIP_ERRATA_R300_CG;
2270
2271 if (rinfo->family == CHIP_FAMILY_RV200 ||
2272 rinfo->family == CHIP_FAMILY_RS200)
2273 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2274
2275 if (rinfo->family == CHIP_FAMILY_RV100 ||
2276 rinfo->family == CHIP_FAMILY_RS100 ||
2277 rinfo->family == CHIP_FAMILY_RS200)
2278 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2279
2280#ifdef CONFIG_PPC_OF
2281 /* On PPC, we obtain the OF device-node pointer to the firmware
2282 * data for this chip
2283 */
2284 rinfo->of_node = pci_device_to_OF_node(pdev);
2285 if (rinfo->of_node == NULL)
2286 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2287 pci_name(rinfo->pdev));
2288
2289 /* On PPC, the firmware sets up a memory mapping that tends
2290 * to cause lockups when enabling the engine. We reconfigure
2291 * the card internal memory mappings properly
2292 */
2293 fixup_memory_mappings(rinfo);
2294#endif /* CONFIG_PPC_OF */
2295
2296 /* Get VRAM size and type */
2297 radeon_identify_vram(rinfo);
2298
2299 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2300
2301 do {
2302 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2303 rinfo->mapped_vram);
2304 } while ( rinfo->fb_base == 0 &&
2305 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2306
2307 if (rinfo->fb_base)
2308 memset_io(rinfo->fb_base, 0, rinfo->mapped_vram);
2309 else {
2310 printk (KERN_ERR "radeonfb (%s): cannot map FB\n", pci_name(rinfo->pdev));
2311 ret = -EIO;
2312 goto err_unmap_rom;
2313 }
2314
2315 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2316 rinfo->mapped_vram/1024);
2317
2318 /*
2319 * Map the BIOS ROM if any and retreive PLL parameters from
2320 * the BIOS. We skip that on mobility chips as the real panel
2321 * values we need aren't in the ROM but in the BIOS image in
2322 * memory. This is definitely not the best meacnism though,
2323 * we really need the arch code to tell us which is the "primary"
2324 * video adapter to use the memory image (or better, the arch
2325 * should provide us a copy of the BIOS image to shield us from
2326 * archs who would store that elsewhere and/or could initialize
2327 * more than one adapter during boot).
2328 */
2329 if (!rinfo->is_mobility)
2330 radeon_map_ROM(rinfo, pdev);
2331
2332 /*
2333 * On x86, the primary display on laptop may have it's BIOS
2334 * ROM elsewhere, try to locate it at the legacy memory hole.
2335 * We probably need to make sure this is the primary display,
2336 * but that is difficult without some arch support.
2337 */
2338#ifdef CONFIG_X86
2339 if (rinfo->bios_seg == NULL)
2340 radeon_find_mem_vbios(rinfo);
2341#endif
2342
2343 /* If both above failed, try the BIOS ROM again for mobility
2344 * chips
2345 */
2346 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2347 radeon_map_ROM(rinfo, pdev);
2348
2349 /* Get informations about the board's PLL */
2350 radeon_get_pllinfo(rinfo);
2351
2352#ifdef CONFIG_FB_RADEON_I2C
2353 /* Register I2C bus */
2354 radeon_create_i2c_busses(rinfo);
2355#endif
2356
2357 /* set all the vital stuff */
2358 radeon_set_fbinfo (rinfo);
2359
2360 /* Probe screen types */
2361 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2362
2363 /* Build mode list, check out panel native model */
2364 radeon_check_modes(rinfo, mode_option);
2365
2366 /* Register some sysfs stuff (should be done better) */
2367 if (rinfo->mon1_EDID)
2368 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2369 if (rinfo->mon2_EDID)
2370 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2371
2372 /* save current mode regs before we switch into the new one
2373 * so we can restore this upon __exit
2374 */
2375 radeon_save_state (rinfo, &rinfo->init_state);
2376 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2377
2378 /* Setup Power Management capabilities */
2379 if (default_dynclk < -1) {
2380 /* -2 is special: means ON on mobility chips and do not
2381 * change on others
2382 */
2383 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
2384 } else
2385 radeonfb_pm_init(rinfo, default_dynclk);
2386
2387 pci_set_drvdata(pdev, info);
2388
2389 /* Register with fbdev layer */
2390 ret = register_framebuffer(info);
2391 if (ret < 0) {
2392 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2393 pci_name(rinfo->pdev));
2394 goto err_unmap_fb;
2395 }
2396
2397#ifdef CONFIG_MTRR
2398 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2399 rinfo->video_ram,
2400 MTRR_TYPE_WRCOMB, 1);
2401#endif
2402
2403#ifdef CONFIG_PMAC_BACKLIGHT
2404 if (rinfo->mon1_type == MT_LCD) {
2405 register_backlight_controller(&radeon_backlight_controller,
2406 rinfo, "ati");
2407 register_backlight_controller(&radeon_backlight_controller,
2408 rinfo, "mnca");
2409 }
2410#endif
2411
2412 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2413
2414 if (rinfo->bios_seg)
2415 radeon_unmap_ROM(rinfo, pdev);
2416 RTRACE("radeonfb_pci_register END\n");
2417
2418 return 0;
2419err_unmap_fb:
2420 iounmap(rinfo->fb_base);
2421err_unmap_rom:
2422 kfree(rinfo->mon1_EDID);
2423 kfree(rinfo->mon2_EDID);
2424 if (rinfo->mon1_modedb)
2425 fb_destroy_modedb(rinfo->mon1_modedb);
2426 fb_dealloc_cmap(&info->cmap);
2427#ifdef CONFIG_FB_RADEON_I2C
2428 radeon_delete_i2c_busses(rinfo);
2429#endif
2430 if (rinfo->bios_seg)
2431 radeon_unmap_ROM(rinfo, pdev);
2432 iounmap(rinfo->mmio_base);
2433err_release_pci:
2434 pci_release_regions(pdev);
2435err_release_fb:
2436 framebuffer_release(info);
2437err_disable:
2438 pci_disable_device(pdev);
2439err_out:
2440 return ret;
2441}
2442
2443
2444
2445static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2446{
2447 struct fb_info *info = pci_get_drvdata(pdev);
2448 struct radeonfb_info *rinfo = info->par;
2449
2450 if (!rinfo)
2451 return;
2452
2453 radeonfb_pm_exit(rinfo);
2454
2455#if 0
2456 /* restore original state
2457 *
2458 * Doesn't quite work yet, I suspect if we come from a legacy
2459 * VGA mode (or worse, text mode), we need to do some VGA black
2460 * magic here that I know nothing about. --BenH
2461 */
2462 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2463 #endif
2464
2465 del_timer_sync(&rinfo->lvds_timer);
2466
2467#ifdef CONFIG_MTRR
2468 if (rinfo->mtrr_hdl >= 0)
2469 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2470#endif
2471
2472 unregister_framebuffer(info);
2473
2474 iounmap(rinfo->mmio_base);
2475 iounmap(rinfo->fb_base);
2476
2477 pci_release_regions(pdev);
2478
2479 kfree(rinfo->mon1_EDID);
2480 kfree(rinfo->mon2_EDID);
2481 if (rinfo->mon1_modedb)
2482 fb_destroy_modedb(rinfo->mon1_modedb);
2483#ifdef CONFIG_FB_RADEON_I2C
2484 radeon_delete_i2c_busses(rinfo);
2485#endif
2486 fb_dealloc_cmap(&info->cmap);
2487 framebuffer_release(info);
2488 pci_disable_device(pdev);
2489}
2490
2491
2492static struct pci_driver radeonfb_driver = {
2493 .name = "radeonfb",
2494 .id_table = radeonfb_pci_table,
2495 .probe = radeonfb_pci_register,
2496 .remove = __devexit_p(radeonfb_pci_unregister),
2497#ifdef CONFIG_PM
2498 .suspend = radeonfb_pci_suspend,
2499 .resume = radeonfb_pci_resume,
2500#endif /* CONFIG_PM */
2501};
2502
2503#ifndef MODULE
2504static int __init radeonfb_setup (char *options)
2505{
2506 char *this_opt;
2507
2508 if (!options || !*options)
2509 return 0;
2510
2511 while ((this_opt = strsep (&options, ",")) != NULL) {
2512 if (!*this_opt)
2513 continue;
2514
2515 if (!strncmp(this_opt, "noaccel", 7)) {
2516 noaccel = 1;
2517 } else if (!strncmp(this_opt, "mirror", 6)) {
2518 mirror = 1;
2519 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2520 force_dfp = 1;
2521 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2522 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2523#ifdef CONFIG_MTRR
2524 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2525 nomtrr = 1;
2526#endif
2527 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2528 nomodeset = 1;
2529 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2530 force_measure_pll = 1;
2531 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2532 ignore_edid = 1;
2533 } else
2534 mode_option = this_opt;
2535 }
2536 return 0;
2537}
2538#endif /* MODULE */
2539
2540static int __init radeonfb_init (void)
2541{
2542#ifndef MODULE
2543 char *option = NULL;
2544
2545 if (fb_get_options("radeonfb", &option))
2546 return -ENODEV;
2547 radeonfb_setup(option);
2548#endif
2549 return pci_register_driver (&radeonfb_driver);
2550}
2551
2552
2553static void __exit radeonfb_exit (void)
2554{
2555 pci_unregister_driver (&radeonfb_driver);
2556}
2557
2558module_init(radeonfb_init);
2559module_exit(radeonfb_exit);
2560
2561MODULE_AUTHOR("Ani Joshi");
2562MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2563MODULE_LICENSE("GPL");
2564module_param(noaccel, bool, 0);
2565module_param(default_dynclk, int, 0);
2566MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2567MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2568module_param(nomodeset, bool, 0);
2569MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2570module_param(mirror, bool, 0);
2571MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2572module_param(force_dfp, bool, 0);
2573MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2574module_param(ignore_edid, bool, 0);
2575MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2576module_param(monitor_layout, charp, 0);
2577MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2578module_param(force_measure_pll, bool, 0);
2579MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2580#ifdef CONFIG_MTRR
2581module_param(nomtrr, bool, 0);
2582MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2583#endif
2584module_param(panel_yres, int, 0);
2585MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2586module_param(mode_option, charp, 0);
2587MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 16:56:02 -0500