diff options
author | David Vrabel <david.vrabel@csr.com> | 2008-12-08 11:18:47 -0500 |
---|---|---|
committer | David Vrabel <david.vrabel@csr.com> | 2008-12-08 11:18:47 -0500 |
commit | c35fa3ea1ae8198bd65c2c6e59d9ebd68c115a59 (patch) | |
tree | 878768b69df25459b448aa890352342c4a3c6e2d /drivers/video/aty/radeon_accel.c | |
parent | dcc7461eef7341e84e2f7274f904ce01a43b2506 (diff) | |
parent | 218d11a8b071b23b76c484fd5f72a4fe3306801e (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-upstream
Diffstat (limited to 'drivers/video/aty/radeon_accel.c')
-rw-r--r-- | drivers/video/aty/radeon_accel.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c index 8718f7349d6b..a547e5d4c8bf 100644 --- a/drivers/video/aty/radeon_accel.c +++ b/drivers/video/aty/radeon_accel.c | |||
@@ -174,12 +174,12 @@ static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo, | |||
174 | const struct fb_image *image, | 174 | const struct fb_image *image, |
175 | u32 fg, u32 bg) | 175 | u32 fg, u32 bg) |
176 | { | 176 | { |
177 | unsigned int src_bytes, dwords; | 177 | unsigned int dwords; |
178 | u32 *bits; | 178 | u32 *bits; |
179 | 179 | ||
180 | radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, | 180 | radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, |
181 | rinfo->dp_gui_mc_base | | 181 | rinfo->dp_gui_mc_base | |
182 | GMC_BRUSH_NONE | | 182 | GMC_BRUSH_NONE | GMC_DST_CLIP_LEAVE | |
183 | GMC_SRC_DATATYPE_MONO_FG_BG | | 183 | GMC_SRC_DATATYPE_MONO_FG_BG | |
184 | ROP3_S | | 184 | ROP3_S | |
185 | GMC_BYTE_ORDER_MSB_TO_LSB | | 185 | GMC_BYTE_ORDER_MSB_TO_LSB | |
@@ -189,9 +189,6 @@ static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo, | |||
189 | radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg); | 189 | radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg); |
190 | radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg); | 190 | radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg); |
191 | 191 | ||
192 | radeon_fifo_wait(rinfo, 1); | ||
193 | OUTREG(DST_Y_X, (image->dy << 16) | image->dx); | ||
194 | |||
195 | /* Ensure the dst cache is flushed and the engine idle before | 192 | /* Ensure the dst cache is flushed and the engine idle before |
196 | * issuing the operation. | 193 | * issuing the operation. |
197 | * | 194 | * |
@@ -205,13 +202,19 @@ static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo, | |||
205 | 202 | ||
206 | /* X here pads width to a multiple of 32 and uses the clipper to | 203 | /* X here pads width to a multiple of 32 and uses the clipper to |
207 | * adjust the result. Is that really necessary ? Things seem to | 204 | * adjust the result. Is that really necessary ? Things seem to |
208 | * work ok for me without that and the doco doesn't seem to imply | 205 | * work ok for me without that and the doco doesn't seem to imply] |
209 | * there is such a restriction. | 206 | * there is such a restriction. |
210 | */ | 207 | */ |
211 | OUTREG(DST_WIDTH_HEIGHT, (image->width << 16) | image->height); | 208 | radeon_fifo_wait(rinfo, 4); |
209 | OUTREG(SC_TOP_LEFT, (image->dy << 16) | image->dx); | ||
210 | OUTREG(SC_BOTTOM_RIGHT, ((image->dy + image->height) << 16) | | ||
211 | (image->dx + image->width)); | ||
212 | OUTREG(DST_Y_X, (image->dy << 16) | image->dx); | ||
213 | |||
214 | OUTREG(DST_HEIGHT_WIDTH, (image->height << 16) | ((image->width + 31) & ~31)); | ||
212 | 215 | ||
213 | src_bytes = (((image->width * image->depth) + 7) / 8) * image->height; | 216 | dwords = (image->width + 31) >> 5; |
214 | dwords = (src_bytes + 3) / 4; | 217 | dwords *= image->height; |
215 | bits = (u32*)(image->data); | 218 | bits = (u32*)(image->data); |
216 | 219 | ||
217 | while(dwords >= 8) { | 220 | while(dwords >= 8) { |