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authorVille Syrj�l� <syrjala@sci.fi>2006-01-09 23:53:31 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-10 11:01:49 -0500
commit0c23b67c49e239e40fad3947483815637e5f1790 (patch)
tree1e3b29be3cb4680f1eb07a02e0407c40a3d15c3d /drivers/video/aty/atyfb_base.c
parent69b569f5c0b47c33fec4e35921368e43cbe089a5 (diff)
[PATCH] atyfb: VT/GT cleanup
Clean up VT and GT chip descriptions. All B revision VT chips are called 264VT3. Verified from pictures of the chips as the specs are a bit unlear in this. GT revision B1 is Rage II, B2 is Rage II+. Specs and chip pictures seem to agree. VT revision A4 is 264VT2. Revision A3 is probably a plain 264VT. Signed-off-by: Ville Syrjälä <syrjala@sci.fi> Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/video/aty/atyfb_base.c')
-rw-r--r--drivers/video/aty/atyfb_base.c62
1 files changed, 41 insertions, 21 deletions
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c
index bfb583132efe..28d17b4b6e13 100644
--- a/drivers/video/aty/atyfb_base.c
+++ b/drivers/video/aty/atyfb_base.c
@@ -380,11 +380,12 @@ static struct {
380#ifdef CONFIG_FB_ATY_CT 380#ifdef CONFIG_FB_ATY_CT
381 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT }, 381 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
382 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET }, 382 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
383 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT }, 383
384 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
384 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT }, 385 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
385 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */ 386
386 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, 100, ATI_CHIP_264GTB }, 387 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
387 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 }, 388 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
388 389
389 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT }, 390 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
390 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */ 391 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
@@ -460,44 +461,63 @@ static int __devinit correct_chipset(struct atyfb_par *par)
460#endif 461#endif
461#ifdef CONFIG_FB_ATY_CT 462#ifdef CONFIG_FB_ATY_CT
462 case PCI_CHIP_MACH64VT: 463 case PCI_CHIP_MACH64VT:
463 rev &= 0xc7; 464 switch (rev & 0x07) {
464 if(rev == 0x00) { 465 case 0x00:
465 name = "ATI264VTA3 (Mach64 VT)"; 466 switch (rev & 0xc0) {
466 par->pll_limits.pll_max = 170; 467 case 0x00:
467 par->pll_limits.mclk = 67; 468 name = "ATI264VT (A3) (Mach64 VT)";
468 par->pll_limits.xclk = 67; 469 par->pll_limits.pll_max = 170;
469 par->pll_limits.ecp_max = 80; 470 par->pll_limits.mclk = 67;
470 par->features = ATI_CHIP_264VT; 471 par->pll_limits.xclk = 67;
471 } else if(rev == 0x40) { 472 par->pll_limits.ecp_max = 80;
472 name = "ATI264VTA4 (Mach64 VT)"; 473 par->features = ATI_CHIP_264VT;
474 break;
475 case 0x40:
476 name = "ATI264VT2 (A4) (Mach64 VT)";
477 par->pll_limits.pll_max = 200;
478 par->pll_limits.mclk = 67;
479 par->pll_limits.xclk = 67;
480 par->pll_limits.ecp_max = 80;
481 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
482 break;
483 }
484 break;
485 case 0x01:
486 name = "ATI264VT3 (B1) (Mach64 VT)";
473 par->pll_limits.pll_max = 200; 487 par->pll_limits.pll_max = 200;
474 par->pll_limits.mclk = 67; 488 par->pll_limits.mclk = 67;
475 par->pll_limits.xclk = 67; 489 par->pll_limits.xclk = 67;
476 par->pll_limits.ecp_max = 80; 490 par->pll_limits.ecp_max = 80;
477 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV; 491 par->features = ATI_CHIP_264VTB;
478 } else { 492 break;
479 name = "ATI264VTB (Mach64 VT)"; 493 case 0x02:
494 name = "ATI264VT3 (B2) (Mach64 VT)";
480 par->pll_limits.pll_max = 200; 495 par->pll_limits.pll_max = 200;
481 par->pll_limits.mclk = 67; 496 par->pll_limits.mclk = 67;
482 par->pll_limits.xclk = 67; 497 par->pll_limits.xclk = 67;
483 par->pll_limits.ecp_max = 80; 498 par->pll_limits.ecp_max = 80;
484 par->features = ATI_CHIP_264VTB; 499 par->features = ATI_CHIP_264VT3;
500 break;
485 } 501 }
486 break; 502 break;
487 case PCI_CHIP_MACH64GT: 503 case PCI_CHIP_MACH64GT:
488 rev &= 0x07; 504 switch (rev & 0x07) {
489 if(rev == 0x01) { 505 case 0x01:
506 name = "3D RAGE II (Mach64 GT)";
490 par->pll_limits.pll_max = 170; 507 par->pll_limits.pll_max = 170;
491 par->pll_limits.mclk = 67; 508 par->pll_limits.mclk = 67;
492 par->pll_limits.xclk = 67; 509 par->pll_limits.xclk = 67;
493 par->pll_limits.ecp_max = 80; 510 par->pll_limits.ecp_max = 80;
494 par->features = ATI_CHIP_264GTB; 511 par->features = ATI_CHIP_264GTB;
495 } else if(rev == 0x02) { 512 break;
513 case 0x02:
514 name = "3D RAGE II+ (Mach64 GT)";
496 par->pll_limits.pll_max = 200; 515 par->pll_limits.pll_max = 200;
497 par->pll_limits.mclk = 67; 516 par->pll_limits.mclk = 67;
498 par->pll_limits.xclk = 67; 517 par->pll_limits.xclk = 67;
499 par->pll_limits.ecp_max = 100; 518 par->pll_limits.ecp_max = 100;
500 par->features = ATI_CHIP_264GTB; 519 par->features = ATI_CHIP_264GTB;
520 break;
501 } 521 }
502 break; 522 break;
503#endif 523#endif