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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/amba-clcd.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/video/amba-clcd.c')
-rw-r--r--drivers/video/amba-clcd.c533
1 files changed, 533 insertions, 0 deletions
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
new file mode 100644
index 000000000000..acdba0c67fb8
--- /dev/null
+++ b/drivers/video/amba-clcd.c
@@ -0,0 +1,533 @@
1/*
2 * linux/drivers/video/amba-clcd.c
3 *
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 *
11 * ARM PrimeCell PL110 Color LCD Controller
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/mm.h>
20#include <linux/fb.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/list.h>
24
25#include <asm/hardware/amba.h>
26#include <asm/hardware/clock.h>
27
28#include <asm/hardware/amba_clcd.h>
29
30#define to_clcd(info) container_of(info, struct clcd_fb, fb)
31
32/* This is limited to 16 characters when displayed by X startup */
33static const char *clcd_name = "CLCD FB";
34
35/*
36 * Unfortunately, the enable/disable functions may be called either from
37 * process or IRQ context, and we _need_ to delay. This is _not_ good.
38 */
39static inline void clcdfb_sleep(unsigned int ms)
40{
41 if (in_atomic()) {
42 mdelay(ms);
43 } else {
44 msleep(ms);
45 }
46}
47
48static inline void clcdfb_set_start(struct clcd_fb *fb)
49{
50 unsigned long ustart = fb->fb.fix.smem_start;
51 unsigned long lstart;
52
53 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
54 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
55
56 writel(ustart, fb->regs + CLCD_UBAS);
57 writel(lstart, fb->regs + CLCD_LBAS);
58}
59
60static void clcdfb_disable(struct clcd_fb *fb)
61{
62 u32 val;
63
64 if (fb->board->disable)
65 fb->board->disable(fb);
66
67 val = readl(fb->regs + CLCD_CNTL);
68 if (val & CNTL_LCDPWR) {
69 val &= ~CNTL_LCDPWR;
70 writel(val, fb->regs + CLCD_CNTL);
71
72 clcdfb_sleep(20);
73 }
74 if (val & CNTL_LCDEN) {
75 val &= ~CNTL_LCDEN;
76 writel(val, fb->regs + CLCD_CNTL);
77 }
78
79 /*
80 * Disable CLCD clock source.
81 */
82 clk_disable(fb->clk);
83}
84
85static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
86{
87 /*
88 * Enable the CLCD clock source.
89 */
90 clk_enable(fb->clk);
91
92 /*
93 * Bring up by first enabling..
94 */
95 cntl |= CNTL_LCDEN;
96 writel(cntl, fb->regs + CLCD_CNTL);
97
98 clcdfb_sleep(20);
99
100 /*
101 * and now apply power.
102 */
103 cntl |= CNTL_LCDPWR;
104 writel(cntl, fb->regs + CLCD_CNTL);
105
106 /*
107 * finally, enable the interface.
108 */
109 if (fb->board->enable)
110 fb->board->enable(fb);
111}
112
113static int
114clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
115{
116 int ret = 0;
117
118 memset(&var->transp, 0, sizeof(var->transp));
119 memset(&var->red, 0, sizeof(var->red));
120 memset(&var->green, 0, sizeof(var->green));
121 memset(&var->blue, 0, sizeof(var->blue));
122
123 switch (var->bits_per_pixel) {
124 case 1:
125 case 2:
126 case 4:
127 case 8:
128 var->red.length = 8;
129 var->red.offset = 0;
130 var->green.length = 8;
131 var->green.offset = 0;
132 var->blue.length = 8;
133 var->blue.offset = 0;
134 break;
135 case 16:
136 var->red.length = 5;
137 var->green.length = 5;
138 var->blue.length = 5;
139 if (fb->panel->cntl & CNTL_BGR) {
140 var->red.offset = 10;
141 var->green.offset = 5;
142 var->blue.offset = 0;
143 } else {
144 var->red.offset = 0;
145 var->green.offset = 5;
146 var->blue.offset = 10;
147 }
148 break;
149 case 24:
150 if (fb->panel->cntl & CNTL_LCDTFT) {
151 var->red.length = 8;
152 var->green.length = 8;
153 var->blue.length = 8;
154
155 if (fb->panel->cntl & CNTL_BGR) {
156 var->red.offset = 16;
157 var->green.offset = 8;
158 var->blue.offset = 0;
159 } else {
160 var->red.offset = 0;
161 var->green.offset = 8;
162 var->blue.offset = 16;
163 }
164 break;
165 }
166 default:
167 ret = -EINVAL;
168 break;
169 }
170
171 return ret;
172}
173
174static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
175{
176 struct clcd_fb *fb = to_clcd(info);
177 int ret = -EINVAL;
178
179 if (fb->board->check)
180 ret = fb->board->check(fb, var);
181 if (ret == 0)
182 ret = clcdfb_set_bitfields(fb, var);
183
184 return ret;
185}
186
187static int clcdfb_set_par(struct fb_info *info)
188{
189 struct clcd_fb *fb = to_clcd(info);
190 struct clcd_regs regs;
191
192 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
193 fb->fb.var.bits_per_pixel / 8;
194
195 if (fb->fb.var.bits_per_pixel <= 8)
196 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
197 else
198 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
199
200 fb->board->decode(fb, &regs);
201
202 clcdfb_disable(fb);
203
204 writel(regs.tim0, fb->regs + CLCD_TIM0);
205 writel(regs.tim1, fb->regs + CLCD_TIM1);
206 writel(regs.tim2, fb->regs + CLCD_TIM2);
207 writel(regs.tim3, fb->regs + CLCD_TIM3);
208
209 clcdfb_set_start(fb);
210
211 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
212
213 fb->clcd_cntl = regs.cntl;
214
215 clcdfb_enable(fb, regs.cntl);
216
217#ifdef DEBUG
218 printk(KERN_INFO "CLCD: Registers set to\n"
219 KERN_INFO " %08x %08x %08x %08x\n"
220 KERN_INFO " %08x %08x %08x %08x\n",
221 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
222 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
223 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
224 readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL));
225#endif
226
227 return 0;
228}
229
230static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
231{
232 unsigned int mask = (1 << bf->length) - 1;
233
234 return (val >> (16 - bf->length) & mask) << bf->offset;
235}
236
237/*
238 * Set a single color register. The values supplied have a 16 bit
239 * magnitude. Return != 0 for invalid regno.
240 */
241static int
242clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
243 unsigned int blue, unsigned int transp, struct fb_info *info)
244{
245 struct clcd_fb *fb = to_clcd(info);
246
247 if (regno < 16)
248 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
249 convert_bitfield(blue, &fb->fb.var.blue) |
250 convert_bitfield(green, &fb->fb.var.green) |
251 convert_bitfield(red, &fb->fb.var.red);
252
253 if (fb->fb.var.bits_per_pixel == 8 && regno < 256) {
254 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
255 u32 val, mask, newval;
256
257 newval = (red >> 11) & 0x001f;
258 newval |= (green >> 6) & 0x03e0;
259 newval |= (blue >> 1) & 0x7c00;
260
261 /*
262 * 3.2.11: if we're configured for big endian
263 * byte order, the palette entries are swapped.
264 */
265 if (fb->clcd_cntl & CNTL_BEBO)
266 regno ^= 1;
267
268 if (regno & 1) {
269 newval <<= 16;
270 mask = 0x0000ffff;
271 } else {
272 mask = 0xffff0000;
273 }
274
275 val = readl(fb->regs + hw_reg) & mask;
276 writel(val | newval, fb->regs + hw_reg);
277 }
278
279 return regno > 255;
280}
281
282/*
283 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
284 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
285 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
286 * to e.g. a video mode which doesn't support it. Implements VESA suspend
287 * and powerdown modes on hardware that supports disabling hsync/vsync:
288 * blank_mode == 2: suspend vsync
289 * blank_mode == 3: suspend hsync
290 * blank_mode == 4: powerdown
291 */
292static int clcdfb_blank(int blank_mode, struct fb_info *info)
293{
294 struct clcd_fb *fb = to_clcd(info);
295
296 if (blank_mode != 0) {
297 clcdfb_disable(fb);
298 } else {
299 clcdfb_enable(fb, fb->clcd_cntl);
300 }
301 return 0;
302}
303
304static int clcdfb_mmap(struct fb_info *info, struct file *file,
305 struct vm_area_struct *vma)
306{
307 struct clcd_fb *fb = to_clcd(info);
308 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
309 int ret = -EINVAL;
310
311 len = info->fix.smem_len;
312
313 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
314 fb->board->mmap)
315 ret = fb->board->mmap(fb, vma);
316
317 return ret;
318}
319
320static struct fb_ops clcdfb_ops = {
321 .owner = THIS_MODULE,
322 .fb_check_var = clcdfb_check_var,
323 .fb_set_par = clcdfb_set_par,
324 .fb_setcolreg = clcdfb_setcolreg,
325 .fb_blank = clcdfb_blank,
326 .fb_fillrect = cfb_fillrect,
327 .fb_copyarea = cfb_copyarea,
328 .fb_imageblit = cfb_imageblit,
329 .fb_cursor = soft_cursor,
330 .fb_mmap = clcdfb_mmap,
331};
332
333static int clcdfb_register(struct clcd_fb *fb)
334{
335 int ret;
336
337 fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
338 if (IS_ERR(fb->clk)) {
339 ret = PTR_ERR(fb->clk);
340 goto out;
341 }
342
343 ret = clk_use(fb->clk);
344 if (ret)
345 goto free_clk;
346
347 fb->fb.fix.mmio_start = fb->dev->res.start;
348 fb->fb.fix.mmio_len = SZ_4K;
349
350 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
351 if (!fb->regs) {
352 printk(KERN_ERR "CLCD: unable to remap registers\n");
353 ret = -ENOMEM;
354 goto unuse_clk;
355 }
356
357 fb->fb.fbops = &clcdfb_ops;
358 fb->fb.flags = FBINFO_FLAG_DEFAULT;
359 fb->fb.pseudo_palette = fb->cmap;
360
361 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
362 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
363 fb->fb.fix.type_aux = 0;
364 fb->fb.fix.xpanstep = 0;
365 fb->fb.fix.ypanstep = 0;
366 fb->fb.fix.ywrapstep = 0;
367 fb->fb.fix.accel = FB_ACCEL_NONE;
368
369 fb->fb.var.xres = fb->panel->mode.xres;
370 fb->fb.var.yres = fb->panel->mode.yres;
371 fb->fb.var.xres_virtual = fb->panel->mode.xres;
372 fb->fb.var.yres_virtual = fb->panel->mode.yres;
373 fb->fb.var.bits_per_pixel = fb->panel->bpp;
374 fb->fb.var.grayscale = fb->panel->grayscale;
375 fb->fb.var.pixclock = fb->panel->mode.pixclock;
376 fb->fb.var.left_margin = fb->panel->mode.left_margin;
377 fb->fb.var.right_margin = fb->panel->mode.right_margin;
378 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
379 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
380 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
381 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
382 fb->fb.var.sync = fb->panel->mode.sync;
383 fb->fb.var.vmode = fb->panel->mode.vmode;
384 fb->fb.var.activate = FB_ACTIVATE_NOW;
385 fb->fb.var.nonstd = 0;
386 fb->fb.var.height = fb->panel->height;
387 fb->fb.var.width = fb->panel->width;
388 fb->fb.var.accel_flags = 0;
389
390 fb->fb.monspecs.hfmin = 0;
391 fb->fb.monspecs.hfmax = 100000;
392 fb->fb.monspecs.vfmin = 0;
393 fb->fb.monspecs.vfmax = 400;
394 fb->fb.monspecs.dclkmin = 1000000;
395 fb->fb.monspecs.dclkmax = 100000000;
396
397 /*
398 * Make sure that the bitfields are set appropriately.
399 */
400 clcdfb_set_bitfields(fb, &fb->fb.var);
401
402 /*
403 * Allocate colourmap.
404 */
405 fb_alloc_cmap(&fb->fb.cmap, 256, 0);
406
407 /*
408 * Ensure interrupts are disabled.
409 */
410 writel(0, fb->regs + CLCD_IENB);
411
412 fb_set_var(&fb->fb, &fb->fb.var);
413
414 printk(KERN_INFO "CLCD: %s hardware, %s display\n",
415 fb->board->name, fb->panel->mode.name);
416
417 ret = register_framebuffer(&fb->fb);
418 if (ret == 0)
419 goto out;
420
421 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
422
423 iounmap(fb->regs);
424 unuse_clk:
425 clk_unuse(fb->clk);
426 free_clk:
427 clk_put(fb->clk);
428 out:
429 return ret;
430}
431
432static int clcdfb_probe(struct amba_device *dev, void *id)
433{
434 struct clcd_board *board = dev->dev.platform_data;
435 struct clcd_fb *fb;
436 int ret;
437
438 if (!board)
439 return -EINVAL;
440
441 ret = amba_request_regions(dev, NULL);
442 if (ret) {
443 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
444 goto out;
445 }
446
447 fb = (struct clcd_fb *) kmalloc(sizeof(struct clcd_fb), GFP_KERNEL);
448 if (!fb) {
449 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
450 ret = -ENOMEM;
451 goto free_region;
452 }
453 memset(fb, 0, sizeof(struct clcd_fb));
454
455 fb->dev = dev;
456 fb->board = board;
457
458 ret = fb->board->setup(fb);
459 if (ret)
460 goto free_fb;
461
462 ret = clcdfb_register(fb);
463 if (ret == 0) {
464 amba_set_drvdata(dev, fb);
465 goto out;
466 }
467
468 fb->board->remove(fb);
469 free_fb:
470 kfree(fb);
471 free_region:
472 amba_release_regions(dev);
473 out:
474 return ret;
475}
476
477static int clcdfb_remove(struct amba_device *dev)
478{
479 struct clcd_fb *fb = amba_get_drvdata(dev);
480
481 amba_set_drvdata(dev, NULL);
482
483 clcdfb_disable(fb);
484 unregister_framebuffer(&fb->fb);
485 iounmap(fb->regs);
486 clk_unuse(fb->clk);
487 clk_put(fb->clk);
488
489 fb->board->remove(fb);
490
491 kfree(fb);
492
493 amba_release_regions(dev);
494
495 return 0;
496}
497
498static struct amba_id clcdfb_id_table[] = {
499 {
500 .id = 0x00041110,
501 .mask = 0x000fffff,
502 },
503 { 0, 0 },
504};
505
506static struct amba_driver clcd_driver = {
507 .drv = {
508 .name = "clcd-pl110",
509 },
510 .probe = clcdfb_probe,
511 .remove = clcdfb_remove,
512 .id_table = clcdfb_id_table,
513};
514
515int __init amba_clcdfb_init(void)
516{
517 if (fb_get_options("ambafb", NULL))
518 return -ENODEV;
519
520 return amba_driver_register(&clcd_driver);
521}
522
523module_init(amba_clcdfb_init);
524
525static void __exit amba_clcdfb_exit(void)
526{
527 amba_driver_unregister(&clcd_driver);
528}
529
530module_exit(amba_clcdfb_exit);
531
532MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
533MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 00:12:43 -0500