diff options
author | Felipe Balbi <felipe.balbi@nokia.com> | 2008-09-11 04:53:24 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2008-10-17 17:40:59 -0400 |
commit | 458e6a511f9dc91e5af5e64740b0a5c9650a25fb (patch) | |
tree | 003551075b14ad2670c183898d28c4a9544d01aa /drivers/usb | |
parent | c767c1c6f1febbd1351cc152bba6e37889322d17 (diff) |
usb: musb: general cleanup to musbhsdma.c
Basically getting rid of CaMeLcAsE, but also adding
missing lines and spaces.
Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb')
-rw-r--r-- | drivers/usb/musb/musbhsdma.c | 306 |
1 files changed, 155 insertions, 151 deletions
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index 9ba8fb7fcd24..8c734ef2c1ed 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c | |||
@@ -45,8 +45,8 @@ | |||
45 | #define MUSB_HSDMA_ADDRESS 0x8 | 45 | #define MUSB_HSDMA_ADDRESS 0x8 |
46 | #define MUSB_HSDMA_COUNT 0xc | 46 | #define MUSB_HSDMA_COUNT 0xc |
47 | 47 | ||
48 | #define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \ | 48 | #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \ |
49 | (MUSB_HSDMA_BASE + (_bChannel << 4) + _offset) | 49 | (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset) |
50 | 50 | ||
51 | /* control register (16-bit): */ | 51 | /* control register (16-bit): */ |
52 | #define MUSB_HSDMA_ENABLE_SHIFT 0 | 52 | #define MUSB_HSDMA_ENABLE_SHIFT 0 |
@@ -67,23 +67,23 @@ | |||
67 | struct musb_dma_controller; | 67 | struct musb_dma_controller; |
68 | 68 | ||
69 | struct musb_dma_channel { | 69 | struct musb_dma_channel { |
70 | struct dma_channel Channel; | 70 | struct dma_channel channel; |
71 | struct musb_dma_controller *controller; | 71 | struct musb_dma_controller *controller; |
72 | u32 dwStartAddress; | 72 | u32 start_addr; |
73 | u32 len; | 73 | u32 len; |
74 | u16 wMaxPacketSize; | 74 | u16 max_packet_sz; |
75 | u8 bIndex; | 75 | u8 idx; |
76 | u8 epnum; | 76 | u8 epnum; |
77 | u8 transmit; | 77 | u8 transmit; |
78 | }; | 78 | }; |
79 | 79 | ||
80 | struct musb_dma_controller { | 80 | struct musb_dma_controller { |
81 | struct dma_controller Controller; | 81 | struct dma_controller controller; |
82 | struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS]; | 82 | struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS]; |
83 | void *pDmaPrivate; | 83 | void *private_data; |
84 | void __iomem *pCoreBase; | 84 | void __iomem *base; |
85 | u8 bChannelCount; | 85 | u8 channel_count; |
86 | u8 bmUsedChannels; | 86 | u8 used_channels; |
87 | u8 irq; | 87 | u8 irq; |
88 | }; | 88 | }; |
89 | 89 | ||
@@ -93,91 +93,91 @@ static int dma_controller_start(struct dma_controller *c) | |||
93 | return 0; | 93 | return 0; |
94 | } | 94 | } |
95 | 95 | ||
96 | static void dma_channel_release(struct dma_channel *pChannel); | 96 | static void dma_channel_release(struct dma_channel *channel); |
97 | 97 | ||
98 | static int dma_controller_stop(struct dma_controller *c) | 98 | static int dma_controller_stop(struct dma_controller *c) |
99 | { | 99 | { |
100 | struct musb_dma_controller *controller = | 100 | struct musb_dma_controller *controller = container_of(c, |
101 | container_of(c, struct musb_dma_controller, Controller); | 101 | struct musb_dma_controller, controller); |
102 | struct musb *musb = (struct musb *) controller->pDmaPrivate; | 102 | struct musb *musb = controller->private_data; |
103 | struct dma_channel *pChannel; | 103 | struct dma_channel *channel; |
104 | u8 bBit; | 104 | u8 bit; |
105 | 105 | ||
106 | if (controller->bmUsedChannels != 0) { | 106 | if (controller->used_channels != 0) { |
107 | dev_err(musb->controller, | 107 | dev_err(musb->controller, |
108 | "Stopping DMA controller while channel active\n"); | 108 | "Stopping DMA controller while channel active\n"); |
109 | 109 | ||
110 | for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) { | 110 | for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { |
111 | if (controller->bmUsedChannels & (1 << bBit)) { | 111 | if (controller->used_channels & (1 << bit)) { |
112 | pChannel = &controller->aChannel[bBit].Channel; | 112 | channel = &controller->channel[bit].channel; |
113 | dma_channel_release(pChannel); | 113 | dma_channel_release(channel); |
114 | 114 | ||
115 | if (!controller->bmUsedChannels) | 115 | if (!controller->used_channels) |
116 | break; | 116 | break; |
117 | } | 117 | } |
118 | } | 118 | } |
119 | } | 119 | } |
120 | |||
120 | return 0; | 121 | return 0; |
121 | } | 122 | } |
122 | 123 | ||
123 | static struct dma_channel *dma_channel_allocate(struct dma_controller *c, | 124 | static struct dma_channel *dma_channel_allocate(struct dma_controller *c, |
124 | struct musb_hw_ep *hw_ep, u8 transmit) | 125 | struct musb_hw_ep *hw_ep, u8 transmit) |
125 | { | 126 | { |
126 | u8 bBit; | 127 | struct musb_dma_controller *controller = container_of(c, |
127 | struct dma_channel *pChannel = NULL; | 128 | struct musb_dma_controller, controller); |
128 | struct musb_dma_channel *pImplChannel = NULL; | 129 | struct musb_dma_channel *musb_channel = NULL; |
129 | struct musb_dma_controller *controller = | 130 | struct dma_channel *channel = NULL; |
130 | container_of(c, struct musb_dma_controller, Controller); | 131 | u8 bit; |
131 | 132 | ||
132 | for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) { | 133 | for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { |
133 | if (!(controller->bmUsedChannels & (1 << bBit))) { | 134 | if (!(controller->used_channels & (1 << bit))) { |
134 | controller->bmUsedChannels |= (1 << bBit); | 135 | controller->used_channels |= (1 << bit); |
135 | pImplChannel = &(controller->aChannel[bBit]); | 136 | musb_channel = &(controller->channel[bit]); |
136 | pImplChannel->controller = controller; | 137 | musb_channel->controller = controller; |
137 | pImplChannel->bIndex = bBit; | 138 | musb_channel->idx = bit; |
138 | pImplChannel->epnum = hw_ep->epnum; | 139 | musb_channel->epnum = hw_ep->epnum; |
139 | pImplChannel->transmit = transmit; | 140 | musb_channel->transmit = transmit; |
140 | pChannel = &(pImplChannel->Channel); | 141 | channel = &(musb_channel->channel); |
141 | pChannel->private_data = pImplChannel; | 142 | channel->private_data = musb_channel; |
142 | pChannel->status = MUSB_DMA_STATUS_FREE; | 143 | channel->status = MUSB_DMA_STATUS_FREE; |
143 | pChannel->max_len = 0x10000; | 144 | channel->max_len = 0x10000; |
144 | /* Tx => mode 1; Rx => mode 0 */ | 145 | /* Tx => mode 1; Rx => mode 0 */ |
145 | pChannel->desired_mode = transmit; | 146 | channel->desired_mode = transmit; |
146 | pChannel->actual_len = 0; | 147 | channel->actual_len = 0; |
147 | break; | 148 | break; |
148 | } | 149 | } |
149 | } | 150 | } |
150 | return pChannel; | 151 | |
152 | return channel; | ||
151 | } | 153 | } |
152 | 154 | ||
153 | static void dma_channel_release(struct dma_channel *pChannel) | 155 | static void dma_channel_release(struct dma_channel *channel) |
154 | { | 156 | { |
155 | struct musb_dma_channel *pImplChannel = | 157 | struct musb_dma_channel *musb_channel = channel->private_data; |
156 | (struct musb_dma_channel *) pChannel->private_data; | ||
157 | 158 | ||
158 | pChannel->actual_len = 0; | 159 | channel->actual_len = 0; |
159 | pImplChannel->dwStartAddress = 0; | 160 | musb_channel->start_addr = 0; |
160 | pImplChannel->len = 0; | 161 | musb_channel->len = 0; |
161 | 162 | ||
162 | pImplChannel->controller->bmUsedChannels &= | 163 | musb_channel->controller->used_channels &= |
163 | ~(1 << pImplChannel->bIndex); | 164 | ~(1 << musb_channel->idx); |
164 | 165 | ||
165 | pChannel->status = MUSB_DMA_STATUS_UNKNOWN; | 166 | channel->status = MUSB_DMA_STATUS_UNKNOWN; |
166 | } | 167 | } |
167 | 168 | ||
168 | static void configure_channel(struct dma_channel *pChannel, | 169 | static void configure_channel(struct dma_channel *channel, |
169 | u16 packet_sz, u8 mode, | 170 | u16 packet_sz, u8 mode, |
170 | dma_addr_t dma_addr, u32 len) | 171 | dma_addr_t dma_addr, u32 len) |
171 | { | 172 | { |
172 | struct musb_dma_channel *pImplChannel = | 173 | struct musb_dma_channel *musb_channel = channel->private_data; |
173 | (struct musb_dma_channel *) pChannel->private_data; | 174 | struct musb_dma_controller *controller = musb_channel->controller; |
174 | struct musb_dma_controller *controller = pImplChannel->controller; | 175 | void __iomem *mbase = controller->base; |
175 | void __iomem *mbase = controller->pCoreBase; | 176 | u8 bchannel = musb_channel->idx; |
176 | u8 bChannel = pImplChannel->bIndex; | ||
177 | u16 csr = 0; | 177 | u16 csr = 0; |
178 | 178 | ||
179 | DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", | 179 | DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", |
180 | pChannel, packet_sz, dma_addr, len, mode); | 180 | channel, packet_sz, dma_addr, len, mode); |
181 | 181 | ||
182 | if (mode) { | 182 | if (mode) { |
183 | csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; | 183 | csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; |
@@ -195,180 +195,183 @@ static void configure_channel(struct dma_channel *pChannel, | |||
195 | } | 195 | } |
196 | } | 196 | } |
197 | 197 | ||
198 | csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) | 198 | csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) |
199 | | (1 << MUSB_HSDMA_ENABLE_SHIFT) | 199 | | (1 << MUSB_HSDMA_ENABLE_SHIFT) |
200 | | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) | 200 | | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) |
201 | | (pImplChannel->transmit | 201 | | (musb_channel->transmit |
202 | ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) | 202 | ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) |
203 | : 0); | 203 | : 0); |
204 | 204 | ||
205 | /* address/count */ | 205 | /* address/count */ |
206 | musb_writel(mbase, | 206 | musb_writel(mbase, |
207 | MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), | 207 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), |
208 | dma_addr); | 208 | dma_addr); |
209 | musb_writel(mbase, | 209 | musb_writel(mbase, |
210 | MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), | 210 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), |
211 | len); | 211 | len); |
212 | 212 | ||
213 | /* control (this should start things) */ | 213 | /* control (this should start things) */ |
214 | musb_writew(mbase, | 214 | musb_writew(mbase, |
215 | MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), | 215 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), |
216 | csr); | 216 | csr); |
217 | } | 217 | } |
218 | 218 | ||
219 | static int dma_channel_program(struct dma_channel *pChannel, | 219 | static int dma_channel_program(struct dma_channel *channel, |
220 | u16 packet_sz, u8 mode, | 220 | u16 packet_sz, u8 mode, |
221 | dma_addr_t dma_addr, u32 len) | 221 | dma_addr_t dma_addr, u32 len) |
222 | { | 222 | { |
223 | struct musb_dma_channel *pImplChannel = | 223 | struct musb_dma_channel *musb_channel = channel->private_data; |
224 | (struct musb_dma_channel *) pChannel->private_data; | ||
225 | 224 | ||
226 | DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", | 225 | DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", |
227 | pImplChannel->epnum, | 226 | musb_channel->epnum, |
228 | pImplChannel->transmit ? "Tx" : "Rx", | 227 | musb_channel->transmit ? "Tx" : "Rx", |
229 | packet_sz, dma_addr, len, mode); | 228 | packet_sz, dma_addr, len, mode); |
230 | 229 | ||
231 | BUG_ON(pChannel->status == MUSB_DMA_STATUS_UNKNOWN || | 230 | BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || |
232 | pChannel->status == MUSB_DMA_STATUS_BUSY); | 231 | channel->status == MUSB_DMA_STATUS_BUSY); |
233 | 232 | ||
234 | pChannel->actual_len = 0; | 233 | channel->actual_len = 0; |
235 | pImplChannel->dwStartAddress = dma_addr; | 234 | musb_channel->start_addr = dma_addr; |
236 | pImplChannel->len = len; | 235 | musb_channel->len = len; |
237 | pImplChannel->wMaxPacketSize = packet_sz; | 236 | musb_channel->max_packet_sz = packet_sz; |
238 | pChannel->status = MUSB_DMA_STATUS_BUSY; | 237 | channel->status = MUSB_DMA_STATUS_BUSY; |
239 | 238 | ||
240 | if ((mode == 1) && (len >= packet_sz)) | 239 | if ((mode == 1) && (len >= packet_sz)) |
241 | configure_channel(pChannel, packet_sz, 1, dma_addr, len); | 240 | configure_channel(channel, packet_sz, 1, dma_addr, len); |
242 | else | 241 | else |
243 | configure_channel(pChannel, packet_sz, 0, dma_addr, len); | 242 | configure_channel(channel, packet_sz, 0, dma_addr, len); |
244 | 243 | ||
245 | return true; | 244 | return true; |
246 | } | 245 | } |
247 | 246 | ||
248 | static int dma_channel_abort(struct dma_channel *pChannel) | 247 | static int dma_channel_abort(struct dma_channel *channel) |
249 | { | 248 | { |
250 | struct musb_dma_channel *pImplChannel = | 249 | struct musb_dma_channel *musb_channel = channel->private_data; |
251 | (struct musb_dma_channel *) pChannel->private_data; | 250 | void __iomem *mbase = musb_channel->controller->base; |
252 | u8 bChannel = pImplChannel->bIndex; | 251 | |
253 | void __iomem *mbase = pImplChannel->controller->pCoreBase; | 252 | u8 bchannel = musb_channel->idx; |
254 | u16 csr; | 253 | u16 csr; |
255 | 254 | ||
256 | if (pChannel->status == MUSB_DMA_STATUS_BUSY) { | 255 | if (channel->status == MUSB_DMA_STATUS_BUSY) { |
257 | if (pImplChannel->transmit) { | 256 | if (musb_channel->transmit) { |
258 | 257 | ||
259 | csr = musb_readw(mbase, | 258 | csr = musb_readw(mbase, |
260 | MUSB_EP_OFFSET(pImplChannel->epnum, | 259 | MUSB_EP_OFFSET(musb_channel->epnum, |
261 | MUSB_TXCSR)); | 260 | MUSB_TXCSR)); |
262 | csr &= ~(MUSB_TXCSR_AUTOSET | | 261 | csr &= ~(MUSB_TXCSR_AUTOSET | |
263 | MUSB_TXCSR_DMAENAB | | 262 | MUSB_TXCSR_DMAENAB | |
264 | MUSB_TXCSR_DMAMODE); | 263 | MUSB_TXCSR_DMAMODE); |
265 | musb_writew(mbase, | 264 | musb_writew(mbase, |
266 | MUSB_EP_OFFSET(pImplChannel->epnum, | 265 | MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR), |
267 | MUSB_TXCSR), | ||
268 | csr); | 266 | csr); |
269 | } else { | 267 | } else { |
270 | csr = musb_readw(mbase, | 268 | csr = musb_readw(mbase, |
271 | MUSB_EP_OFFSET(pImplChannel->epnum, | 269 | MUSB_EP_OFFSET(musb_channel->epnum, |
272 | MUSB_RXCSR)); | 270 | MUSB_RXCSR)); |
273 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | | 271 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
274 | MUSB_RXCSR_DMAENAB | | 272 | MUSB_RXCSR_DMAENAB | |
275 | MUSB_RXCSR_DMAMODE); | 273 | MUSB_RXCSR_DMAMODE); |
276 | musb_writew(mbase, | 274 | musb_writew(mbase, |
277 | MUSB_EP_OFFSET(pImplChannel->epnum, | 275 | MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR), |
278 | MUSB_RXCSR), | ||
279 | csr); | 276 | csr); |
280 | } | 277 | } |
281 | 278 | ||
282 | musb_writew(mbase, | 279 | musb_writew(mbase, |
283 | MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), | 280 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), |
284 | 0); | 281 | 0); |
285 | musb_writel(mbase, | 282 | musb_writel(mbase, |
286 | MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), | 283 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), |
287 | 0); | 284 | 0); |
288 | musb_writel(mbase, | 285 | musb_writel(mbase, |
289 | MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), | 286 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), |
290 | 0); | 287 | 0); |
291 | 288 | ||
292 | pChannel->status = MUSB_DMA_STATUS_FREE; | 289 | channel->status = MUSB_DMA_STATUS_FREE; |
293 | } | 290 | } |
291 | |||
294 | return 0; | 292 | return 0; |
295 | } | 293 | } |
296 | 294 | ||
297 | static irqreturn_t dma_controller_irq(int irq, void *private_data) | 295 | static irqreturn_t dma_controller_irq(int irq, void *private_data) |
298 | { | 296 | { |
299 | struct musb_dma_controller *controller = | 297 | struct musb_dma_controller *controller = private_data; |
300 | (struct musb_dma_controller *)private_data; | 298 | struct musb *musb = controller->private_data; |
301 | struct musb_dma_channel *pImplChannel; | 299 | struct musb_dma_channel *musb_channel; |
302 | struct musb *musb = controller->pDmaPrivate; | 300 | struct dma_channel *channel; |
303 | void __iomem *mbase = controller->pCoreBase; | 301 | |
304 | struct dma_channel *pChannel; | 302 | void __iomem *mbase = controller->base; |
305 | u8 bChannel; | 303 | |
306 | u16 csr; | ||
307 | u32 dwAddress; | ||
308 | u8 int_hsdma; | ||
309 | irqreturn_t retval = IRQ_NONE; | 304 | irqreturn_t retval = IRQ_NONE; |
305 | |||
310 | unsigned long flags; | 306 | unsigned long flags; |
311 | 307 | ||
308 | u8 bchannel; | ||
309 | u8 int_hsdma; | ||
310 | |||
311 | u32 addr; | ||
312 | u16 csr; | ||
313 | |||
312 | spin_lock_irqsave(&musb->lock, flags); | 314 | spin_lock_irqsave(&musb->lock, flags); |
313 | 315 | ||
314 | int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); | 316 | int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); |
315 | if (!int_hsdma) | 317 | if (!int_hsdma) |
316 | goto done; | 318 | goto done; |
317 | 319 | ||
318 | for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) { | 320 | for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { |
319 | if (int_hsdma & (1 << bChannel)) { | 321 | if (int_hsdma & (1 << bchannel)) { |
320 | pImplChannel = (struct musb_dma_channel *) | 322 | musb_channel = (struct musb_dma_channel *) |
321 | &(controller->aChannel[bChannel]); | 323 | &(controller->channel[bchannel]); |
322 | pChannel = &pImplChannel->Channel; | 324 | channel = &musb_channel->channel; |
323 | 325 | ||
324 | csr = musb_readw(mbase, | 326 | csr = musb_readw(mbase, |
325 | MUSB_HSDMA_CHANNEL_OFFSET(bChannel, | 327 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, |
326 | MUSB_HSDMA_CONTROL)); | 328 | MUSB_HSDMA_CONTROL)); |
327 | 329 | ||
328 | if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) | 330 | if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { |
329 | pImplChannel->Channel.status = | 331 | musb_channel->channel.status = |
330 | MUSB_DMA_STATUS_BUS_ABORT; | 332 | MUSB_DMA_STATUS_BUS_ABORT; |
331 | else { | 333 | } else { |
332 | u8 devctl; | 334 | u8 devctl; |
333 | 335 | ||
334 | dwAddress = musb_readl(mbase, | 336 | addr = musb_readl(mbase, |
335 | MUSB_HSDMA_CHANNEL_OFFSET( | 337 | MUSB_HSDMA_CHANNEL_OFFSET( |
336 | bChannel, | 338 | bchannel, |
337 | MUSB_HSDMA_ADDRESS)); | 339 | MUSB_HSDMA_ADDRESS)); |
338 | pChannel->actual_len = dwAddress | 340 | channel->actual_len = addr |
339 | - pImplChannel->dwStartAddress; | 341 | - musb_channel->start_addr; |
340 | 342 | ||
341 | DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", | 343 | DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", |
342 | pChannel, pImplChannel->dwStartAddress, | 344 | channel, musb_channel->start_addr, |
343 | dwAddress, pChannel->actual_len, | 345 | addr, channel->actual_len, |
344 | pImplChannel->len, | 346 | musb_channel->len, |
345 | (pChannel->actual_len | 347 | (channel->actual_len |
346 | < pImplChannel->len) ? | 348 | < musb_channel->len) ? |
347 | "=> reconfig 0" : "=> complete"); | 349 | "=> reconfig 0" : "=> complete"); |
348 | 350 | ||
349 | devctl = musb_readb(mbase, MUSB_DEVCTL); | 351 | devctl = musb_readb(mbase, MUSB_DEVCTL); |
350 | 352 | ||
351 | pChannel->status = MUSB_DMA_STATUS_FREE; | 353 | channel->status = MUSB_DMA_STATUS_FREE; |
352 | 354 | ||
353 | /* completed */ | 355 | /* completed */ |
354 | if ((devctl & MUSB_DEVCTL_HM) | 356 | if ((devctl & MUSB_DEVCTL_HM) |
355 | && (pImplChannel->transmit) | 357 | && (musb_channel->transmit) |
356 | && ((pChannel->desired_mode == 0) | 358 | && ((channel->desired_mode == 0) |
357 | || (pChannel->actual_len & | 359 | || (channel->actual_len & |
358 | (pImplChannel->wMaxPacketSize - 1))) | 360 | (musb_channel->max_packet_sz - 1))) |
359 | ) { | 361 | ) { |
360 | /* Send out the packet */ | 362 | /* Send out the packet */ |
361 | musb_ep_select(mbase, | 363 | musb_ep_select(mbase, |
362 | pImplChannel->epnum); | 364 | musb_channel->epnum); |
363 | musb_writew(mbase, MUSB_EP_OFFSET( | 365 | musb_writew(mbase, MUSB_EP_OFFSET( |
364 | pImplChannel->epnum, | 366 | musb_channel->epnum, |
365 | MUSB_TXCSR), | 367 | MUSB_TXCSR), |
366 | MUSB_TXCSR_TXPKTRDY); | 368 | MUSB_TXCSR_TXPKTRDY); |
367 | } else | 369 | } else { |
368 | musb_dma_completion( | 370 | musb_dma_completion( |
369 | musb, | 371 | musb, |
370 | pImplChannel->epnum, | 372 | musb_channel->epnum, |
371 | pImplChannel->transmit); | 373 | musb_channel->transmit); |
374 | } | ||
372 | } | 375 | } |
373 | } | 376 | } |
374 | } | 377 | } |
@@ -380,9 +383,9 @@ done: | |||
380 | 383 | ||
381 | void dma_controller_destroy(struct dma_controller *c) | 384 | void dma_controller_destroy(struct dma_controller *c) |
382 | { | 385 | { |
383 | struct musb_dma_controller *controller; | 386 | struct musb_dma_controller *controller = container_of(c, |
387 | struct musb_dma_controller, controller); | ||
384 | 388 | ||
385 | controller = container_of(c, struct musb_dma_controller, Controller); | ||
386 | if (!controller) | 389 | if (!controller) |
387 | return; | 390 | return; |
388 | 391 | ||
@@ -393,7 +396,7 @@ void dma_controller_destroy(struct dma_controller *c) | |||
393 | } | 396 | } |
394 | 397 | ||
395 | struct dma_controller *__init | 398 | struct dma_controller *__init |
396 | dma_controller_create(struct musb *musb, void __iomem *pCoreBase) | 399 | dma_controller_create(struct musb *musb, void __iomem *base) |
397 | { | 400 | { |
398 | struct musb_dma_controller *controller; | 401 | struct musb_dma_controller *controller; |
399 | struct device *dev = musb->controller; | 402 | struct device *dev = musb->controller; |
@@ -405,29 +408,30 @@ dma_controller_create(struct musb *musb, void __iomem *pCoreBase) | |||
405 | return NULL; | 408 | return NULL; |
406 | } | 409 | } |
407 | 410 | ||
408 | controller = kzalloc(sizeof(struct musb_dma_controller), GFP_KERNEL); | 411 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
409 | if (!controller) | 412 | if (!controller) |
410 | return NULL; | 413 | return NULL; |
411 | 414 | ||
412 | controller->bChannelCount = MUSB_HSDMA_CHANNELS; | 415 | controller->channel_count = MUSB_HSDMA_CHANNELS; |
413 | controller->pDmaPrivate = musb; | 416 | controller->private_data = musb; |
414 | controller->pCoreBase = pCoreBase; | 417 | controller->base = base; |
415 | 418 | ||
416 | controller->Controller.start = dma_controller_start; | 419 | controller->controller.start = dma_controller_start; |
417 | controller->Controller.stop = dma_controller_stop; | 420 | controller->controller.stop = dma_controller_stop; |
418 | controller->Controller.channel_alloc = dma_channel_allocate; | 421 | controller->controller.channel_alloc = dma_channel_allocate; |
419 | controller->Controller.channel_release = dma_channel_release; | 422 | controller->controller.channel_release = dma_channel_release; |
420 | controller->Controller.channel_program = dma_channel_program; | 423 | controller->controller.channel_program = dma_channel_program; |
421 | controller->Controller.channel_abort = dma_channel_abort; | 424 | controller->controller.channel_abort = dma_channel_abort; |
422 | 425 | ||
423 | if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, | 426 | if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, |
424 | musb->controller->bus_id, &controller->Controller)) { | 427 | musb->controller->bus_id, &controller->controller)) { |
425 | dev_err(dev, "request_irq %d failed!\n", irq); | 428 | dev_err(dev, "request_irq %d failed!\n", irq); |
426 | dma_controller_destroy(&controller->Controller); | 429 | dma_controller_destroy(&controller->controller); |
430 | |||
427 | return NULL; | 431 | return NULL; |
428 | } | 432 | } |
429 | 433 | ||
430 | controller->irq = irq; | 434 | controller->irq = irq; |
431 | 435 | ||
432 | return &controller->Controller; | 436 | return &controller->controller; |
433 | } | 437 | } |