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authorYuan-Hsin Chen <yhchen@faraday-tech.com>2011-01-18 01:49:28 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-01-22 22:45:36 -0500
commit0fe6f1d1f612035d78d8d195bbc3485a341386d5 (patch)
treec62236f95906cd576788897674f85bf43c5392da /drivers/usb
parentbc0f23dccad16c7834cb09d943981475be81ddb1 (diff)
usb: udc: add Faraday fusb300 driver
USB2.0 device controller driver for Faraday fubs300 Signed-off-by: Yuan-Hsin Chen <yhchen@faraday-tech.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/gadget/Kconfig12
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/fusb300_udc.c1743
-rw-r--r--drivers/usb/gadget/fusb300_udc.h687
4 files changed, 2443 insertions, 0 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 1dc9739277b4..48455397ef61 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -176,6 +176,18 @@ config USB_FSL_USB2
176 default USB_GADGET 176 default USB_GADGET
177 select USB_GADGET_SELECTED 177 select USB_GADGET_SELECTED
178 178
179config USB_GADGET_FUSB300
180 boolean "Faraday FUSB300 USB Peripheral Controller"
181 select USB_GADGET_DUALSPEED
182 help
183 Faraday usb device controller FUSB300 driver
184
185config USB_FUSB300
186 tristate
187 depends on USB_GADGET_FUSB300
188 default USB_GADGET
189 select USB_GADGET_SELECTED
190
179config USB_GADGET_LH7A40X 191config USB_GADGET_LH7A40X
180 boolean "LH7A40X" 192 boolean "LH7A40X"
181 depends on ARCH_LH7A40X 193 depends on ARCH_LH7A40X
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 55f5e8ae5924..305286e181d5 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_USB_EG20T) += pch_udc.o
28obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o 28obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
29mv_udc-y := mv_udc_core.o mv_udc_phy.o 29mv_udc-y := mv_udc_core.o mv_udc_phy.o
30obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o 30obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
31obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
31 32
32# 33#
33# USB gadget drivers 34# USB gadget drivers
diff --git a/drivers/usb/gadget/fusb300_udc.c b/drivers/usb/gadget/fusb300_udc.c
new file mode 100644
index 000000000000..fd4fd69f5ad6
--- /dev/null
+++ b/drivers/usb/gadget/fusb300_udc.c
@@ -0,0 +1,1743 @@
1/*
2 * Fusb300 UDC (USB gadget)
3 *
4 * Copyright (C) 2010 Faraday Technology Corp.
5 *
6 * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22#include <linux/dma-mapping.h>
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/platform_device.h>
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29
30#include "fusb300_udc.h"
31
32MODULE_DESCRIPTION("FUSB300 USB gadget driver");
33MODULE_LICENSE("GPL");
34MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>");
35MODULE_ALIAS("platform:fusb300_udc");
36
37#define DRIVER_VERSION "20 October 2010"
38
39static const char udc_name[] = "fusb300_udc";
40static const char * const fusb300_ep_name[] = {
41 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
42};
43
44static void done(struct fusb300_ep *ep, struct fusb300_request *req,
45 int status);
46
47static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
48 u32 value)
49{
50 u32 reg = ioread32(fusb300->reg + offset);
51
52 reg |= value;
53 iowrite32(reg, fusb300->reg + offset);
54}
55
56static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
57 u32 value)
58{
59 u32 reg = ioread32(fusb300->reg + offset);
60
61 reg &= ~value;
62 iowrite32(reg, fusb300->reg + offset);
63}
64
65
66static void fusb300_ep_setting(struct fusb300_ep *ep,
67 struct fusb300_ep_info info)
68{
69 ep->epnum = info.epnum;
70 ep->type = info.type;
71}
72
73static int fusb300_ep_release(struct fusb300_ep *ep)
74{
75 if (!ep->epnum)
76 return 0;
77 ep->epnum = 0;
78 ep->stall = 0;
79 ep->wedged = 0;
80 return 0;
81}
82
83static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
84 u32 ep)
85{
86 u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
87
88 val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
89 val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
90 iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
91}
92
93static void fusb300_set_start_entry(struct fusb300 *fusb300,
94 u8 ep)
95{
96 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
97 u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
98
99 reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
100 reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
101 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
102 if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
103 fusb300->fifo_entry_num = 0;
104 fusb300->addrofs = 0;
105 pr_err("fifo entry is over the maximum number!\n");
106 } else
107 fusb300->fifo_entry_num++;
108}
109
110/* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
111static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
112 struct fusb300_ep_info info)
113{
114 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
115
116 reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
117 reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
118 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
119 fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
120}
121
122static void ep_fifo_setting(struct fusb300 *fusb300,
123 struct fusb300_ep_info info)
124{
125 fusb300_set_fifo_entry(fusb300, info.epnum);
126 fusb300_set_start_entry(fusb300, info.epnum);
127 fusb300_set_epaddrofs(fusb300, info);
128}
129
130static void fusb300_set_eptype(struct fusb300 *fusb300,
131 struct fusb300_ep_info info)
132{
133 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
134
135 reg &= ~FUSB300_EPSET1_TYPE_MSK;
136 reg |= FUSB300_EPSET1_TYPE(info.type);
137 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
138}
139
140static void fusb300_set_epdir(struct fusb300 *fusb300,
141 struct fusb300_ep_info info)
142{
143 u32 reg;
144
145 if (!info.dir_in)
146 return;
147 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
148 reg &= ~FUSB300_EPSET1_DIR_MSK;
149 reg |= FUSB300_EPSET1_DIRIN;
150 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
151}
152
153static void fusb300_set_ep_active(struct fusb300 *fusb300,
154 u8 ep)
155{
156 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
157
158 reg |= FUSB300_EPSET1_ACTEN;
159 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
160}
161
162static void fusb300_set_epmps(struct fusb300 *fusb300,
163 struct fusb300_ep_info info)
164{
165 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
166
167 reg &= ~FUSB300_EPSET2_MPS_MSK;
168 reg |= FUSB300_EPSET2_MPS(info.maxpacket);
169 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
170}
171
172static void fusb300_set_interval(struct fusb300 *fusb300,
173 struct fusb300_ep_info info)
174{
175 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
176
177 reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
178 reg |= FUSB300_EPSET1_INTERVAL(info.interval);
179 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
180}
181
182static void fusb300_set_bwnum(struct fusb300 *fusb300,
183 struct fusb300_ep_info info)
184{
185 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
186
187 reg &= ~FUSB300_EPSET1_BWNUM(0x3);
188 reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
189 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
190}
191
192static void set_ep_reg(struct fusb300 *fusb300,
193 struct fusb300_ep_info info)
194{
195 fusb300_set_eptype(fusb300, info);
196 fusb300_set_epdir(fusb300, info);
197 fusb300_set_epmps(fusb300, info);
198
199 if (info.interval)
200 fusb300_set_interval(fusb300, info);
201
202 if (info.bw_num)
203 fusb300_set_bwnum(fusb300, info);
204
205 fusb300_set_ep_active(fusb300, info.epnum);
206}
207
208static int config_ep(struct fusb300_ep *ep,
209 const struct usb_endpoint_descriptor *desc)
210{
211 struct fusb300 *fusb300 = ep->fusb300;
212 struct fusb300_ep_info info;
213
214 ep->desc = desc;
215
216 info.interval = 0;
217 info.addrofs = 0;
218 info.bw_num = 0;
219
220 info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
221 info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
222 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
223 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
224
225 if ((info.type == USB_ENDPOINT_XFER_INT) ||
226 (info.type == USB_ENDPOINT_XFER_ISOC)) {
227 info.interval = desc->bInterval;
228 if (info.type == USB_ENDPOINT_XFER_ISOC)
229 info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11);
230 }
231
232 ep_fifo_setting(fusb300, info);
233
234 set_ep_reg(fusb300, info);
235
236 fusb300_ep_setting(ep, info);
237
238 fusb300->ep[info.epnum] = ep;
239
240 return 0;
241}
242
243static int fusb300_enable(struct usb_ep *_ep,
244 const struct usb_endpoint_descriptor *desc)
245{
246 struct fusb300_ep *ep;
247
248 ep = container_of(_ep, struct fusb300_ep, ep);
249
250 if (ep->fusb300->reenum) {
251 ep->fusb300->fifo_entry_num = 0;
252 ep->fusb300->addrofs = 0;
253 ep->fusb300->reenum = 0;
254 }
255
256 return config_ep(ep, desc);
257}
258
259static int fusb300_disable(struct usb_ep *_ep)
260{
261 struct fusb300_ep *ep;
262 struct fusb300_request *req;
263 unsigned long flags;
264
265 ep = container_of(_ep, struct fusb300_ep, ep);
266
267 BUG_ON(!ep);
268
269 while (!list_empty(&ep->queue)) {
270 req = list_entry(ep->queue.next, struct fusb300_request, queue);
271 spin_lock_irqsave(&ep->fusb300->lock, flags);
272 done(ep, req, -ECONNRESET);
273 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
274 }
275
276 return fusb300_ep_release(ep);
277}
278
279static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
280 gfp_t gfp_flags)
281{
282 struct fusb300_request *req;
283
284 req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
285 if (!req)
286 return NULL;
287 INIT_LIST_HEAD(&req->queue);
288
289 return &req->req;
290}
291
292static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
293{
294 struct fusb300_request *req;
295
296 req = container_of(_req, struct fusb300_request, req);
297 kfree(req);
298}
299
300static int enable_fifo_int(struct fusb300_ep *ep)
301{
302 struct fusb300 *fusb300 = ep->fusb300;
303
304 if (ep->epnum) {
305 fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
306 FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
307 } else {
308 pr_err("can't enable_fifo_int ep0\n");
309 return -EINVAL;
310 }
311
312 return 0;
313}
314
315static int disable_fifo_int(struct fusb300_ep *ep)
316{
317 struct fusb300 *fusb300 = ep->fusb300;
318
319 if (ep->epnum) {
320 fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
321 FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
322 } else {
323 pr_err("can't disable_fifo_int ep0\n");
324 return -EINVAL;
325 }
326
327 return 0;
328}
329
330static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
331{
332 u32 reg;
333
334 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
335 reg &= ~FUSB300_CSR_LEN_MSK;
336 reg |= FUSB300_CSR_LEN(length);
337 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
338}
339
340/* write data to cx fifo */
341static void fusb300_wrcxf(struct fusb300_ep *ep,
342 struct fusb300_request *req)
343{
344 int i = 0;
345 u8 *tmp;
346 u32 data;
347 struct fusb300 *fusb300 = ep->fusb300;
348 u32 length = req->req.length - req->req.actual;
349
350 tmp = req->req.buf + req->req.actual;
351
352 if (length > SS_CTL_MAX_PACKET_SIZE) {
353 fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
354 for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
355 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
356 *(tmp + 3) << 24;
357 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
358 tmp += 4;
359 }
360 req->req.actual += SS_CTL_MAX_PACKET_SIZE;
361 } else { /* length is less than max packet size */
362 fusb300_set_cxlen(fusb300, length);
363 for (i = length >> 2; i > 0; i--) {
364 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
365 *(tmp + 3) << 24;
366 printk(KERN_DEBUG " 0x%x\n", data);
367 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
368 tmp = tmp + 4;
369 }
370 switch (length % 4) {
371 case 1:
372 data = *tmp;
373 printk(KERN_DEBUG " 0x%x\n", data);
374 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
375 break;
376 case 2:
377 data = *tmp | *(tmp + 1) << 8;
378 printk(KERN_DEBUG " 0x%x\n", data);
379 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
380 break;
381 case 3:
382 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
383 printk(KERN_DEBUG " 0x%x\n", data);
384 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
385 break;
386 default:
387 break;
388 }
389 req->req.actual += length;
390 }
391}
392
393static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
394{
395 fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
396 FUSB300_EPSET0_STL);
397}
398
399static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
400{
401 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
402
403 if (reg & FUSB300_EPSET0_STL) {
404 printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
405 reg &= ~FUSB300_EPSET0_STL;
406 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
407 }
408}
409
410static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
411{
412 if (ep->fusb300->ep0_dir) { /* if IN */
413 if (req->req.length) {
414 fusb300_wrcxf(ep, req);
415 } else
416 printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
417 __func__, req->req.length);
418 if ((req->req.length == req->req.actual) ||
419 (req->req.actual < ep->ep.maxpacket))
420 done(ep, req, 0);
421 } else { /* OUT */
422 if (!req->req.length)
423 done(ep, req, 0);
424 else
425 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
426 FUSB300_IGER1_CX_OUT_INT);
427 }
428}
429
430static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
431 gfp_t gfp_flags)
432{
433 struct fusb300_ep *ep;
434 struct fusb300_request *req;
435 unsigned long flags;
436 int request = 0;
437
438 ep = container_of(_ep, struct fusb300_ep, ep);
439 req = container_of(_req, struct fusb300_request, req);
440
441 if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
442 return -ESHUTDOWN;
443
444 spin_lock_irqsave(&ep->fusb300->lock, flags);
445
446 if (list_empty(&ep->queue))
447 request = 1;
448
449 list_add_tail(&req->queue, &ep->queue);
450
451 req->req.actual = 0;
452 req->req.status = -EINPROGRESS;
453
454 if (ep->desc == NULL) /* ep0 */
455 ep0_queue(ep, req);
456 else if (request && !ep->stall)
457 enable_fifo_int(ep);
458
459 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
460
461 return 0;
462}
463
464static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
465{
466 struct fusb300_ep *ep;
467 struct fusb300_request *req;
468 unsigned long flags;
469
470 ep = container_of(_ep, struct fusb300_ep, ep);
471 req = container_of(_req, struct fusb300_request, req);
472
473 spin_lock_irqsave(&ep->fusb300->lock, flags);
474 if (!list_empty(&ep->queue))
475 done(ep, req, -ECONNRESET);
476 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
477
478 return 0;
479}
480
481static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
482{
483 struct fusb300_ep *ep;
484 struct fusb300 *fusb300;
485 unsigned long flags;
486 int ret = 0;
487
488 ep = container_of(_ep, struct fusb300_ep, ep);
489
490 fusb300 = ep->fusb300;
491
492 spin_lock_irqsave(&ep->fusb300->lock, flags);
493
494 if (!list_empty(&ep->queue)) {
495 ret = -EAGAIN;
496 goto out;
497 }
498
499 if (value) {
500 fusb300_set_epnstall(fusb300, ep->epnum);
501 ep->stall = 1;
502 if (wedge)
503 ep->wedged = 1;
504 } else {
505 fusb300_clear_epnstall(fusb300, ep->epnum);
506 ep->stall = 0;
507 ep->wedged = 0;
508 }
509
510out:
511 spin_unlock_irqrestore(&ep->fusb300->lock, flags);
512 return ret;
513}
514
515static int fusb300_set_halt(struct usb_ep *_ep, int value)
516{
517 return fusb300_set_halt_and_wedge(_ep, value, 0);
518}
519
520static int fusb300_set_wedge(struct usb_ep *_ep)
521{
522 return fusb300_set_halt_and_wedge(_ep, 1, 1);
523}
524
525static void fusb300_fifo_flush(struct usb_ep *_ep)
526{
527}
528
529static struct usb_ep_ops fusb300_ep_ops = {
530 .enable = fusb300_enable,
531 .disable = fusb300_disable,
532
533 .alloc_request = fusb300_alloc_request,
534 .free_request = fusb300_free_request,
535
536 .queue = fusb300_queue,
537 .dequeue = fusb300_dequeue,
538
539 .set_halt = fusb300_set_halt,
540 .fifo_flush = fusb300_fifo_flush,
541 .set_wedge = fusb300_set_wedge,
542};
543
544/*****************************************************************************/
545static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
546 u32 value)
547{
548 iowrite32(value, fusb300->reg + offset);
549}
550
551static void fusb300_reset(void)
552{
553}
554
555static void fusb300_set_cxstall(struct fusb300 *fusb300)
556{
557 fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
558 FUSB300_CSR_STL);
559}
560
561static void fusb300_set_cxdone(struct fusb300 *fusb300)
562{
563 fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
564 FUSB300_CSR_DONE);
565}
566
567/* read data from cx fifo */
568void fusb300_rdcxf(struct fusb300 *fusb300,
569 u8 *buffer, u32 length)
570{
571 int i = 0;
572 u8 *tmp;
573 u32 data;
574
575 tmp = buffer;
576
577 for (i = (length >> 2); i > 0; i--) {
578 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
579 printk(KERN_DEBUG " 0x%x\n", data);
580 *tmp = data & 0xFF;
581 *(tmp + 1) = (data >> 8) & 0xFF;
582 *(tmp + 2) = (data >> 16) & 0xFF;
583 *(tmp + 3) = (data >> 24) & 0xFF;
584 tmp = tmp + 4;
585 }
586
587 switch (length % 4) {
588 case 1:
589 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
590 printk(KERN_DEBUG " 0x%x\n", data);
591 *tmp = data & 0xFF;
592 break;
593 case 2:
594 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
595 printk(KERN_DEBUG " 0x%x\n", data);
596 *tmp = data & 0xFF;
597 *(tmp + 1) = (data >> 8) & 0xFF;
598 break;
599 case 3:
600 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
601 printk(KERN_DEBUG " 0x%x\n", data);
602 *tmp = data & 0xFF;
603 *(tmp + 1) = (data >> 8) & 0xFF;
604 *(tmp + 2) = (data >> 16) & 0xFF;
605 break;
606 default:
607 break;
608 }
609}
610
611#if 0
612static void fusb300_dbg_fifo(struct fusb300_ep *ep,
613 u8 entry, u16 length)
614{
615 u32 reg;
616 u32 i = 0;
617 u32 j = 0;
618
619 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
620 reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
621 FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
622 reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
623 FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
624 iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
625
626 for (i = 0; i < (length >> 2); i++) {
627 if (i * 4 == 1024)
628 break;
629 reg = ioread32(ep->fusb300->reg +
630 FUSB300_OFFSET_BUFDBG_START + i * 4);
631 printk(KERN_DEBUG" 0x%-8x", reg);
632 j++;
633 if ((j % 4) == 0)
634 printk(KERN_DEBUG "\n");
635 }
636
637 if (length % 4) {
638 reg = ioread32(ep->fusb300->reg +
639 FUSB300_OFFSET_BUFDBG_START + i * 4);
640 printk(KERN_DEBUG " 0x%x\n", reg);
641 }
642
643 if ((j % 4) != 0)
644 printk(KERN_DEBUG "\n");
645
646 fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
647 FUSB300_GTM_TST_FIFO_DEG);
648}
649
650static void fusb300_cmp_dbg_fifo(struct fusb300_ep *ep,
651 u8 entry, u16 length, u8 *golden)
652{
653 u32 reg;
654 u32 i = 0;
655 u32 golden_value;
656 u8 *tmp;
657
658 tmp = golden;
659
660 printk(KERN_DEBUG "fusb300_cmp_dbg_fifo (entry %d) : start\n", entry);
661
662 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
663 reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
664 FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
665 reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
666 FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
667 iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
668
669 for (i = 0; i < (length >> 2); i++) {
670 if (i * 4 == 1024)
671 break;
672 golden_value = *tmp | *(tmp + 1) << 8 |
673 *(tmp + 2) << 16 | *(tmp + 3) << 24;
674
675 reg = ioread32(ep->fusb300->reg +
676 FUSB300_OFFSET_BUFDBG_START + i*4);
677
678 if (reg != golden_value) {
679 printk(KERN_DEBUG "0x%x : ", (u32)(ep->fusb300->reg +
680 FUSB300_OFFSET_BUFDBG_START + i*4));
681 printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
682 golden_value, reg);
683 }
684 tmp += 4;
685 }
686
687 switch (length % 4) {
688 case 1:
689 golden_value = *tmp;
690 case 2:
691 golden_value = *tmp | *(tmp + 1) << 8;
692 case 3:
693 golden_value = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
694 default:
695 break;
696
697 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_BUFDBG_START + i*4);
698 if (reg != golden_value) {
699 printk(KERN_DEBUG "0x%x:", (u32)(ep->fusb300->reg +
700 FUSB300_OFFSET_BUFDBG_START + i*4));
701 printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
702 golden_value, reg);
703 }
704 }
705
706 printk(KERN_DEBUG "fusb300_cmp_dbg_fifo : end\n");
707 fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
708 FUSB300_GTM_TST_FIFO_DEG);
709}
710#endif
711
712static void fusb300_rdfifo(struct fusb300_ep *ep,
713 struct fusb300_request *req,
714 u32 length)
715{
716 int i = 0;
717 u8 *tmp;
718 u32 data, reg;
719 struct fusb300 *fusb300 = ep->fusb300;
720
721 tmp = req->req.buf + req->req.actual;
722 req->req.actual += length;
723
724 if (req->req.actual > req->req.length)
725 printk(KERN_DEBUG "req->req.actual > req->req.length\n");
726
727 for (i = (length >> 2); i > 0; i--) {
728 data = ioread32(fusb300->reg +
729 FUSB300_OFFSET_EPPORT(ep->epnum));
730 *tmp = data & 0xFF;
731 *(tmp + 1) = (data >> 8) & 0xFF;
732 *(tmp + 2) = (data >> 16) & 0xFF;
733 *(tmp + 3) = (data >> 24) & 0xFF;
734 tmp = tmp + 4;
735 }
736
737 switch (length % 4) {
738 case 1:
739 data = ioread32(fusb300->reg +
740 FUSB300_OFFSET_EPPORT(ep->epnum));
741 *tmp = data & 0xFF;
742 break;
743 case 2:
744 data = ioread32(fusb300->reg +
745 FUSB300_OFFSET_EPPORT(ep->epnum));
746 *tmp = data & 0xFF;
747 *(tmp + 1) = (data >> 8) & 0xFF;
748 break;
749 case 3:
750 data = ioread32(fusb300->reg +
751 FUSB300_OFFSET_EPPORT(ep->epnum));
752 *tmp = data & 0xFF;
753 *(tmp + 1) = (data >> 8) & 0xFF;
754 *(tmp + 2) = (data >> 16) & 0xFF;
755 break;
756 default:
757 break;
758 }
759
760 do {
761 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
762 reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
763 if (i)
764 printk(KERN_INFO "sync fifo is not empty!\n");
765 i++;
766 } while (!reg);
767}
768
769/* write data to fifo */
770static void fusb300_wrfifo(struct fusb300_ep *ep,
771 struct fusb300_request *req)
772{
773 int i = 0;
774 u8 *tmp;
775 u32 data, reg;
776 struct fusb300 *fusb300 = ep->fusb300;
777
778 tmp = req->req.buf;
779 req->req.actual = req->req.length;
780
781 for (i = (req->req.length >> 2); i > 0; i--) {
782 data = *tmp | *(tmp + 1) << 8 |
783 *(tmp + 2) << 16 | *(tmp + 3) << 24;
784
785 iowrite32(data, fusb300->reg +
786 FUSB300_OFFSET_EPPORT(ep->epnum));
787 tmp += 4;
788 }
789
790 switch (req->req.length % 4) {
791 case 1:
792 data = *tmp;
793 iowrite32(data, fusb300->reg +
794 FUSB300_OFFSET_EPPORT(ep->epnum));
795 break;
796 case 2:
797 data = *tmp | *(tmp + 1) << 8;
798 iowrite32(data, fusb300->reg +
799 FUSB300_OFFSET_EPPORT(ep->epnum));
800 break;
801 case 3:
802 data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
803 iowrite32(data, fusb300->reg +
804 FUSB300_OFFSET_EPPORT(ep->epnum));
805 break;
806 default:
807 break;
808 }
809
810 do {
811 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
812 reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
813 if (i)
814 printk(KERN_INFO"sync fifo is not empty!\n");
815 i++;
816 } while (!reg);
817}
818
819static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
820{
821 u8 value;
822 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
823
824 value = reg & FUSB300_EPSET0_STL;
825
826 return value;
827}
828
829static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
830{
831 u8 value;
832 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
833
834 value = (reg & FUSB300_CSR_STL) >> 1;
835
836 return value;
837}
838
839static void request_error(struct fusb300 *fusb300)
840{
841 fusb300_set_cxstall(fusb300);
842 printk(KERN_DEBUG "request error!!\n");
843}
844
845static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
846__releases(fusb300->lock)
847__acquires(fusb300->lock)
848{
849 u8 ep;
850 u16 status = 0;
851 u16 w_index = ctrl->wIndex;
852
853 switch (ctrl->bRequestType & USB_RECIP_MASK) {
854 case USB_RECIP_DEVICE:
855 status = 1 << USB_DEVICE_SELF_POWERED;
856 break;
857 case USB_RECIP_INTERFACE:
858 status = 0;
859 break;
860 case USB_RECIP_ENDPOINT:
861 ep = w_index & USB_ENDPOINT_NUMBER_MASK;
862 if (ep) {
863 if (fusb300_get_epnstall(fusb300, ep))
864 status = 1 << USB_ENDPOINT_HALT;
865 } else {
866 if (fusb300_get_cxstall(fusb300))
867 status = 0;
868 }
869 break;
870
871 default:
872 request_error(fusb300);
873 return; /* exit */
874 }
875
876 fusb300->ep0_data = cpu_to_le16(status);
877 fusb300->ep0_req->buf = &fusb300->ep0_data;
878 fusb300->ep0_req->length = 2;
879
880 spin_unlock(&fusb300->lock);
881 fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
882 spin_lock(&fusb300->lock);
883}
884
885static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
886{
887 u8 ep;
888
889 switch (ctrl->bRequestType & USB_RECIP_MASK) {
890 case USB_RECIP_DEVICE:
891 fusb300_set_cxdone(fusb300);
892 break;
893 case USB_RECIP_INTERFACE:
894 fusb300_set_cxdone(fusb300);
895 break;
896 case USB_RECIP_ENDPOINT: {
897 u16 w_index = le16_to_cpu(ctrl->wIndex);
898
899 ep = w_index & USB_ENDPOINT_NUMBER_MASK;
900 if (ep)
901 fusb300_set_epnstall(fusb300, ep);
902 else
903 fusb300_set_cxstall(fusb300);
904 fusb300_set_cxdone(fusb300);
905 }
906 break;
907 default:
908 request_error(fusb300);
909 break;
910 }
911}
912
913static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
914{
915 fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
916 FUSB300_EPSET0_CLRSEQNUM);
917}
918
919static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
920{
921 struct fusb300_ep *ep =
922 fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
923
924 switch (ctrl->bRequestType & USB_RECIP_MASK) {
925 case USB_RECIP_DEVICE:
926 fusb300_set_cxdone(fusb300);
927 break;
928 case USB_RECIP_INTERFACE:
929 fusb300_set_cxdone(fusb300);
930 break;
931 case USB_RECIP_ENDPOINT:
932 if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
933 if (ep->wedged) {
934 fusb300_set_cxdone(fusb300);
935 break;
936 }
937 if (ep->stall) {
938 ep->stall = 0;
939 fusb300_clear_seqnum(fusb300, ep->epnum);
940 fusb300_clear_epnstall(fusb300, ep->epnum);
941 if (!list_empty(&ep->queue))
942 enable_fifo_int(ep);
943 }
944 }
945 fusb300_set_cxdone(fusb300);
946 break;
947 default:
948 request_error(fusb300);
949 break;
950 }
951}
952
953static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
954{
955 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
956
957 reg &= ~FUSB300_DAR_DRVADDR_MSK;
958 reg |= FUSB300_DAR_DRVADDR(addr);
959
960 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
961}
962
963static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
964{
965 if (ctrl->wValue >= 0x0100)
966 request_error(fusb300);
967 else {
968 fusb300_set_dev_addr(fusb300, ctrl->wValue);
969 fusb300_set_cxdone(fusb300);
970 }
971}
972
973#define UVC_COPY_DESCRIPTORS(mem, src) \
974 do { \
975 const struct usb_descriptor_header * const *__src; \
976 for (__src = src; *__src; ++__src) { \
977 memcpy(mem, *__src, (*__src)->bLength); \
978 mem += (*__src)->bLength; \
979 } \
980 } while (0)
981
982static void fusb300_ep0_complete(struct usb_ep *ep,
983 struct usb_request *req)
984{
985}
986
987static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
988{
989 u8 *p = (u8 *)ctrl;
990 u8 ret = 0;
991 u8 i = 0;
992
993 fusb300_rdcxf(fusb300, p, 8);
994 fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
995 fusb300->ep0_length = ctrl->wLength;
996
997 /* check request */
998 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
999 switch (ctrl->bRequest) {
1000 case USB_REQ_GET_STATUS:
1001 get_status(fusb300, ctrl);
1002 break;
1003 case USB_REQ_CLEAR_FEATURE:
1004 clear_feature(fusb300, ctrl);
1005 break;
1006 case USB_REQ_SET_FEATURE:
1007 set_feature(fusb300, ctrl);
1008 break;
1009 case USB_REQ_SET_ADDRESS:
1010 set_address(fusb300, ctrl);
1011 break;
1012 case USB_REQ_SET_CONFIGURATION:
1013 fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
1014 FUSB300_DAR_SETCONFG);
1015 /* clear sequence number */
1016 for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
1017 fusb300_clear_seqnum(fusb300, i);
1018 fusb300->reenum = 1;
1019 ret = 1;
1020 break;
1021 default:
1022 ret = 1;
1023 break;
1024 }
1025 } else
1026 ret = 1;
1027
1028 return ret;
1029}
1030
1031static void fusb300_set_ep_bycnt(struct fusb300_ep *ep, u32 bycnt)
1032{
1033 struct fusb300 *fusb300 = ep->fusb300;
1034 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
1035
1036 reg &= ~FUSB300_FFR_BYCNT;
1037 reg |= bycnt & FUSB300_FFR_BYCNT;
1038
1039 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
1040}
1041
1042static void done(struct fusb300_ep *ep, struct fusb300_request *req,
1043 int status)
1044{
1045 list_del_init(&req->queue);
1046
1047 /* don't modify queue heads during completion callback */
1048 if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
1049 req->req.status = -ESHUTDOWN;
1050 else
1051 req->req.status = status;
1052
1053 spin_unlock(&ep->fusb300->lock);
1054 req->req.complete(&ep->ep, &req->req);
1055 spin_lock(&ep->fusb300->lock);
1056
1057 if (ep->epnum) {
1058 disable_fifo_int(ep);
1059 if (!list_empty(&ep->queue))
1060 enable_fifo_int(ep);
1061 } else
1062 fusb300_set_cxdone(ep->fusb300);
1063}
1064
1065void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep,
1066 struct fusb300_request *req)
1067{
1068 u32 value;
1069 u32 reg;
1070
1071 /* wait SW owner */
1072 do {
1073 reg = ioread32(ep->fusb300->reg +
1074 FUSB300_OFFSET_EPPRD_W0(ep->epnum));
1075 reg &= FUSB300_EPPRD0_H;
1076 } while (reg);
1077
1078 iowrite32((u32) req->req.buf, ep->fusb300->reg +
1079 FUSB300_OFFSET_EPPRD_W1(ep->epnum));
1080
1081 value = FUSB300_EPPRD0_BTC(req->req.length) | FUSB300_EPPRD0_H |
1082 FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
1083 iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
1084
1085 iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
1086
1087 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
1088 FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
1089}
1090
1091static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
1092{
1093 u32 reg;
1094
1095 do {
1096 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
1097 if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
1098 (reg & FUSB300_IGR1_WARM_RST_INT) ||
1099 (reg & FUSB300_IGR1_HOT_RST_INT) ||
1100 (reg & FUSB300_IGR1_USBRST_INT)
1101 )
1102 goto IDMA_RESET;
1103 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
1104 reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
1105 } while (!reg);
1106
1107 fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
1108 FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
1109IDMA_RESET:
1110 fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0,
1111 FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
1112}
1113
1114static void fusb300_set_idma(struct fusb300_ep *ep,
1115 struct fusb300_request *req)
1116{
1117 dma_addr_t d;
1118 u8 *tmp = NULL;
1119
1120 d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE);
1121
1122 if (dma_mapping_error(NULL, d)) {
1123 kfree(req->req.buf);
1124 printk(KERN_DEBUG "dma_mapping_error\n");
1125 }
1126
1127 dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE);
1128
1129 fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
1130 FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
1131
1132 tmp = req->req.buf;
1133 req->req.buf = (u8 *)d;
1134
1135 fusb300_fill_idma_prdtbl(ep, req);
1136 /* check idma is done */
1137 fusb300_wait_idma_finished(ep);
1138
1139 req->req.buf = tmp;
1140
1141 if (d)
1142 dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE);
1143}
1144
1145static void in_ep_fifo_handler(struct fusb300_ep *ep)
1146{
1147 struct fusb300_request *req = list_entry(ep->queue.next,
1148 struct fusb300_request, queue);
1149
1150 if (req->req.length) {
1151#if 0
1152 fusb300_set_ep_bycnt(ep, req->req.length);
1153 fusb300_wrfifo(ep, req);
1154#else
1155 fusb300_set_idma(ep, req);
1156#endif
1157 }
1158 done(ep, req, 0);
1159}
1160
1161static void out_ep_fifo_handler(struct fusb300_ep *ep)
1162{
1163 struct fusb300 *fusb300 = ep->fusb300;
1164 struct fusb300_request *req = list_entry(ep->queue.next,
1165 struct fusb300_request, queue);
1166 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
1167 u32 length = reg & FUSB300_FFR_BYCNT;
1168
1169 fusb300_rdfifo(ep, req, length);
1170
1171 /* finish out transfer */
1172 if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
1173 done(ep, req, 0);
1174}
1175
1176static void check_device_mode(struct fusb300 *fusb300)
1177{
1178 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
1179
1180 switch (reg & FUSB300_GCR_DEVEN_MSK) {
1181 case FUSB300_GCR_DEVEN_SS:
1182 fusb300->gadget.speed = USB_SPEED_SUPER;
1183 break;
1184 case FUSB300_GCR_DEVEN_HS:
1185 fusb300->gadget.speed = USB_SPEED_HIGH;
1186 break;
1187 case FUSB300_GCR_DEVEN_FS:
1188 fusb300->gadget.speed = USB_SPEED_FULL;
1189 break;
1190 default:
1191 fusb300->gadget.speed = USB_SPEED_UNKNOWN;
1192 break;
1193 }
1194 printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
1195}
1196
1197
1198static void fusb300_ep0out(struct fusb300 *fusb300)
1199{
1200 struct fusb300_ep *ep = fusb300->ep[0];
1201 u32 reg;
1202
1203 if (!list_empty(&ep->queue)) {
1204 struct fusb300_request *req;
1205
1206 req = list_first_entry(&ep->queue,
1207 struct fusb300_request, queue);
1208 if (req->req.length)
1209 fusb300_rdcxf(ep->fusb300, req->req.buf,
1210 req->req.length);
1211 done(ep, req, 0);
1212 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
1213 reg &= ~FUSB300_IGER1_CX_OUT_INT;
1214 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
1215 } else
1216 pr_err("%s : empty queue\n", __func__);
1217}
1218
1219static void fusb300_ep0in(struct fusb300 *fusb300)
1220{
1221 struct fusb300_request *req;
1222 struct fusb300_ep *ep = fusb300->ep[0];
1223
1224 if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
1225 req = list_entry(ep->queue.next,
1226 struct fusb300_request, queue);
1227 if (req->req.length)
1228 fusb300_wrcxf(ep, req);
1229 if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
1230 done(ep, req, 0);
1231 } else
1232 fusb300_set_cxdone(fusb300);
1233}
1234
1235static void fusb300_grp2_handler(void)
1236{
1237}
1238
1239static void fusb300_grp3_handler(void)
1240{
1241}
1242
1243static void fusb300_grp4_handler(void)
1244{
1245}
1246
1247static void fusb300_grp5_handler(void)
1248{
1249}
1250
1251static irqreturn_t fusb300_irq(int irq, void *_fusb300)
1252{
1253 struct fusb300 *fusb300 = _fusb300;
1254 u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
1255 u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
1256 u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
1257 u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
1258 struct usb_ctrlrequest ctrl;
1259 u8 in;
1260 u32 reg;
1261 int i;
1262
1263 spin_lock(&fusb300->lock);
1264
1265 int_grp1 &= int_grp1_en;
1266 int_grp0 &= int_grp0_en;
1267
1268 if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
1269 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1270 FUSB300_IGR1_WARM_RST_INT);
1271 printk(KERN_INFO"fusb300_warmreset\n");
1272 fusb300_reset();
1273 }
1274
1275 if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
1276 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1277 FUSB300_IGR1_HOT_RST_INT);
1278 printk(KERN_INFO"fusb300_hotreset\n");
1279 fusb300_reset();
1280 }
1281
1282 if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
1283 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1284 FUSB300_IGR1_USBRST_INT);
1285 fusb300_reset();
1286 }
1287 /* COMABT_INT has a highest priority */
1288
1289 if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
1290 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1291 FUSB300_IGR1_CX_COMABT_INT);
1292 printk(KERN_INFO"fusb300_ep0abt\n");
1293 }
1294
1295 if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
1296 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1297 FUSB300_IGR1_VBUS_CHG_INT);
1298 printk(KERN_INFO"fusb300_vbus_change\n");
1299 }
1300
1301 if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
1302 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1303 FUSB300_IGR1_U3_EXIT_FAIL_INT);
1304 }
1305
1306 if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
1307 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1308 FUSB300_IGR1_U2_EXIT_FAIL_INT);
1309 }
1310
1311 if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
1312 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1313 FUSB300_IGR1_U1_EXIT_FAIL_INT);
1314 }
1315
1316 if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
1317 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1318 FUSB300_IGR1_U2_ENTRY_FAIL_INT);
1319 }
1320
1321 if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
1322 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1323 FUSB300_IGR1_U1_ENTRY_FAIL_INT);
1324 }
1325
1326 if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
1327 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1328 FUSB300_IGR1_U3_EXIT_INT);
1329 printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
1330 }
1331
1332 if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
1333 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1334 FUSB300_IGR1_U2_EXIT_INT);
1335 printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
1336 }
1337
1338 if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
1339 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1340 FUSB300_IGR1_U1_EXIT_INT);
1341 printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
1342 }
1343
1344 if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
1345 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1346 FUSB300_IGR1_U3_ENTRY_INT);
1347 printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
1348 fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
1349 FUSB300_SSCR1_GO_U3_DONE);
1350 }
1351
1352 if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
1353 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1354 FUSB300_IGR1_U2_ENTRY_INT);
1355 printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
1356 }
1357
1358 if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
1359 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1360 FUSB300_IGR1_U1_ENTRY_INT);
1361 printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
1362 }
1363
1364 if (int_grp1 & FUSB300_IGR1_RESM_INT) {
1365 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1366 FUSB300_IGR1_RESM_INT);
1367 printk(KERN_INFO "fusb300_resume\n");
1368 }
1369
1370 if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
1371 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1372 FUSB300_IGR1_SUSP_INT);
1373 printk(KERN_INFO "fusb300_suspend\n");
1374 }
1375
1376 if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
1377 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1378 FUSB300_IGR1_HS_LPM_INT);
1379 printk(KERN_INFO "fusb300_HS_LPM_INT\n");
1380 }
1381
1382 if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
1383 fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
1384 FUSB300_IGR1_DEV_MODE_CHG_INT);
1385 check_device_mode(fusb300);
1386 }
1387
1388 if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
1389 fusb300_set_cxstall(fusb300);
1390 printk(KERN_INFO "fusb300_ep0fail\n");
1391 }
1392
1393 if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
1394 printk(KERN_INFO "fusb300_ep0setup\n");
1395 if (setup_packet(fusb300, &ctrl)) {
1396 spin_unlock(&fusb300->lock);
1397 if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
1398 fusb300_set_cxstall(fusb300);
1399 spin_lock(&fusb300->lock);
1400 }
1401 }
1402
1403 if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
1404 printk(KERN_INFO "fusb300_cmdend\n");
1405
1406
1407 if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
1408 printk(KERN_INFO "fusb300_cxout\n");
1409 fusb300_ep0out(fusb300);
1410 }
1411
1412 if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
1413 printk(KERN_INFO "fusb300_cxin\n");
1414 fusb300_ep0in(fusb300);
1415 }
1416
1417 if (int_grp1 & FUSB300_IGR1_INTGRP5)
1418 fusb300_grp5_handler();
1419
1420 if (int_grp1 & FUSB300_IGR1_INTGRP4)
1421 fusb300_grp4_handler();
1422
1423 if (int_grp1 & FUSB300_IGR1_INTGRP3)
1424 fusb300_grp3_handler();
1425
1426 if (int_grp1 & FUSB300_IGR1_INTGRP2)
1427 fusb300_grp2_handler();
1428
1429 if (int_grp0) {
1430 for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
1431 if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
1432 reg = ioread32(fusb300->reg +
1433 FUSB300_OFFSET_EPSET1(i));
1434 in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
1435 if (in)
1436 in_ep_fifo_handler(fusb300->ep[i]);
1437 else
1438 out_ep_fifo_handler(fusb300->ep[i]);
1439 }
1440 }
1441 }
1442
1443 spin_unlock(&fusb300->lock);
1444
1445 return IRQ_HANDLED;
1446}
1447
1448static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
1449 u32 time)
1450{
1451 u32 reg;
1452
1453 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
1454 reg &= ~0xff;
1455 reg |= FUSB300_SSCR2_U2TIMEOUT(time);
1456
1457 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
1458}
1459
1460static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
1461 u32 time)
1462{
1463 u32 reg;
1464
1465 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
1466 reg &= ~(0xff << 8);
1467 reg |= FUSB300_SSCR2_U1TIMEOUT(time);
1468
1469 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
1470}
1471
1472static void init_controller(struct fusb300 *fusb300)
1473{
1474 u32 reg;
1475 u32 mask = 0;
1476 u32 val = 0;
1477
1478 /* split on */
1479 mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
1480 reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
1481 reg &= ~mask;
1482 reg |= val;
1483 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
1484
1485 /* enable high-speed LPM */
1486 mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
1487 reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
1488 reg &= ~mask;
1489 reg |= val;
1490 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
1491
1492 /*set u1 u2 timmer*/
1493 fusb300_set_u2_timeout(fusb300, 0xff);
1494 fusb300_set_u1_timeout(fusb300, 0xff);
1495
1496 /* enable all grp1 interrupt */
1497 iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
1498}
1499/*------------------------------------------------------------------------*/
1500static struct fusb300 *the_controller;
1501
1502int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1503 int (*bind)(struct usb_gadget *))
1504{
1505 struct fusb300 *fusb300 = the_controller;
1506 int retval;
1507
1508 if (!driver
1509 || driver->speed < USB_SPEED_FULL
1510 || !bind
1511 || !driver->setup)
1512 return -EINVAL;
1513
1514 if (!fusb300)
1515 return -ENODEV;
1516
1517 if (fusb300->driver)
1518 return -EBUSY;
1519
1520 /* hook up the driver */
1521 driver->driver.bus = NULL;
1522 fusb300->driver = driver;
1523 fusb300->gadget.dev.driver = &driver->driver;
1524
1525 retval = device_add(&fusb300->gadget.dev);
1526 if (retval) {
1527 pr_err("device_add error (%d)\n", retval);
1528 goto error;
1529 }
1530
1531 retval = bind(&fusb300->gadget);
1532 if (retval) {
1533 pr_err("bind to driver error (%d)\n", retval);
1534 device_del(&fusb300->gadget.dev);
1535 goto error;
1536 }
1537
1538 return 0;
1539
1540error:
1541 fusb300->driver = NULL;
1542 fusb300->gadget.dev.driver = NULL;
1543
1544 return retval;
1545}
1546EXPORT_SYMBOL(usb_gadget_probe_driver);
1547
1548int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1549{
1550 struct fusb300 *fusb300 = the_controller;
1551
1552 if (driver != fusb300->driver || !driver->unbind)
1553 return -EINVAL;
1554
1555 driver->unbind(&fusb300->gadget);
1556 fusb300->gadget.dev.driver = NULL;
1557
1558 init_controller(fusb300);
1559 device_del(&fusb300->gadget.dev);
1560 fusb300->driver = NULL;
1561
1562 return 0;
1563}
1564EXPORT_SYMBOL(usb_gadget_unregister_driver);
1565/*--------------------------------------------------------------------------*/
1566
1567static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
1568{
1569 return 0;
1570}
1571
1572static struct usb_gadget_ops fusb300_gadget_ops = {
1573 .pullup = fusb300_udc_pullup,
1574};
1575
1576static int __exit fusb300_remove(struct platform_device *pdev)
1577{
1578 struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev);
1579
1580 iounmap(fusb300->reg);
1581 free_irq(platform_get_irq(pdev, 0), fusb300);
1582
1583 fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
1584 kfree(fusb300);
1585
1586 return 0;
1587}
1588
1589static int __init fusb300_probe(struct platform_device *pdev)
1590{
1591 struct resource *res, *ires, *ires1;
1592 void __iomem *reg = NULL;
1593 struct fusb300 *fusb300 = NULL;
1594 struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
1595 int ret = 0;
1596 int i;
1597
1598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1599 if (!res) {
1600 ret = -ENODEV;
1601 pr_err("platform_get_resource error.\n");
1602 goto clean_up;
1603 }
1604
1605 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1606 if (!ires) {
1607 ret = -ENODEV;
1608 dev_err(&pdev->dev,
1609 "platform_get_resource IORESOURCE_IRQ error.\n");
1610 goto clean_up;
1611 }
1612
1613 ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1614 if (!ires1) {
1615 ret = -ENODEV;
1616 dev_err(&pdev->dev,
1617 "platform_get_resource IORESOURCE_IRQ 1 error.\n");
1618 goto clean_up;
1619 }
1620
1621 reg = ioremap(res->start, resource_size(res));
1622 if (reg == NULL) {
1623 ret = -ENOMEM;
1624 pr_err("ioremap error.\n");
1625 goto clean_up;
1626 }
1627
1628 /* initialize udc */
1629 fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
1630 if (fusb300 == NULL) {
1631 pr_err("kzalloc error\n");
1632 goto clean_up;
1633 }
1634
1635 for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
1636 _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
1637 if (_ep[i] == NULL) {
1638 pr_err("_ep kzalloc error\n");
1639 goto clean_up;
1640 }
1641 fusb300->ep[i] = _ep[i];
1642 }
1643
1644 spin_lock_init(&fusb300->lock);
1645
1646 dev_set_drvdata(&pdev->dev, fusb300);
1647
1648 fusb300->gadget.ops = &fusb300_gadget_ops;
1649
1650 device_initialize(&fusb300->gadget.dev);
1651
1652 dev_set_name(&fusb300->gadget.dev, "gadget");
1653
1654 fusb300->gadget.is_dualspeed = 1;
1655 fusb300->gadget.dev.parent = &pdev->dev;
1656 fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
1657 fusb300->gadget.dev.release = pdev->dev.release;
1658 fusb300->gadget.name = udc_name;
1659 fusb300->reg = reg;
1660
1661 ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED,
1662 udc_name, fusb300);
1663 if (ret < 0) {
1664 pr_err("request_irq error (%d)\n", ret);
1665 goto clean_up;
1666 }
1667
1668 ret = request_irq(ires1->start, fusb300_irq,
1669 IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300);
1670 if (ret < 0) {
1671 pr_err("request_irq1 error (%d)\n", ret);
1672 goto clean_up;
1673 }
1674
1675 INIT_LIST_HEAD(&fusb300->gadget.ep_list);
1676
1677 for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
1678 struct fusb300_ep *ep = fusb300->ep[i];
1679
1680 if (i != 0) {
1681 INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
1682 list_add_tail(&fusb300->ep[i]->ep.ep_list,
1683 &fusb300->gadget.ep_list);
1684 }
1685 ep->fusb300 = fusb300;
1686 INIT_LIST_HEAD(&ep->queue);
1687 ep->ep.name = fusb300_ep_name[i];
1688 ep->ep.ops = &fusb300_ep_ops;
1689 ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE;
1690 }
1691 fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE;
1692 fusb300->ep[0]->epnum = 0;
1693 fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
1694 INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
1695
1696 the_controller = fusb300;
1697
1698 fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
1699 GFP_KERNEL);
1700 if (fusb300->ep0_req == NULL)
1701 goto clean_up3;
1702
1703 init_controller(fusb300);
1704 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1705
1706 return 0;
1707
1708clean_up3:
1709 free_irq(ires->start, fusb300);
1710
1711clean_up:
1712 if (fusb300) {
1713 if (fusb300->ep0_req)
1714 fusb300_free_request(&fusb300->ep[0]->ep,
1715 fusb300->ep0_req);
1716 kfree(fusb300);
1717 }
1718 if (reg)
1719 iounmap(reg);
1720
1721 return ret;
1722}
1723
1724static struct platform_driver fusb300_driver = {
1725 .remove = __exit_p(fusb300_remove),
1726 .driver = {
1727 .name = (char *) udc_name,
1728 .owner = THIS_MODULE,
1729 },
1730};
1731
1732static int __init fusb300_udc_init(void)
1733{
1734 return platform_driver_probe(&fusb300_driver, fusb300_probe);
1735}
1736
1737module_init(fusb300_udc_init);
1738
1739static void __exit fusb300_udc_cleanup(void)
1740{
1741 platform_driver_unregister(&fusb300_driver);
1742}
1743module_exit(fusb300_udc_cleanup);
diff --git a/drivers/usb/gadget/fusb300_udc.h b/drivers/usb/gadget/fusb300_udc.h
new file mode 100644
index 000000000000..f51aa2ef1f90
--- /dev/null
+++ b/drivers/usb/gadget/fusb300_udc.h
@@ -0,0 +1,687 @@
1/*
2 * Fusb300 UDC (USB gadget)
3 *
4 * Copyright (C) 2010 Faraday Technology Corp.
5 *
6 * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23
24#ifndef __FUSB300_UDC_H__
25#define __FUSB300_UDC_H_
26
27#include <linux/kernel.h>
28
29#define FUSB300_OFFSET_GCR 0x00
30#define FUSB300_OFFSET_GTM 0x04
31#define FUSB300_OFFSET_DAR 0x08
32#define FUSB300_OFFSET_CSR 0x0C
33#define FUSB300_OFFSET_CXPORT 0x10
34#define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30)
35#define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30)
36#define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30)
37#define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30)
38#define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30)
39#define FUSB300_OFFSET_HSPTM 0x300
40#define FUSB300_OFFSET_HSCR 0x304
41#define FUSB300_OFFSET_SSCR0 0x308
42#define FUSB300_OFFSET_SSCR1 0x30C
43#define FUSB300_OFFSET_TT 0x310
44#define FUSB300_OFFSET_DEVNOTF 0x314
45#define FUSB300_OFFSET_DNC1 0x318
46#define FUSB300_OFFSET_CS 0x31C
47#define FUSB300_OFFSET_SOF 0x324
48#define FUSB300_OFFSET_EFCS 0x328
49#define FUSB300_OFFSET_IGR0 0x400
50#define FUSB300_OFFSET_IGR1 0x404
51#define FUSB300_OFFSET_IGR2 0x408
52#define FUSB300_OFFSET_IGR3 0x40C
53#define FUSB300_OFFSET_IGR4 0x410
54#define FUSB300_OFFSET_IGR5 0x414
55#define FUSB300_OFFSET_IGER0 0x420
56#define FUSB300_OFFSET_IGER1 0x424
57#define FUSB300_OFFSET_IGER2 0x428
58#define FUSB300_OFFSET_IGER3 0x42C
59#define FUSB300_OFFSET_IGER4 0x430
60#define FUSB300_OFFSET_IGER5 0x434
61#define FUSB300_OFFSET_DMAHMER 0x500
62#define FUSB300_OFFSET_EPPRDRDY 0x504
63#define FUSB300_OFFSET_DMAEPMR 0x508
64#define FUSB300_OFFSET_DMAENR 0x50C
65#define FUSB300_OFFSET_DMAAPR 0x510
66#define FUSB300_OFFSET_AHBCR 0x514
67#define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10)
68#define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10)
69#define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10)
70#define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10)
71#define FUSB300_OFFSET_BUFDBG_START 0x800
72#define FUSB300_OFFSET_BUFDBG_END 0xBFC
73#define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10)
74
75/*
76 * * Global Control Register (offset = 000H)
77 * */
78#define FUSB300_GCR_SF_RST (1 << 8)
79#define FUSB300_GCR_VBUS_STATUS (1 << 7)
80#define FUSB300_GCR_FORCE_HS_SUSP (1 << 6)
81#define FUSB300_GCR_SYNC_FIFO1_CLR (1 << 5)
82#define FUSB300_GCR_SYNC_FIFO0_CLR (1 << 4)
83#define FUSB300_GCR_FIFOCLR (1 << 3)
84#define FUSB300_GCR_GLINTEN (1 << 2)
85#define FUSB300_GCR_DEVEN_FS 0x3
86#define FUSB300_GCR_DEVEN_HS 0x2
87#define FUSB300_GCR_DEVEN_SS 0x1
88#define FUSB300_GCR_DEVDIS 0x0
89#define FUSB300_GCR_DEVEN_MSK 0x3
90
91
92/*
93 * *Global Test Mode (offset = 004H)
94 * */
95#define FUSB300_GTM_TST_DIS_SOFGEN (1 << 16)
96#define FUSB300_GTM_TST_CUR_EP_ENTRY(n) ((n & 0xF) << 12)
97#define FUSB300_GTM_TST_EP_ENTRY(n) ((n & 0xF) << 8)
98#define FUSB300_GTM_TST_EP_NUM(n) ((n & 0xF) << 4)
99#define FUSB300_GTM_TST_FIFO_DEG (1 << 1)
100#define FUSB300_GTM_TSTMODE (1 << 0)
101
102/*
103 * * Device Address Register (offset = 008H)
104 * */
105#define FUSB300_DAR_SETCONFG (1 << 7)
106#define FUSB300_DAR_DRVADDR(x) (x & 0x7F)
107#define FUSB300_DAR_DRVADDR_MSK 0x7F
108
109/*
110 * *Control Transfer Configuration and Status Register
111 * (CX_Config_Status, offset = 00CH)
112 * */
113#define FUSB300_CSR_LEN(x) ((x & 0xFFFF) << 8)
114#define FUSB300_CSR_LEN_MSK (0xFFFF << 8)
115#define FUSB300_CSR_EMP (1 << 4)
116#define FUSB300_CSR_FUL (1 << 3)
117#define FUSB300_CSR_CLR (1 << 2)
118#define FUSB300_CSR_STL (1 << 1)
119#define FUSB300_CSR_DONE (1 << 0)
120
121/*
122 * * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 )
123 * */
124#define FUSB300_EPSET0_CLRSEQNUM (1 << 2)
125#define FUSB300_EPSET0_EPn_TX0BYTE (1 << 1)
126#define FUSB300_EPSET0_STL (1 << 0)
127
128/*
129 * * EPn Setting 1 (EPn_SET1, offset = 024H+(n-1)*30H, n=1~15)
130 * */
131#define FUSB300_EPSET1_START_ENTRY(x) ((x & 0xFF) << 24)
132#define FUSB300_EPSET1_START_ENTRY_MSK (0xFF << 24)
133#define FUSB300_EPSET1_FIFOENTRY(x) ((x & 0x1F) << 12)
134#define FUSB300_EPSET1_FIFOENTRY_MSK (0x1f << 12)
135#define FUSB300_EPSET1_INTERVAL(x) ((x & 0x7) << 6)
136#define FUSB300_EPSET1_BWNUM(x) ((x & 0x3) << 4)
137#define FUSB300_EPSET1_TYPEISO (1 << 2)
138#define FUSB300_EPSET1_TYPEBLK (2 << 2)
139#define FUSB300_EPSET1_TYPEINT (3 << 2)
140#define FUSB300_EPSET1_TYPE(x) ((x & 0x3) << 2)
141#define FUSB300_EPSET1_TYPE_MSK (0x3 << 2)
142#define FUSB300_EPSET1_DIROUT (0 << 1)
143#define FUSB300_EPSET1_DIRIN (1 << 1)
144#define FUSB300_EPSET1_DIR(x) ((x & 0x1) << 1)
145#define FUSB300_EPSET1_DIRIN (1 << 1)
146#define FUSB300_EPSET1_DIR_MSK ((0x1) << 1)
147#define FUSB300_EPSET1_ACTDIS 0
148#define FUSB300_EPSET1_ACTEN 1
149
150/*
151 * *EPn Setting 2 (EPn_SET2, offset = 028H+(n-1)*30H, n=1~15)
152 * */
153#define FUSB300_EPSET2_ADDROFS(x) ((x & 0x7FFF) << 16)
154#define FUSB300_EPSET2_ADDROFS_MSK (0x7fff << 16)
155#define FUSB300_EPSET2_MPS(x) (x & 0x7FF)
156#define FUSB300_EPSET2_MPS_MSK 0x7FF
157
158/*
159 * * EPn FIFO Register (offset = 2cH+(n-1)*30H)
160 * */
161#define FUSB300_FFR_RST (1 << 31)
162#define FUSB300_FF_FUL (1 << 30)
163#define FUSB300_FF_EMPTY (1 << 29)
164#define FUSB300_FFR_BYCNT 0x1FFFF
165
166/*
167 * *EPn Stream ID (EPn_STR_ID, offset = 040H+(n-1)*30H, n=1~15)
168 * */
169#define FUSB300_STRID_STREN (1 << 16)
170#define FUSB300_STRID_STRID(x) (x & 0xFFFF)
171
172/*
173 * *HS PHY Test Mode (offset = 300H)
174 * */
175#define FUSB300_HSPTM_TSTPKDONE (1 << 4)
176#define FUSB300_HSPTM_TSTPKT (1 << 3)
177#define FUSB300_HSPTM_TSTSET0NAK (1 << 2)
178#define FUSB300_HSPTM_TSTKSTA (1 << 1)
179#define FUSB300_HSPTM_TSTJSTA (1 << 0)
180
181/*
182 * *HS Control Register (offset = 304H)
183 * */
184#define FUSB300_HSCR_HS_LPM_PERMIT (1 << 8)
185#define FUSB300_HSCR_HS_LPM_RMWKUP (1 << 7)
186#define FUSB300_HSCR_CAP_LPM_RMWKUP (1 << 6)
187#define FUSB300_HSCR_HS_GOSUSP (1 << 5)
188#define FUSB300_HSCR_HS_GORMWKU (1 << 4)
189#define FUSB300_HSCR_CAP_RMWKUP (1 << 3)
190#define FUSB300_HSCR_IDLECNT_0MS 0
191#define FUSB300_HSCR_IDLECNT_1MS 1
192#define FUSB300_HSCR_IDLECNT_2MS 2
193#define FUSB300_HSCR_IDLECNT_3MS 3
194#define FUSB300_HSCR_IDLECNT_4MS 4
195#define FUSB300_HSCR_IDLECNT_5MS 5
196#define FUSB300_HSCR_IDLECNT_6MS 6
197#define FUSB300_HSCR_IDLECNT_7MS 7
198
199/*
200 * * SS Controller Register 0 (offset = 308H)
201 * */
202#define FUSB300_SSCR0_MAX_INTERVAL(x) ((x & 0x7) << 4)
203#define FUSB300_SSCR0_U2_FUN_EN (1 << 1)
204#define FUSB300_SSCR0_U1_FUN_EN (1 << 0)
205
206/*
207 * * SS Controller Register 1 (offset = 30CH)
208 * */
209#define FUSB300_SSCR1_GO_U3_DONE (1 << 8)
210#define FUSB300_SSCR1_TXDEEMPH_LEVEL (1 << 7)
211#define FUSB300_SSCR1_DIS_SCRMB (1 << 6)
212#define FUSB300_SSCR1_FORCE_RECOVERY (1 << 5)
213#define FUSB300_SSCR1_U3_WAKEUP_EN (1 << 4)
214#define FUSB300_SSCR1_U2_EXIT_EN (1 << 3)
215#define FUSB300_SSCR1_U1_EXIT_EN (1 << 2)
216#define FUSB300_SSCR1_U2_ENTRY_EN (1 << 1)
217#define FUSB300_SSCR1_U1_ENTRY_EN (1 << 0)
218
219/*
220 * *SS Controller Register 2 (offset = 310H)
221 * */
222#define FUSB300_SSCR2_SS_TX_SWING (1 << 25)
223#define FUSB300_SSCR2_FORCE_LINKPM_ACCEPT (1 << 24)
224#define FUSB300_SSCR2_U2_INACT_TIMEOUT(x) ((x & 0xFF) << 16)
225#define FUSB300_SSCR2_U1TIMEOUT(x) ((x & 0xFF) << 8)
226#define FUSB300_SSCR2_U2TIMEOUT(x) (x & 0xFF)
227
228/*
229 * *SS Device Notification Control (DEV_NOTF, offset = 314H)
230 * */
231#define FUSB300_DEVNOTF_CONTEXT0(x) ((x & 0xFFFFFF) << 8)
232#define FUSB300_DEVNOTF_TYPE_DIS 0
233#define FUSB300_DEVNOTF_TYPE_FUNCWAKE 1
234#define FUSB300_DEVNOTF_TYPE_LTM 2
235#define FUSB300_DEVNOTF_TYPE_BUSINT_ADJMSG 3
236
237/*
238 * *BFM Arbiter Priority Register (BFM_ARB offset = 31CH)
239 * */
240#define FUSB300_BFMARB_ARB_M1 (1 << 3)
241#define FUSB300_BFMARB_ARB_M0 (1 << 2)
242#define FUSB300_BFMARB_ARB_S1 (1 << 1)
243#define FUSB300_BFMARB_ARB_S0 1
244
245/*
246 * *Vendor Specific IO Control Register (offset = 320H)
247 * */
248#define FUSB300_VSIC_VCTLOAD_N (1 << 8)
249#define FUSB300_VSIC_VCTL(x) (x & 0x3F)
250
251/*
252 * *SOF Mask Timer (offset = 324H)
253 * */
254#define FUSB300_SOF_MASK_TIMER_HS 0x044c
255#define FUSB300_SOF_MASK_TIMER_FS 0x2710
256
257/*
258 * *Error Flag and Control Status (offset = 328H)
259 * */
260#define FUSB300_EFCS_PM_STATE_U3 3
261#define FUSB300_EFCS_PM_STATE_U2 2
262#define FUSB300_EFCS_PM_STATE_U1 1
263#define FUSB300_EFCS_PM_STATE_U0 0
264
265/*
266 * *Interrupt Group 0 Register (offset = 400H)
267 * */
268#define FUSB300_IGR0_EP15_PRD_INT (1 << 31)
269#define FUSB300_IGR0_EP14_PRD_INT (1 << 30)
270#define FUSB300_IGR0_EP13_PRD_INT (1 << 29)
271#define FUSB300_IGR0_EP12_PRD_INT (1 << 28)
272#define FUSB300_IGR0_EP11_PRD_INT (1 << 27)
273#define FUSB300_IGR0_EP10_PRD_INT (1 << 26)
274#define FUSB300_IGR0_EP9_PRD_INT (1 << 25)
275#define FUSB300_IGR0_EP8_PRD_INT (1 << 24)
276#define FUSB300_IGR0_EP7_PRD_INT (1 << 23)
277#define FUSB300_IGR0_EP6_PRD_INT (1 << 22)
278#define FUSB300_IGR0_EP5_PRD_INT (1 << 21)
279#define FUSB300_IGR0_EP4_PRD_INT (1 << 20)
280#define FUSB300_IGR0_EP3_PRD_INT (1 << 19)
281#define FUSB300_IGR0_EP2_PRD_INT (1 << 18)
282#define FUSB300_IGR0_EP1_PRD_INT (1 << 17)
283#define FUSB300_IGR0_EPn_PRD_INT(n) (1 << (n + 16))
284
285#define FUSB300_IGR0_EP15_FIFO_INT (1 << 15)
286#define FUSB300_IGR0_EP14_FIFO_INT (1 << 14)
287#define FUSB300_IGR0_EP13_FIFO_INT (1 << 13)
288#define FUSB300_IGR0_EP12_FIFO_INT (1 << 12)
289#define FUSB300_IGR0_EP11_FIFO_INT (1 << 11)
290#define FUSB300_IGR0_EP10_FIFO_INT (1 << 10)
291#define FUSB300_IGR0_EP9_FIFO_INT (1 << 9)
292#define FUSB300_IGR0_EP8_FIFO_INT (1 << 8)
293#define FUSB300_IGR0_EP7_FIFO_INT (1 << 7)
294#define FUSB300_IGR0_EP6_FIFO_INT (1 << 6)
295#define FUSB300_IGR0_EP5_FIFO_INT (1 << 5)
296#define FUSB300_IGR0_EP4_FIFO_INT (1 << 4)
297#define FUSB300_IGR0_EP3_FIFO_INT (1 << 3)
298#define FUSB300_IGR0_EP2_FIFO_INT (1 << 2)
299#define FUSB300_IGR0_EP1_FIFO_INT (1 << 1)
300#define FUSB300_IGR0_EPn_FIFO_INT(n) (1 << n)
301
302/*
303 * *Interrupt Group 1 Register (offset = 404H)
304 * */
305#define FUSB300_IGR1_INTGRP5 (1 << 31)
306#define FUSB300_IGR1_VBUS_CHG_INT (1 << 30)
307#define FUSB300_IGR1_SYNF1_EMPTY_INT (1 << 29)
308#define FUSB300_IGR1_SYNF0_EMPTY_INT (1 << 28)
309#define FUSB300_IGR1_U3_EXIT_FAIL_INT (1 << 27)
310#define FUSB300_IGR1_U2_EXIT_FAIL_INT (1 << 26)
311#define FUSB300_IGR1_U1_EXIT_FAIL_INT (1 << 25)
312#define FUSB300_IGR1_U2_ENTRY_FAIL_INT (1 << 24)
313#define FUSB300_IGR1_U1_ENTRY_FAIL_INT (1 << 23)
314#define FUSB300_IGR1_U3_EXIT_INT (1 << 22)
315#define FUSB300_IGR1_U2_EXIT_INT (1 << 21)
316#define FUSB300_IGR1_U1_EXIT_INT (1 << 20)
317#define FUSB300_IGR1_U3_ENTRY_INT (1 << 19)
318#define FUSB300_IGR1_U2_ENTRY_INT (1 << 18)
319#define FUSB300_IGR1_U1_ENTRY_INT (1 << 17)
320#define FUSB300_IGR1_HOT_RST_INT (1 << 16)
321#define FUSB300_IGR1_WARM_RST_INT (1 << 15)
322#define FUSB300_IGR1_RESM_INT (1 << 14)
323#define FUSB300_IGR1_SUSP_INT (1 << 13)
324#define FUSB300_IGR1_HS_LPM_INT (1 << 12)
325#define FUSB300_IGR1_USBRST_INT (1 << 11)
326#define FUSB300_IGR1_DEV_MODE_CHG_INT (1 << 9)
327#define FUSB300_IGR1_CX_COMABT_INT (1 << 8)
328#define FUSB300_IGR1_CX_COMFAIL_INT (1 << 7)
329#define FUSB300_IGR1_CX_CMDEND_INT (1 << 6)
330#define FUSB300_IGR1_CX_OUT_INT (1 << 5)
331#define FUSB300_IGR1_CX_IN_INT (1 << 4)
332#define FUSB300_IGR1_CX_SETUP_INT (1 << 3)
333#define FUSB300_IGR1_INTGRP4 (1 << 2)
334#define FUSB300_IGR1_INTGRP3 (1 << 1)
335#define FUSB300_IGR1_INTGRP2 (1 << 0)
336
337/*
338 * *Interrupt Group 2 Register (offset = 408H)
339 * */
340#define FUSB300_IGR2_EP6_STR_ACCEPT_INT (1 << 29)
341#define FUSB300_IGR2_EP6_STR_RESUME_INT (1 << 28)
342#define FUSB300_IGR2_EP6_STR_REQ_INT (1 << 27)
343#define FUSB300_IGR2_EP6_STR_NOTRDY_INT (1 << 26)
344#define FUSB300_IGR2_EP6_STR_PRIME_INT (1 << 25)
345#define FUSB300_IGR2_EP5_STR_ACCEPT_INT (1 << 24)
346#define FUSB300_IGR2_EP5_STR_RESUME_INT (1 << 23)
347#define FUSB300_IGR2_EP5_STR_REQ_INT (1 << 22)
348#define FUSB300_IGR2_EP5_STR_NOTRDY_INT (1 << 21)
349#define FUSB300_IGR2_EP5_STR_PRIME_INT (1 << 20)
350#define FUSB300_IGR2_EP4_STR_ACCEPT_INT (1 << 19)
351#define FUSB300_IGR2_EP4_STR_RESUME_INT (1 << 18)
352#define FUSB300_IGR2_EP4_STR_REQ_INT (1 << 17)
353#define FUSB300_IGR2_EP4_STR_NOTRDY_INT (1 << 16)
354#define FUSB300_IGR2_EP4_STR_PRIME_INT (1 << 15)
355#define FUSB300_IGR2_EP3_STR_ACCEPT_INT (1 << 14)
356#define FUSB300_IGR2_EP3_STR_RESUME_INT (1 << 13)
357#define FUSB300_IGR2_EP3_STR_REQ_INT (1 << 12)
358#define FUSB300_IGR2_EP3_STR_NOTRDY_INT (1 << 11)
359#define FUSB300_IGR2_EP3_STR_PRIME_INT (1 << 10)
360#define FUSB300_IGR2_EP2_STR_ACCEPT_INT (1 << 9)
361#define FUSB300_IGR2_EP2_STR_RESUME_INT (1 << 8)
362#define FUSB300_IGR2_EP2_STR_REQ_INT (1 << 7)
363#define FUSB300_IGR2_EP2_STR_NOTRDY_INT (1 << 6)
364#define FUSB300_IGR2_EP2_STR_PRIME_INT (1 << 5)
365#define FUSB300_IGR2_EP1_STR_ACCEPT_INT (1 << 4)
366#define FUSB300_IGR2_EP1_STR_RESUME_INT (1 << 3)
367#define FUSB300_IGR2_EP1_STR_REQ_INT (1 << 2)
368#define FUSB300_IGR2_EP1_STR_NOTRDY_INT (1 << 1)
369#define FUSB300_IGR2_EP1_STR_PRIME_INT (1 << 0)
370
371#define FUSB300_IGR2_EP_STR_ACCEPT_INT(n) (1 << (5 * n - 1))
372#define FUSB300_IGR2_EP_STR_RESUME_INT(n) (1 << (5 * n - 2))
373#define FUSB300_IGR2_EP_STR_REQ_INT(n) (1 << (5 * n - 3))
374#define FUSB300_IGR2_EP_STR_NOTRDY_INT(n) (1 << (5 * n - 4))
375#define FUSB300_IGR2_EP_STR_PRIME_INT(n) (1 << (5 * n - 5))
376
377/*
378 * *Interrupt Group 3 Register (offset = 40CH)
379 * */
380#define FUSB300_IGR3_EP12_STR_ACCEPT_INT (1 << 29)
381#define FUSB300_IGR3_EP12_STR_RESUME_INT (1 << 28)
382#define FUSB300_IGR3_EP12_STR_REQ_INT (1 << 27)
383#define FUSB300_IGR3_EP12_STR_NOTRDY_INT (1 << 26)
384#define FUSB300_IGR3_EP12_STR_PRIME_INT (1 << 25)
385#define FUSB300_IGR3_EP11_STR_ACCEPT_INT (1 << 24)
386#define FUSB300_IGR3_EP11_STR_RESUME_INT (1 << 23)
387#define FUSB300_IGR3_EP11_STR_REQ_INT (1 << 22)
388#define FUSB300_IGR3_EP11_STR_NOTRDY_INT (1 << 21)
389#define FUSB300_IGR3_EP11_STR_PRIME_INT (1 << 20)
390#define FUSB300_IGR3_EP10_STR_ACCEPT_INT (1 << 19)
391#define FUSB300_IGR3_EP10_STR_RESUME_INT (1 << 18)
392#define FUSB300_IGR3_EP10_STR_REQ_INT (1 << 17)
393#define FUSB300_IGR3_EP10_STR_NOTRDY_INT (1 << 16)
394#define FUSB300_IGR3_EP10_STR_PRIME_INT (1 << 15)
395#define FUSB300_IGR3_EP9_STR_ACCEPT_INT (1 << 14)
396#define FUSB300_IGR3_EP9_STR_RESUME_INT (1 << 13)
397#define FUSB300_IGR3_EP9_STR_REQ_INT (1 << 12)
398#define FUSB300_IGR3_EP9_STR_NOTRDY_INT (1 << 11)
399#define FUSB300_IGR3_EP9_STR_PRIME_INT (1 << 10)
400#define FUSB300_IGR3_EP8_STR_ACCEPT_INT (1 << 9)
401#define FUSB300_IGR3_EP8_STR_RESUME_INT (1 << 8)
402#define FUSB300_IGR3_EP8_STR_REQ_INT (1 << 7)
403#define FUSB300_IGR3_EP8_STR_NOTRDY_INT (1 << 6)
404#define FUSB300_IGR3_EP8_STR_PRIME_INT (1 << 5)
405#define FUSB300_IGR3_EP7_STR_ACCEPT_INT (1 << 4)
406#define FUSB300_IGR3_EP7_STR_RESUME_INT (1 << 3)
407#define FUSB300_IGR3_EP7_STR_REQ_INT (1 << 2)
408#define FUSB300_IGR3_EP7_STR_NOTRDY_INT (1 << 1)
409#define FUSB300_IGR3_EP7_STR_PRIME_INT (1 << 0)
410
411#define FUSB300_IGR3_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
412#define FUSB300_IGR3_EP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
413#define FUSB300_IGR3_EP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
414#define FUSB300_IGR3_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
415#define FUSB300_IGR3_EP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
416
417/*
418 * *Interrupt Group 4 Register (offset = 410H)
419 * */
420#define FUSB300_IGR4_EP15_RX0_INT (1 << 31)
421#define FUSB300_IGR4_EP14_RX0_INT (1 << 30)
422#define FUSB300_IGR4_EP13_RX0_INT (1 << 29)
423#define FUSB300_IGR4_EP12_RX0_INT (1 << 28)
424#define FUSB300_IGR4_EP11_RX0_INT (1 << 27)
425#define FUSB300_IGR4_EP10_RX0_INT (1 << 26)
426#define FUSB300_IGR4_EP9_RX0_INT (1 << 25)
427#define FUSB300_IGR4_EP8_RX0_INT (1 << 24)
428#define FUSB300_IGR4_EP7_RX0_INT (1 << 23)
429#define FUSB300_IGR4_EP6_RX0_INT (1 << 22)
430#define FUSB300_IGR4_EP5_RX0_INT (1 << 21)
431#define FUSB300_IGR4_EP4_RX0_INT (1 << 20)
432#define FUSB300_IGR4_EP3_RX0_INT (1 << 19)
433#define FUSB300_IGR4_EP2_RX0_INT (1 << 18)
434#define FUSB300_IGR4_EP1_RX0_INT (1 << 17)
435#define FUSB300_IGR4_EP_RX0_INT(x) (1 << (x + 16))
436#define FUSB300_IGR4_EP15_STR_ACCEPT_INT (1 << 14)
437#define FUSB300_IGR4_EP15_STR_RESUME_INT (1 << 13)
438#define FUSB300_IGR4_EP15_STR_REQ_INT (1 << 12)
439#define FUSB300_IGR4_EP15_STR_NOTRDY_INT (1 << 11)
440#define FUSB300_IGR4_EP15_STR_PRIME_INT (1 << 10)
441#define FUSB300_IGR4_EP14_STR_ACCEPT_INT (1 << 9)
442#define FUSB300_IGR4_EP14_STR_RESUME_INT (1 << 8)
443#define FUSB300_IGR4_EP14_STR_REQ_INT (1 << 7)
444#define FUSB300_IGR4_EP14_STR_NOTRDY_INT (1 << 6)
445#define FUSB300_IGR4_EP14_STR_PRIME_INT (1 << 5)
446#define FUSB300_IGR4_EP13_STR_ACCEPT_INT (1 << 4)
447#define FUSB300_IGR4_EP13_STR_RESUME_INT (1 << 3)
448#define FUSB300_IGR4_EP13_STR_REQ_INT (1 << 2)
449#define FUSB300_IGR4_EP13_STR_NOTRDY_INT (1 << 1)
450#define FUSB300_IGR4_EP13_STR_PRIME_INT (1 << 0)
451
452#define FUSB300_IGR4_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 12) - 1))
453#define FUSB300_IGR4_EP_STR_RESUME_INT(n) (1 << (5 * (n - 12) - 2))
454#define FUSB300_IGR4_EP_STR_REQ_INT(n) (1 << (5 * (n - 12) - 3))
455#define FUSB300_IGR4_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 12) - 4))
456#define FUSB300_IGR4_EP_STR_PRIME_INT(n) (1 << (5 * (n - 12) - 5))
457
458/*
459 * *Interrupt Group 5 Register (offset = 414H)
460 * */
461#define FUSB300_IGR5_EP_STL_INT(n) (1 << n)
462
463/*
464 * *Interrupt Enable Group 0 Register (offset = 420H)
465 * */
466#define FUSB300_IGER0_EEP15_PRD_INT (1 << 31)
467#define FUSB300_IGER0_EEP14_PRD_INT (1 << 30)
468#define FUSB300_IGER0_EEP13_PRD_INT (1 << 29)
469#define FUSB300_IGER0_EEP12_PRD_INT (1 << 28)
470#define FUSB300_IGER0_EEP11_PRD_INT (1 << 27)
471#define FUSB300_IGER0_EEP10_PRD_INT (1 << 26)
472#define FUSB300_IGER0_EEP9_PRD_INT (1 << 25)
473#define FUSB300_IGER0_EP8_PRD_INT (1 << 24)
474#define FUSB300_IGER0_EEP7_PRD_INT (1 << 23)
475#define FUSB300_IGER0_EEP6_PRD_INT (1 << 22)
476#define FUSB300_IGER0_EEP5_PRD_INT (1 << 21)
477#define FUSB300_IGER0_EEP4_PRD_INT (1 << 20)
478#define FUSB300_IGER0_EEP3_PRD_INT (1 << 19)
479#define FUSB300_IGER0_EEP2_PRD_INT (1 << 18)
480#define FUSB300_IGER0_EEP1_PRD_INT (1 << 17)
481#define FUSB300_IGER0_EEPn_PRD_INT(n) (1 << (n + 16))
482
483#define FUSB300_IGER0_EEP15_FIFO_INT (1 << 15)
484#define FUSB300_IGER0_EEP14_FIFO_INT (1 << 14)
485#define FUSB300_IGER0_EEP13_FIFO_INT (1 << 13)
486#define FUSB300_IGER0_EEP12_FIFO_INT (1 << 12)
487#define FUSB300_IGER0_EEP11_FIFO_INT (1 << 11)
488#define FUSB300_IGER0_EEP10_FIFO_INT (1 << 10)
489#define FUSB300_IGER0_EEP9_FIFO_INT (1 << 9)
490#define FUSB300_IGER0_EEP8_FIFO_INT (1 << 8)
491#define FUSB300_IGER0_EEP7_FIFO_INT (1 << 7)
492#define FUSB300_IGER0_EEP6_FIFO_INT (1 << 6)
493#define FUSB300_IGER0_EEP5_FIFO_INT (1 << 5)
494#define FUSB300_IGER0_EEP4_FIFO_INT (1 << 4)
495#define FUSB300_IGER0_EEP3_FIFO_INT (1 << 3)
496#define FUSB300_IGER0_EEP2_FIFO_INT (1 << 2)
497#define FUSB300_IGER0_EEP1_FIFO_INT (1 << 1)
498#define FUSB300_IGER0_EEPn_FIFO_INT(n) (1 << n)
499
500/*
501 * *Interrupt Enable Group 1 Register (offset = 424H)
502 * */
503#define FUSB300_IGER1_EINT_GRP5 (1 << 31)
504#define FUSB300_IGER1_VBUS_CHG_INT (1 << 30)
505#define FUSB300_IGER1_SYNF1_EMPTY_INT (1 << 29)
506#define FUSB300_IGER1_SYNF0_EMPTY_INT (1 << 28)
507#define FUSB300_IGER1_U3_EXIT_FAIL_INT (1 << 27)
508#define FUSB300_IGER1_U2_EXIT_FAIL_INT (1 << 26)
509#define FUSB300_IGER1_U1_EXIT_FAIL_INT (1 << 25)
510#define FUSB300_IGER1_U2_ENTRY_FAIL_INT (1 << 24)
511#define FUSB300_IGER1_U1_ENTRY_FAIL_INT (1 << 23)
512#define FUSB300_IGER1_U3_EXIT_INT (1 << 22)
513#define FUSB300_IGER1_U2_EXIT_INT (1 << 21)
514#define FUSB300_IGER1_U1_EXIT_INT (1 << 20)
515#define FUSB300_IGER1_U3_ENTRY_INT (1 << 19)
516#define FUSB300_IGER1_U2_ENTRY_INT (1 << 18)
517#define FUSB300_IGER1_U1_ENTRY_INT (1 << 17)
518#define FUSB300_IGER1_HOT_RST_INT (1 << 16)
519#define FUSB300_IGER1_WARM_RST_INT (1 << 15)
520#define FUSB300_IGER1_RESM_INT (1 << 14)
521#define FUSB300_IGER1_SUSP_INT (1 << 13)
522#define FUSB300_IGER1_LPM_INT (1 << 12)
523#define FUSB300_IGER1_HS_RST_INT (1 << 11)
524#define FUSB300_IGER1_EDEV_MODE_CHG_INT (1 << 9)
525#define FUSB300_IGER1_CX_COMABT_INT (1 << 8)
526#define FUSB300_IGER1_CX_COMFAIL_INT (1 << 7)
527#define FUSB300_IGER1_CX_CMDEND_INT (1 << 6)
528#define FUSB300_IGER1_CX_OUT_INT (1 << 5)
529#define FUSB300_IGER1_CX_IN_INT (1 << 4)
530#define FUSB300_IGER1_CX_SETUP_INT (1 << 3)
531#define FUSB300_IGER1_INTGRP4 (1 << 2)
532#define FUSB300_IGER1_INTGRP3 (1 << 1)
533#define FUSB300_IGER1_INTGRP2 (1 << 0)
534
535/*
536 * *Interrupt Enable Group 2 Register (offset = 428H)
537 * */
538#define FUSB300_IGER2_EEP_STR_ACCEPT_INT(n) (1 << (5 * n - 1))
539#define FUSB300_IGER2_EEP_STR_RESUME_INT(n) (1 << (5 * n - 2))
540#define FUSB300_IGER2_EEP_STR_REQ_INT(n) (1 << (5 * n - 3))
541#define FUSB300_IGER2_EEP_STR_NOTRDY_INT(n) (1 << (5 * n - 4))
542#define FUSB300_IGER2_EEP_STR_PRIME_INT(n) (1 << (5 * n - 5))
543
544/*
545 * *Interrupt Enable Group 3 Register (offset = 42CH)
546 * */
547
548#define FUSB300_IGER3_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
549#define FUSB300_IGER3_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
550#define FUSB300_IGER3_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
551#define FUSB300_IGER3_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
552#define FUSB300_IGER3_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
553
554/*
555 * *Interrupt Enable Group 4 Register (offset = 430H)
556 * */
557
558#define FUSB300_IGER4_EEP_RX0_INT(n) (1 << (n + 16))
559#define FUSB300_IGER4_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
560#define FUSB300_IGER4_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
561#define FUSB300_IGER4_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
562#define FUSB300_IGER4_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
563#define FUSB300_IGER4_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
564
565/* EP PRD Ready (EP_PRD_RDY, offset = 504H) */
566
567#define FUSB300_EPPRDR_EP15_PRD_RDY (1 << 15)
568#define FUSB300_EPPRDR_EP14_PRD_RDY (1 << 14)
569#define FUSB300_EPPRDR_EP13_PRD_RDY (1 << 13)
570#define FUSB300_EPPRDR_EP12_PRD_RDY (1 << 12)
571#define FUSB300_EPPRDR_EP11_PRD_RDY (1 << 11)
572#define FUSB300_EPPRDR_EP10_PRD_RDY (1 << 10)
573#define FUSB300_EPPRDR_EP9_PRD_RDY (1 << 9)
574#define FUSB300_EPPRDR_EP8_PRD_RDY (1 << 8)
575#define FUSB300_EPPRDR_EP7_PRD_RDY (1 << 7)
576#define FUSB300_EPPRDR_EP6_PRD_RDY (1 << 6)
577#define FUSB300_EPPRDR_EP5_PRD_RDY (1 << 5)
578#define FUSB300_EPPRDR_EP4_PRD_RDY (1 << 4)
579#define FUSB300_EPPRDR_EP3_PRD_RDY (1 << 3)
580#define FUSB300_EPPRDR_EP2_PRD_RDY (1 << 2)
581#define FUSB300_EPPRDR_EP1_PRD_RDY (1 << 1)
582#define FUSB300_EPPRDR_EP_PRD_RDY(n) (1 << n)
583
584/* AHB Bus Control Register (offset = 514H) */
585#define FUSB300_AHBBCR_S1_SPLIT_ON (1 << 17)
586#define FUSB300_AHBBCR_S0_SPLIT_ON (1 << 16)
587#define FUSB300_AHBBCR_S1_1entry (0 << 12)
588#define FUSB300_AHBBCR_S1_4entry (3 << 12)
589#define FUSB300_AHBBCR_S1_8entry (5 << 12)
590#define FUSB300_AHBBCR_S1_16entry (7 << 12)
591#define FUSB300_AHBBCR_S0_1entry (0 << 8)
592#define FUSB300_AHBBCR_S0_4entry (3 << 8)
593#define FUSB300_AHBBCR_S0_8entry (5 << 8)
594#define FUSB300_AHBBCR_S0_16entry (7 << 8)
595#define FUSB300_AHBBCR_M1_BURST_SINGLE (0 << 4)
596#define FUSB300_AHBBCR_M1_BURST_INCR (1 << 4)
597#define FUSB300_AHBBCR_M1_BURST_INCR4 (3 << 4)
598#define FUSB300_AHBBCR_M1_BURST_INCR8 (5 << 4)
599#define FUSB300_AHBBCR_M1_BURST_INCR16 (7 << 4)
600#define FUSB300_AHBBCR_M0_BURST_SINGLE 0
601#define FUSB300_AHBBCR_M0_BURST_INCR 1
602#define FUSB300_AHBBCR_M0_BURST_INCR4 3
603#define FUSB300_AHBBCR_M0_BURST_INCR8 5
604#define FUSB300_AHBBCR_M0_BURST_INCR16 7
605#define FUSB300_IGER5_EEP_STL_INT(n) (1 << n)
606
607/* WORD 0 Data Structure of PRD Table */
608#define FUSB300_EPPRD0_M (1 << 30)
609#define FUSB300_EPPRD0_O (1 << 29)
610/* The finished prd */
611#define FUSB300_EPPRD0_F (1 << 28)
612#define FUSB300_EPPRD0_I (1 << 27)
613#define FUSB300_EPPRD0_A (1 << 26)
614/* To decide HW point to first prd at next time */
615#define FUSB300_EPPRD0_L (1 << 25)
616#define FUSB300_EPPRD0_H (1 << 24)
617#define FUSB300_EPPRD0_BTC(n) (n & 0xFFFFFF)
618
619/*----------------------------------------------------------------------*/
620#define FUSB300_MAX_NUM_EP 16
621
622#define FUSB300_FIFO_ENTRY_NUM 8
623#define FUSB300_MAX_FIFO_ENTRY 8
624
625#define SS_CTL_MAX_PACKET_SIZE 0x200
626#define SS_BULK_MAX_PACKET_SIZE 0x400
627#define SS_INT_MAX_PACKET_SIZE 0x400
628#define SS_ISO_MAX_PACKET_SIZE 0x400
629
630#define HS_BULK_MAX_PACKET_SIZE 0x200
631#define HS_CTL_MAX_PACKET_SIZE 0x40
632#define HS_INT_MAX_PACKET_SIZE 0x400
633#define HS_ISO_MAX_PACKET_SIZE 0x400
634
635struct fusb300_ep_info {
636 u8 epnum;
637 u8 type;
638 u8 interval;
639 u8 dir_in;
640 u16 maxpacket;
641 u16 addrofs;
642 u16 bw_num;
643};
644
645struct fusb300_request {
646
647 struct usb_request req;
648 struct list_head queue;
649};
650
651
652struct fusb300_ep {
653 struct usb_ep ep;
654 struct fusb300 *fusb300;
655
656 struct list_head queue;
657 unsigned stall:1;
658 unsigned wedged:1;
659 unsigned use_dma:1;
660
661 unsigned char epnum;
662 unsigned char type;
663 const struct usb_endpoint_descriptor *desc;
664};
665
666struct fusb300 {
667 spinlock_t lock;
668 void __iomem *reg;
669
670 unsigned long irq_trigger;
671
672 struct usb_gadget gadget;
673 struct usb_gadget_driver *driver;
674
675 struct fusb300_ep *ep[FUSB300_MAX_NUM_EP];
676
677 struct usb_request *ep0_req; /* for internal request */
678 __le16 ep0_data;
679 u32 ep0_length; /* for internal request */
680 u8 ep0_dir; /* 0/0x80 out/in */
681
682 u8 fifo_entry_num; /* next start fifo entry */
683 u32 addrofs; /* next fifo address offset */
684 u8 reenum; /* if re-enumeration */
685};
686
687#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 14:39:42 -0500