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authorRobert Jarzmik <rjarzmik@free.fr>2008-04-18 18:56:49 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2008-05-02 13:25:53 -0400
commitd75379a538708c5a8e3dba673d866c3f5f856620 (patch)
treed6d8bcc134c16b107682ae9fcab9e8bae89c1af1 /drivers/usb
parentd301f528eb7b204fc99fb9ebbf289f84a69bfa19 (diff)
usb: pxa27x_udc driver
Adds pxa27x udc driver to support USB peripherals on pxa27x chips. The driver is compatible with: Gadget Zero, the File Storage gadget, and the Ethernet gadget (only in CDC subset mode). The driver can't properly support multiple interfaces, because of hardware bugs without possible workaround. That means no RNDIS support from g_ether, and no CDC ACM support in g_serial. Signed-off-by: Robert Jarzmik <rjarzmik@free.fr> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/gadget/Kconfig20
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/ether.c8
-rw-r--r--drivers/usb/gadget/pxa27x_udc.c2404
-rw-r--r--drivers/usb/gadget/pxa27x_udc.h487
5 files changed, 2916 insertions, 4 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index f7b54651dd42..6e784d2db423 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -231,6 +231,26 @@ config SUPERH_BUILT_IN_M66592
231 However, this problem is improved if change a value of 231 However, this problem is improved if change a value of
232 NET_IP_ALIGN to 4. 232 NET_IP_ALIGN to 4.
233 233
234config USB_GADGET_PXA27X
235 boolean "PXA 27x"
236 depends on ARCH_PXA && PXA27x
237 help
238 Intel's PXA 27x series XScale ARM v5TE processors include
239 an integrated full speed USB 1.1 device controller.
240
241 It has up to 23 endpoints, as well as endpoint zero (for
242 control transfers).
243
244 Say "y" to link the driver statically, or "m" to build a
245 dynamically linked module called "pxa27x_udc" and force all
246 gadget drivers to also be dynamically linked.
247
248config USB_PXA27X
249 tristate
250 depends on USB_GADGET_PXA27X
251 default USB_GADGET
252 select USB_GADGET_SELECTED
253
234config USB_GADGET_GOKU 254config USB_GADGET_GOKU
235 boolean "Toshiba TC86C001 'Goku-S'" 255 boolean "Toshiba TC86C001 'Goku-S'"
236 depends on PCI 256 depends on PCI
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index c3aab80b6c76..12357255d740 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_USB_DUMMY_HCD) += dummy_hcd.o
9obj-$(CONFIG_USB_NET2280) += net2280.o 9obj-$(CONFIG_USB_NET2280) += net2280.o
10obj-$(CONFIG_USB_AMD5536UDC) += amd5536udc.o 10obj-$(CONFIG_USB_AMD5536UDC) += amd5536udc.o
11obj-$(CONFIG_USB_PXA2XX) += pxa2xx_udc.o 11obj-$(CONFIG_USB_PXA2XX) += pxa2xx_udc.o
12obj-$(CONFIG_USB_PXA27X) += pxa27x_udc.o
12obj-$(CONFIG_USB_GOKU) += goku_udc.o 13obj-$(CONFIG_USB_GOKU) += goku_udc.o
13obj-$(CONFIG_USB_OMAP) += omap_udc.o 14obj-$(CONFIG_USB_OMAP) += omap_udc.o
14obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o 15obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index bb93bdd76593..8d61ea67a817 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -235,10 +235,6 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address");
235#define DEV_CONFIG_CDC 235#define DEV_CONFIG_CDC
236#endif 236#endif
237 237
238#ifdef CONFIG_USB_GADGET_PXA27X
239#define DEV_CONFIG_CDC
240#endif
241
242#ifdef CONFIG_USB_GADGET_S3C2410 238#ifdef CONFIG_USB_GADGET_S3C2410
243#define DEV_CONFIG_CDC 239#define DEV_CONFIG_CDC
244#endif 240#endif
@@ -270,6 +266,10 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address");
270#define DEV_CONFIG_SUBSET 266#define DEV_CONFIG_SUBSET
271#endif 267#endif
272 268
269#ifdef CONFIG_USB_GADGET_PXA27X
270#define DEV_CONFIG_SUBSET
271#endif
272
273#ifdef CONFIG_USB_GADGET_SUPERH 273#ifdef CONFIG_USB_GADGET_SUPERH
274#define DEV_CONFIG_SUBSET 274#define DEV_CONFIG_SUBSET
275#endif 275#endif
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
new file mode 100644
index 000000000000..75eba202f737
--- /dev/null
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -0,0 +1,2404 @@
1/*
2 * Handles the Intel 27x USB Device Controller (UDC)
3 *
4 * Inspired by original driver by Frank Becker, David Brownell, and others.
5 * Copyright (C) 2008 Robert Jarzmik
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <linux/version.h>
26#include <linux/errno.h>
27#include <linux/platform_device.h>
28#include <linux/delay.h>
29#include <linux/list.h>
30#include <linux/interrupt.h>
31#include <linux/proc_fs.h>
32#include <linux/clk.h>
33#include <linux/irq.h>
34
35#include <asm/byteorder.h>
36#include <asm/hardware.h>
37
38#include <linux/usb.h>
39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h>
41
42#include <asm/arch/udc.h>
43
44#include "pxa27x_udc.h"
45
46/*
47 * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x
48 * series processors.
49 *
50 * Such controller drivers work with a gadget driver. The gadget driver
51 * returns descriptors, implements configuration and data protocols used
52 * by the host to interact with this device, and allocates endpoints to
53 * the different protocol interfaces. The controller driver virtualizes
54 * usb hardware so that the gadget drivers will be more portable.
55 *
56 * This UDC hardware wants to implement a bit too much USB protocol. The
57 * biggest issues are: that the endpoints have to be set up before the
58 * controller can be enabled (minor, and not uncommon); and each endpoint
59 * can only have one configuration, interface and alternative interface
60 * number (major, and very unusual). Once set up, these cannot be changed
61 * without a controller reset.
62 *
63 * The workaround is to setup all combinations necessary for the gadgets which
64 * will work with this driver. This is done in pxa_udc structure, statically.
65 * See pxa_udc, udc_usb_ep versus pxa_ep, and matching function find_pxa_ep.
66 * (You could modify this if needed. Some drivers have a "fifo_mode" module
67 * parameter to facilitate such changes.)
68 *
69 * The combinations have been tested with these gadgets :
70 * - zero gadget
71 * - file storage gadget
72 * - ether gadget
73 *
74 * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is
75 * made of UDC's double buffering either. USB "On-The-Go" is not implemented.
76 *
77 * All the requests are handled the same way :
78 * - the drivers tries to handle the request directly to the IO
79 * - if the IO fifo is not big enough, the remaining is send/received in
80 * interrupt handling.
81 */
82
83#define DRIVER_VERSION "2008-04-18"
84#define DRIVER_DESC "PXA 27x USB Device Controller driver"
85
86static const char driver_name[] = "pxa27x_udc";
87static struct pxa_udc *the_controller;
88
89static void handle_ep(struct pxa_ep *ep);
90
91/*
92 * Debug filesystem
93 */
94#ifdef CONFIG_USB_GADGET_DEBUG_FS
95
96#include <linux/debugfs.h>
97#include <linux/uaccess.h>
98#include <linux/seq_file.h>
99
100static int state_dbg_show(struct seq_file *s, void *p)
101{
102 struct pxa_udc *udc = s->private;
103 int pos = 0, ret;
104 u32 tmp;
105
106 ret = -ENODEV;
107 if (!udc->driver)
108 goto out;
109
110 /* basic device status */
111 pos += seq_printf(s, DRIVER_DESC "\n"
112 "%s version: %s\nGadget driver: %s\n",
113 driver_name, DRIVER_VERSION,
114 udc->driver ? udc->driver->driver.name : "(none)");
115
116 tmp = udc_readl(udc, UDCCR);
117 pos += seq_printf(s,
118 "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), "
119 "con=%d,inter=%d,altinter=%d\n", tmp,
120 (tmp & UDCCR_OEN) ? " oen":"",
121 (tmp & UDCCR_AALTHNP) ? " aalthnp":"",
122 (tmp & UDCCR_AHNP) ? " rem" : "",
123 (tmp & UDCCR_BHNP) ? " rstir" : "",
124 (tmp & UDCCR_DWRE) ? " dwre" : "",
125 (tmp & UDCCR_SMAC) ? " smac" : "",
126 (tmp & UDCCR_EMCE) ? " emce" : "",
127 (tmp & UDCCR_UDR) ? " udr" : "",
128 (tmp & UDCCR_UDA) ? " uda" : "",
129 (tmp & UDCCR_UDE) ? " ude" : "",
130 (tmp & UDCCR_ACN) >> UDCCR_ACN_S,
131 (tmp & UDCCR_AIN) >> UDCCR_AIN_S,
132 (tmp & UDCCR_AAISN) >> UDCCR_AAISN_S);
133 /* registers for device and ep0 */
134 pos += seq_printf(s, "udcicr0=0x%08x udcicr1=0x%08x\n",
135 udc_readl(udc, UDCICR0), udc_readl(udc, UDCICR1));
136 pos += seq_printf(s, "udcisr0=0x%08x udcisr1=0x%08x\n",
137 udc_readl(udc, UDCISR0), udc_readl(udc, UDCISR1));
138 pos += seq_printf(s, "udcfnr=%d\n", udc_readl(udc, UDCFNR));
139 pos += seq_printf(s, "irqs: reset=%lu, suspend=%lu, resume=%lu, "
140 "reconfig=%lu\n",
141 udc->stats.irqs_reset, udc->stats.irqs_suspend,
142 udc->stats.irqs_resume, udc->stats.irqs_reconfig);
143
144 ret = 0;
145out:
146 return ret;
147}
148
149static int queues_dbg_show(struct seq_file *s, void *p)
150{
151 struct pxa_udc *udc = s->private;
152 struct pxa_ep *ep;
153 struct pxa27x_request *req;
154 int pos = 0, i, maxpkt, ret;
155
156 ret = -ENODEV;
157 if (!udc->driver)
158 goto out;
159
160 /* dump endpoint queues */
161 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
162 ep = &udc->pxa_ep[i];
163 maxpkt = ep->fifo_size;
164 pos += seq_printf(s, "%-12s max_pkt=%d %s\n",
165 EPNAME(ep), maxpkt, "pio");
166
167 if (list_empty(&ep->queue)) {
168 pos += seq_printf(s, "\t(nothing queued)\n");
169 continue;
170 }
171
172 list_for_each_entry(req, &ep->queue, queue) {
173 pos += seq_printf(s, "\treq %p len %d/%d buf %p\n",
174 &req->req, req->req.actual,
175 req->req.length, req->req.buf);
176 }
177 }
178
179 ret = 0;
180out:
181 return ret;
182}
183
184static int eps_dbg_show(struct seq_file *s, void *p)
185{
186 struct pxa_udc *udc = s->private;
187 struct pxa_ep *ep;
188 int pos = 0, i, ret;
189 u32 tmp;
190
191 ret = -ENODEV;
192 if (!udc->driver)
193 goto out;
194
195 ep = &udc->pxa_ep[0];
196 tmp = udc_ep_readl(ep, UDCCSR);
197 pos += seq_printf(s, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", tmp,
198 (tmp & UDCCSR0_SA) ? " sa" : "",
199 (tmp & UDCCSR0_RNE) ? " rne" : "",
200 (tmp & UDCCSR0_FST) ? " fst" : "",
201 (tmp & UDCCSR0_SST) ? " sst" : "",
202 (tmp & UDCCSR0_DME) ? " dme" : "",
203 (tmp & UDCCSR0_IPR) ? " ipr" : "",
204 (tmp & UDCCSR0_OPC) ? " opc" : "");
205 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
206 ep = &udc->pxa_ep[i];
207 tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR);
208 pos += seq_printf(s, "%-12s: "
209 "IN %lu(%lu reqs), OUT %lu(%lu reqs), "
210 "irqs=%lu, udccr=0x%08x, udccsr=0x%03x, "
211 "udcbcr=%d\n",
212 EPNAME(ep),
213 ep->stats.in_bytes, ep->stats.in_ops,
214 ep->stats.out_bytes, ep->stats.out_ops,
215 ep->stats.irqs,
216 tmp, udc_ep_readl(ep, UDCCSR),
217 udc_ep_readl(ep, UDCBCR));
218 }
219
220 ret = 0;
221out:
222 return ret;
223}
224
225static int eps_dbg_open(struct inode *inode, struct file *file)
226{
227 return single_open(file, eps_dbg_show, inode->i_private);
228}
229
230static int queues_dbg_open(struct inode *inode, struct file *file)
231{
232 return single_open(file, queues_dbg_show, inode->i_private);
233}
234
235static int state_dbg_open(struct inode *inode, struct file *file)
236{
237 return single_open(file, state_dbg_show, inode->i_private);
238}
239
240static const struct file_operations state_dbg_fops = {
241 .owner = THIS_MODULE,
242 .open = state_dbg_open,
243 .llseek = seq_lseek,
244 .read = seq_read,
245 .release = single_release,
246};
247
248static const struct file_operations queues_dbg_fops = {
249 .owner = THIS_MODULE,
250 .open = queues_dbg_open,
251 .llseek = seq_lseek,
252 .read = seq_read,
253 .release = single_release,
254};
255
256static const struct file_operations eps_dbg_fops = {
257 .owner = THIS_MODULE,
258 .open = eps_dbg_open,
259 .llseek = seq_lseek,
260 .read = seq_read,
261 .release = single_release,
262};
263
264static void pxa_init_debugfs(struct pxa_udc *udc)
265{
266 struct dentry *root, *state, *queues, *eps;
267
268 root = debugfs_create_dir(udc->gadget.name, NULL);
269 if (IS_ERR(root) || !root)
270 goto err_root;
271
272 state = debugfs_create_file("udcstate", 0400, root, udc,
273 &state_dbg_fops);
274 if (!state)
275 goto err_state;
276 queues = debugfs_create_file("queues", 0400, root, udc,
277 &queues_dbg_fops);
278 if (!queues)
279 goto err_queues;
280 eps = debugfs_create_file("epstate", 0400, root, udc,
281 &eps_dbg_fops);
282 if (!queues)
283 goto err_eps;
284
285 udc->debugfs_root = root;
286 udc->debugfs_state = state;
287 udc->debugfs_queues = queues;
288 udc->debugfs_eps = eps;
289 return;
290err_eps:
291 debugfs_remove(eps);
292err_queues:
293 debugfs_remove(queues);
294err_state:
295 debugfs_remove(root);
296err_root:
297 dev_err(udc->dev, "debugfs is not available\n");
298}
299
300static void pxa_cleanup_debugfs(struct pxa_udc *udc)
301{
302 debugfs_remove(udc->debugfs_eps);
303 debugfs_remove(udc->debugfs_queues);
304 debugfs_remove(udc->debugfs_state);
305 debugfs_remove(udc->debugfs_root);
306 udc->debugfs_eps = NULL;
307 udc->debugfs_queues = NULL;
308 udc->debugfs_state = NULL;
309 udc->debugfs_root = NULL;
310}
311
312#else
313static inline void pxa_init_debugfs(struct pxa_udc *udc)
314{
315}
316
317static inline void pxa_cleanup_debugfs(struct pxa_udc *udc)
318{
319}
320#endif
321
322/**
323 * is_match_usb_pxa - check if usb_ep and pxa_ep match
324 * @udc_usb_ep: usb endpoint
325 * @ep: pxa endpoint
326 * @config: configuration required in pxa_ep
327 * @interface: interface required in pxa_ep
328 * @altsetting: altsetting required in pxa_ep
329 *
330 * Returns 1 if all criteria match between pxa and usb endpoint, 0 otherwise
331 */
332static int is_match_usb_pxa(struct udc_usb_ep *udc_usb_ep, struct pxa_ep *ep,
333 int config, int interface, int altsetting)
334{
335 if (usb_endpoint_num(&udc_usb_ep->desc) != ep->addr)
336 return 0;
337 if (usb_endpoint_dir_in(&udc_usb_ep->desc) != ep->dir_in)
338 return 0;
339 if (usb_endpoint_type(&udc_usb_ep->desc) != ep->type)
340 return 0;
341 if ((ep->config != config) || (ep->interface != interface)
342 || (ep->alternate != altsetting))
343 return 0;
344 return 1;
345}
346
347/**
348 * find_pxa_ep - find pxa_ep structure matching udc_usb_ep
349 * @udc: pxa udc
350 * @udc_usb_ep: udc_usb_ep structure
351 *
352 * Match udc_usb_ep and all pxa_ep available, to see if one matches.
353 * This is necessary because of the strong pxa hardware restriction requiring
354 * that once pxa endpoints are initialized, their configuration is freezed, and
355 * no change can be made to their address, direction, or in which configuration,
356 * interface or altsetting they are active ... which differs from more usual
357 * models which have endpoints be roughly just addressable fifos, and leave
358 * configuration events up to gadget drivers (like all control messages).
359 *
360 * Note that there is still a blurred point here :
361 * - we rely on UDCCR register "active interface" and "active altsetting".
362 * This is a nonsense in regard of USB spec, where multiple interfaces are
363 * active at the same time.
364 * - if we knew for sure that the pxa can handle multiple interface at the
365 * same time, assuming Intel's Developer Guide is wrong, this function
366 * should be reviewed, and a cache of couples (iface, altsetting) should
367 * be kept in the pxa_udc structure. In this case this function would match
368 * against the cache of couples instead of the "last altsetting" set up.
369 *
370 * Returns the matched pxa_ep structure or NULL if none found
371 */
372static struct pxa_ep *find_pxa_ep(struct pxa_udc *udc,
373 struct udc_usb_ep *udc_usb_ep)
374{
375 int i;
376 struct pxa_ep *ep;
377 int cfg = udc->config;
378 int iface = udc->last_interface;
379 int alt = udc->last_alternate;
380
381 if (udc_usb_ep == &udc->udc_usb_ep[0])
382 return &udc->pxa_ep[0];
383
384 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
385 ep = &udc->pxa_ep[i];
386 if (is_match_usb_pxa(udc_usb_ep, ep, cfg, iface, alt))
387 return ep;
388 }
389 return NULL;
390}
391
392/**
393 * update_pxa_ep_matches - update pxa_ep cached values in all udc_usb_ep
394 * @udc: pxa udc
395 *
396 * Context: in_interrupt()
397 *
398 * Updates all pxa_ep fields in udc_usb_ep structures, if this field was
399 * previously set up (and is not NULL). The update is necessary is a
400 * configuration change or altsetting change was issued by the USB host.
401 */
402static void update_pxa_ep_matches(struct pxa_udc *udc)
403{
404 int i;
405 struct udc_usb_ep *udc_usb_ep;
406
407 for (i = 1; i < NR_USB_ENDPOINTS; i++) {
408 udc_usb_ep = &udc->udc_usb_ep[i];
409 if (udc_usb_ep->pxa_ep)
410 udc_usb_ep->pxa_ep = find_pxa_ep(udc, udc_usb_ep);
411 }
412}
413
414/**
415 * pio_irq_enable - Enables irq generation for one endpoint
416 * @ep: udc endpoint
417 */
418static void pio_irq_enable(struct pxa_ep *ep)
419{
420 struct pxa_udc *udc = ep->dev;
421 int index = EPIDX(ep);
422 u32 udcicr0 = udc_readl(udc, UDCICR0);
423 u32 udcicr1 = udc_readl(udc, UDCICR1);
424
425 if (index < 16)
426 udc_writel(udc, UDCICR0, udcicr0 | (3 << (index * 2)));
427 else
428 udc_writel(udc, UDCICR1, udcicr1 | (3 << ((index - 16) * 2)));
429}
430
431/**
432 * pio_irq_disable - Disables irq generation for one endpoint
433 * @ep: udc endpoint
434 * @index: endpoint number
435 */
436static void pio_irq_disable(struct pxa_ep *ep)
437{
438 struct pxa_udc *udc = ep->dev;
439 int index = EPIDX(ep);
440 u32 udcicr0 = udc_readl(udc, UDCICR0);
441 u32 udcicr1 = udc_readl(udc, UDCICR1);
442
443 if (index < 16)
444 udc_writel(udc, UDCICR0, udcicr0 & ~(3 << (index * 2)));
445 else
446 udc_writel(udc, UDCICR1, udcicr1 & ~(3 << ((index - 16) * 2)));
447}
448
449/**
450 * udc_set_mask_UDCCR - set bits in UDCCR
451 * @udc: udc device
452 * @mask: bits to set in UDCCR
453 *
454 * Sets bits in UDCCR, leaving DME and FST bits as they were.
455 */
456static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask)
457{
458 u32 udccr = udc_readl(udc, UDCCR);
459 udc_writel(udc, UDCCR,
460 (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS));
461}
462
463/**
464 * udc_clear_mask_UDCCR - clears bits in UDCCR
465 * @udc: udc device
466 * @mask: bit to clear in UDCCR
467 *
468 * Clears bits in UDCCR, leaving DME and FST bits as they were.
469 */
470static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask)
471{
472 u32 udccr = udc_readl(udc, UDCCR);
473 udc_writel(udc, UDCCR,
474 (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS));
475}
476
477/**
478 * ep_count_bytes_remain - get how many bytes in udc endpoint
479 * @ep: udc endpoint
480 *
481 * Returns number of bytes in OUT fifos. Broken for IN fifos (-EOPNOTSUPP)
482 */
483static int ep_count_bytes_remain(struct pxa_ep *ep)
484{
485 if (ep->dir_in)
486 return -EOPNOTSUPP;
487 return udc_ep_readl(ep, UDCBCR) & 0x3ff;
488}
489
490/**
491 * ep_is_empty - checks if ep has byte ready for reading
492 * @ep: udc endpoint
493 *
494 * If endpoint is the control endpoint, checks if there are bytes in the
495 * control endpoint fifo. If endpoint is a data endpoint, checks if bytes
496 * are ready for reading on OUT endpoint.
497 *
498 * Returns 0 if ep not empty, 1 if ep empty, -EOPNOTSUPP if IN endpoint
499 */
500static int ep_is_empty(struct pxa_ep *ep)
501{
502 int ret;
503
504 if (!is_ep0(ep) && ep->dir_in)
505 return -EOPNOTSUPP;
506 if (is_ep0(ep))
507 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR0_RNE);
508 else
509 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNE);
510 return ret;
511}
512
513/**
514 * ep_is_full - checks if ep has place to write bytes
515 * @ep: udc endpoint
516 *
517 * If endpoint is not the control endpoint and is an IN endpoint, checks if
518 * there is place to write bytes into the endpoint.
519 *
520 * Returns 0 if ep not full, 1 if ep full, -EOPNOTSUPP if OUT endpoint
521 */
522static int ep_is_full(struct pxa_ep *ep)
523{
524 if (is_ep0(ep))
525 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_IPR);
526 if (!ep->dir_in)
527 return -EOPNOTSUPP;
528 return (!(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNF));
529}
530
531/**
532 * epout_has_pkt - checks if OUT endpoint fifo has a packet available
533 * @ep: pxa endpoint
534 *
535 * Returns 1 if a complete packet is available, 0 if not, -EOPNOTSUPP for IN ep.
536 */
537static int epout_has_pkt(struct pxa_ep *ep)
538{
539 if (!is_ep0(ep) && ep->dir_in)
540 return -EOPNOTSUPP;
541 if (is_ep0(ep))
542 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_OPC);
543 return (udc_ep_readl(ep, UDCCSR) & UDCCSR_PC);
544}
545
546/**
547 * set_ep0state - Set ep0 automata state
548 * @dev: udc device
549 * @state: state
550 */
551static void set_ep0state(struct pxa_udc *udc, int state)
552{
553 struct pxa_ep *ep = &udc->pxa_ep[0];
554 char *old_stname = EP0_STNAME(udc);
555
556 udc->ep0state = state;
557 ep_dbg(ep, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname,
558 EP0_STNAME(udc), udc_ep_readl(ep, UDCCSR),
559 udc_ep_readl(ep, UDCBCR));
560}
561
562/**
563 * ep0_idle - Put control endpoint into idle state
564 * @dev: udc device
565 */
566static void ep0_idle(struct pxa_udc *dev)
567{
568 set_ep0state(dev, WAIT_FOR_SETUP);
569}
570
571/**
572 * inc_ep_stats_reqs - Update ep stats counts
573 * @ep: physical endpoint
574 * @req: usb request
575 * @is_in: ep direction (USB_DIR_IN or 0)
576 *
577 */
578static void inc_ep_stats_reqs(struct pxa_ep *ep, int is_in)
579{
580 if (is_in)
581 ep->stats.in_ops++;
582 else
583 ep->stats.out_ops++;
584}
585
586/**
587 * inc_ep_stats_bytes - Update ep stats counts
588 * @ep: physical endpoint
589 * @count: bytes transfered on endpoint
590 * @req: usb request
591 * @is_in: ep direction (USB_DIR_IN or 0)
592 */
593static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in)
594{
595 if (is_in)
596 ep->stats.in_bytes += count;
597 else
598 ep->stats.out_bytes += count;
599}
600
601/**
602 * pxa_ep_setup - Sets up an usb physical endpoint
603 * @ep: pxa27x physical endpoint
604 *
605 * Find the physical pxa27x ep, and setup its UDCCR
606 */
607static __init void pxa_ep_setup(struct pxa_ep *ep)
608{
609 u32 new_udccr;
610
611 new_udccr = ((ep->config << UDCCONR_CN_S) & UDCCONR_CN)
612 | ((ep->interface << UDCCONR_IN_S) & UDCCONR_IN)
613 | ((ep->alternate << UDCCONR_AISN_S) & UDCCONR_AISN)
614 | ((EPADDR(ep) << UDCCONR_EN_S) & UDCCONR_EN)
615 | ((EPXFERTYPE(ep) << UDCCONR_ET_S) & UDCCONR_ET)
616 | ((ep->dir_in) ? UDCCONR_ED : 0)
617 | ((ep->fifo_size << UDCCONR_MPS_S) & UDCCONR_MPS)
618 | UDCCONR_EE;
619
620 udc_ep_writel(ep, UDCCR, new_udccr);
621}
622
623/**
624 * pxa_eps_setup - Sets up all usb physical endpoints
625 * @dev: udc device
626 *
627 * Setup all pxa physical endpoints, except ep0
628 */
629static __init void pxa_eps_setup(struct pxa_udc *dev)
630{
631 unsigned int i;
632
633 dev_dbg(dev->dev, "%s: dev=%p\n", __func__, dev);
634
635 for (i = 1; i < NR_PXA_ENDPOINTS; i++)
636 pxa_ep_setup(&dev->pxa_ep[i]);
637}
638
639/**
640 * pxa_ep_alloc_request - Allocate usb request
641 * @_ep: usb endpoint
642 * @gfp_flags:
643 *
644 * For the pxa27x, these can just wrap kmalloc/kfree. gadget drivers
645 * must still pass correctly initialized endpoints, since other controller
646 * drivers may care about how it's currently set up (dma issues etc).
647 */
648static struct usb_request *
649pxa_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
650{
651 struct pxa27x_request *req;
652
653 req = kzalloc(sizeof *req, gfp_flags);
654 if (!req || !_ep)
655 return NULL;
656
657 INIT_LIST_HEAD(&req->queue);
658 req->in_use = 0;
659 req->udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
660
661 return &req->req;
662}
663
664/**
665 * pxa_ep_free_request - Free usb request
666 * @_ep: usb endpoint
667 * @_req: usb request
668 *
669 * Wrapper around kfree to free _req
670 */
671static void pxa_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
672{
673 struct pxa27x_request *req;
674
675 req = container_of(_req, struct pxa27x_request, req);
676 WARN_ON(!list_empty(&req->queue));
677 kfree(req);
678}
679
680/**
681 * ep_add_request - add a request to the endpoint's queue
682 * @ep: usb endpoint
683 * @req: usb request
684 *
685 * Context: ep->lock held
686 *
687 * Queues the request in the endpoint's queue, and enables the interrupts
688 * on the endpoint.
689 */
690static void ep_add_request(struct pxa_ep *ep, struct pxa27x_request *req)
691{
692 if (unlikely(!req))
693 return;
694 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req,
695 req->req.length, udc_ep_readl(ep, UDCCSR));
696
697 req->in_use = 1;
698 list_add_tail(&req->queue, &ep->queue);
699 pio_irq_enable(ep);
700}
701
702/**
703 * ep_del_request - removes a request from the endpoint's queue
704 * @ep: usb endpoint
705 * @req: usb request
706 *
707 * Context: ep->lock held
708 *
709 * Unqueue the request from the endpoint's queue. If there are no more requests
710 * on the endpoint, and if it's not the control endpoint, interrupts are
711 * disabled on the endpoint.
712 */
713static void ep_del_request(struct pxa_ep *ep, struct pxa27x_request *req)
714{
715 if (unlikely(!req))
716 return;
717 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req,
718 req->req.length, udc_ep_readl(ep, UDCCSR));
719
720 list_del_init(&req->queue);
721 req->in_use = 0;
722 if (!is_ep0(ep) && list_empty(&ep->queue))
723 pio_irq_disable(ep);
724}
725
726/**
727 * req_done - Complete an usb request
728 * @ep: pxa physical endpoint
729 * @req: pxa request
730 * @status: usb request status sent to gadget API
731 *
732 * Context: ep->lock held
733 *
734 * Retire a pxa27x usb request. Endpoint must be locked.
735 */
736static void req_done(struct pxa_ep *ep, struct pxa27x_request *req, int status)
737{
738 ep_del_request(ep, req);
739 if (likely(req->req.status == -EINPROGRESS))
740 req->req.status = status;
741 else
742 status = req->req.status;
743
744 if (status && status != -ESHUTDOWN)
745 ep_dbg(ep, "complete req %p stat %d len %u/%u\n",
746 &req->req, status,
747 req->req.actual, req->req.length);
748
749 req->req.complete(&req->udc_usb_ep->usb_ep, &req->req);
750}
751
752/**
753 * ep_end_out_req - Ends control endpoint in request
754 * @ep: physical endpoint
755 * @req: pxa request
756 *
757 * Context: ep->lock held
758 *
759 * Ends endpoint in request (completes usb request).
760 */
761static void ep_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req)
762{
763 inc_ep_stats_reqs(ep, !USB_DIR_IN);
764 req_done(ep, req, 0);
765}
766
767/**
768 * ep0_end_out_req - Ends control endpoint in request (ends data stage)
769 * @ep: physical endpoint
770 * @req: pxa request
771 *
772 * Context: ep->lock held
773 *
774 * Ends control endpoint in request (completes usb request), and puts
775 * control endpoint into idle state
776 */
777static void ep0_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req)
778{
779 set_ep0state(ep->dev, OUT_STATUS_STAGE);
780 ep_end_out_req(ep, req);
781 ep0_idle(ep->dev);
782}
783
784/**
785 * ep_end_in_req - Ends endpoint out request
786 * @ep: physical endpoint
787 * @req: pxa request
788 *
789 * Context: ep->lock held
790 *
791 * Ends endpoint out request (completes usb request).
792 */
793static void ep_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req)
794{
795 inc_ep_stats_reqs(ep, USB_DIR_IN);
796 req_done(ep, req, 0);
797}
798
799/**
800 * ep0_end_in_req - Ends control endpoint out request (ends data stage)
801 * @ep: physical endpoint
802 * @req: pxa request
803 *
804 * Context: ep->lock held
805 *
806 * Ends control endpoint out request (completes usb request), and puts
807 * control endpoint into status state
808 */
809static void ep0_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req)
810{
811 struct pxa_udc *udc = ep->dev;
812
813 set_ep0state(udc, IN_STATUS_STAGE);
814 ep_end_in_req(ep, req);
815}
816
817/**
818 * nuke - Dequeue all requests
819 * @ep: pxa endpoint
820 * @status: usb request status
821 *
822 * Context: ep->lock held
823 *
824 * Dequeues all requests on an endpoint. As a side effect, interrupts will be
825 * disabled on that endpoint (because no more requests).
826 */
827static void nuke(struct pxa_ep *ep, int status)
828{
829 struct pxa27x_request *req;
830
831 while (!list_empty(&ep->queue)) {
832 req = list_entry(ep->queue.next, struct pxa27x_request, queue);
833 req_done(ep, req, status);
834 }
835}
836
837/**
838 * read_packet - transfer 1 packet from an OUT endpoint into request
839 * @ep: pxa physical endpoint
840 * @req: usb request
841 *
842 * Takes bytes from OUT endpoint and transfers them info the usb request.
843 * If there is less space in request than bytes received in OUT endpoint,
844 * bytes are left in the OUT endpoint.
845 *
846 * Returns how many bytes were actually transfered
847 */
848static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req)
849{
850 u32 *buf;
851 int bytes_ep, bufferspace, count, i;
852
853 bytes_ep = ep_count_bytes_remain(ep);
854 bufferspace = req->req.length - req->req.actual;
855
856 buf = (u32 *)(req->req.buf + req->req.actual);
857 prefetchw(buf);
858
859 if (likely(!ep_is_empty(ep)))
860 count = min(bytes_ep, bufferspace);
861 else /* zlp */
862 count = 0;
863
864 for (i = count; i > 0; i -= 4)
865 *buf++ = udc_ep_readl(ep, UDCDR);
866 req->req.actual += count;
867
868 udc_ep_writel(ep, UDCCSR, UDCCSR_PC);
869
870 return count;
871}
872
873/**
874 * write_packet - transfer 1 packet from request into an IN endpoint
875 * @ep: pxa physical endpoint
876 * @req: usb request
877 * @max: max bytes that fit into endpoint
878 *
879 * Takes bytes from usb request, and transfers them into the physical
880 * endpoint. If there are no bytes to transfer, doesn't write anything
881 * to physical endpoint.
882 *
883 * Returns how many bytes were actually transfered.
884 */
885static int write_packet(struct pxa_ep *ep, struct pxa27x_request *req,
886 unsigned int max)
887{
888 int length, count, remain, i;
889 u32 *buf;
890 u8 *buf_8;
891
892 buf = (u32 *)(req->req.buf + req->req.actual);
893 prefetch(buf);
894
895 length = min(req->req.length - req->req.actual, max);
896 req->req.actual += length;
897
898 remain = length & 0x3;
899 count = length & ~(0x3);
900 for (i = count; i > 0 ; i -= 4)
901 udc_ep_writel(ep, UDCDR, *buf++);
902
903 buf_8 = (u8 *)buf;
904 for (i = remain; i > 0; i--)
905 udc_ep_writeb(ep, UDCDR, *buf_8++);
906
907 ep_vdbg(ep, "length=%d+%d, udccsr=0x%03x\n", count, remain,
908 udc_ep_readl(ep, UDCCSR));
909
910 return length;
911}
912
913/**
914 * read_fifo - Transfer packets from OUT endpoint into usb request
915 * @ep: pxa physical endpoint
916 * @req: usb request
917 *
918 * Context: callable when in_interrupt()
919 *
920 * Unload as many packets as possible from the fifo we use for usb OUT
921 * transfers and put them into the request. Caller should have made sure
922 * there's at least one packet ready.
923 * Doesn't complete the request, that's the caller's job
924 *
925 * Returns 1 if the request completed, 0 otherwise
926 */
927static int read_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
928{
929 int count, is_short, completed = 0;
930
931 while (epout_has_pkt(ep)) {
932 count = read_packet(ep, req);
933 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
934
935 is_short = (count < ep->fifo_size);
936 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
937 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "",
938 &req->req, req->req.actual, req->req.length);
939
940 /* completion */
941 if (is_short || req->req.actual == req->req.length) {
942 completed = 1;
943 break;
944 }
945 /* finished that packet. the next one may be waiting... */
946 }
947 return completed;
948}
949
950/**
951 * write_fifo - transfer packets from usb request into an IN endpoint
952 * @ep: pxa physical endpoint
953 * @req: pxa usb request
954 *
955 * Write to an IN endpoint fifo, as many packets as possible.
956 * irqs will use this to write the rest later.
957 * caller guarantees at least one packet buffer is ready (or a zlp).
958 * Doesn't complete the request, that's the caller's job
959 *
960 * Returns 1 if request fully transfered, 0 if partial transfer
961 */
962static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
963{
964 unsigned max;
965 int count, is_short, is_last = 0, completed = 0, totcount = 0;
966 u32 udccsr;
967
968 max = ep->fifo_size;
969 do {
970 is_short = 0;
971
972 udccsr = udc_ep_readl(ep, UDCCSR);
973 if (udccsr & UDCCSR_PC) {
974 ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n",
975 udccsr);
976 udc_ep_writel(ep, UDCCSR, UDCCSR_PC);
977 }
978 if (udccsr & UDCCSR_TRN) {
979 ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n",
980 udccsr);
981 udc_ep_writel(ep, UDCCSR, UDCCSR_TRN);
982 }
983
984 count = write_packet(ep, req, max);
985 inc_ep_stats_bytes(ep, count, USB_DIR_IN);
986 totcount += count;
987
988 /* last packet is usually short (or a zlp) */
989 if (unlikely(count < max)) {
990 is_last = 1;
991 is_short = 1;
992 } else {
993 if (likely(req->req.length > req->req.actual)
994 || req->req.zero)
995 is_last = 0;
996 else
997 is_last = 1;
998 /* interrupt/iso maxpacket may not fill the fifo */
999 is_short = unlikely(max < ep->fifo_size);
1000 }
1001
1002 if (is_short)
1003 udc_ep_writel(ep, UDCCSR, UDCCSR_SP);
1004
1005 /* requests complete when all IN data is in the FIFO */
1006 if (is_last) {
1007 completed = 1;
1008 break;
1009 }
1010 } while (!ep_is_full(ep));
1011
1012 ep_dbg(ep, "wrote count:%d bytes%s%s, left:%d req=%p\n",
1013 totcount, is_last ? "/L" : "", is_short ? "/S" : "",
1014 req->req.length - req->req.actual, &req->req);
1015
1016 return completed;
1017}
1018
1019/**
1020 * read_ep0_fifo - Transfer packets from control endpoint into usb request
1021 * @ep: control endpoint
1022 * @req: pxa usb request
1023 *
1024 * Special ep0 version of the above read_fifo. Reads as many bytes from control
1025 * endpoint as can be read, and stores them into usb request (limited by request
1026 * maximum length).
1027 *
1028 * Returns 0 if usb request only partially filled, 1 if fully filled
1029 */
1030static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1031{
1032 int count, is_short, completed = 0;
1033
1034 while (epout_has_pkt(ep)) {
1035 count = read_packet(ep, req);
1036 udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC);
1037 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
1038
1039 is_short = (count < ep->fifo_size);
1040 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
1041 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "",
1042 &req->req, req->req.actual, req->req.length);
1043
1044 if (is_short || req->req.actual >= req->req.length) {
1045 completed = 1;
1046 break;
1047 }
1048 }
1049
1050 return completed;
1051}
1052
1053/**
1054 * write_ep0_fifo - Send a request to control endpoint (ep0 in)
1055 * @ep: control endpoint
1056 * @req: request
1057 *
1058 * Context: callable when in_interrupt()
1059 *
1060 * Sends a request (or a part of the request) to the control endpoint (ep0 in).
1061 * If the request doesn't fit, the remaining part will be sent from irq.
1062 * The request is considered fully written only if either :
1063 * - last write transfered all remaining bytes, but fifo was not fully filled
1064 * - last write was a 0 length write
1065 *
1066 * Returns 1 if request fully written, 0 if request only partially sent
1067 */
1068static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1069{
1070 unsigned count;
1071 int is_last, is_short;
1072
1073 count = write_packet(ep, req, EP0_FIFO_SIZE);
1074 inc_ep_stats_bytes(ep, count, USB_DIR_IN);
1075
1076 is_short = (count < EP0_FIFO_SIZE);
1077 is_last = ((count == 0) || (count < EP0_FIFO_SIZE));
1078
1079 /* Sends either a short packet or a 0 length packet */
1080 if (unlikely(is_short))
1081 udc_ep_writel(ep, UDCCSR, UDCCSR0_IPR);
1082
1083 ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n",
1084 count, is_short ? "/S" : "", is_last ? "/L" : "",
1085 req->req.length - req->req.actual,
1086 &req->req, udc_ep_readl(ep, UDCCSR));
1087
1088 return is_last;
1089}
1090
1091/**
1092 * pxa_ep_queue - Queue a request into an IN endpoint
1093 * @_ep: usb endpoint
1094 * @_req: usb request
1095 * @gfp_flags: flags
1096 *
1097 * Context: normally called when !in_interrupt, but callable when in_interrupt()
1098 * in the special case of ep0 setup :
1099 * (irq->handle_ep0_ctrl_req->gadget_setup->pxa_ep_queue)
1100 *
1101 * Returns 0 if succedeed, error otherwise
1102 */
1103static int pxa_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
1104 gfp_t gfp_flags)
1105{
1106 struct udc_usb_ep *udc_usb_ep;
1107 struct pxa_ep *ep;
1108 struct pxa27x_request *req;
1109 struct pxa_udc *dev;
1110 unsigned long flags;
1111 int rc = 0;
1112 int is_first_req;
1113 unsigned length;
1114
1115 req = container_of(_req, struct pxa27x_request, req);
1116 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1117
1118 if (unlikely(!_req || !_req->complete || !_req->buf))
1119 return -EINVAL;
1120
1121 if (unlikely(!_ep))
1122 return -EINVAL;
1123
1124 dev = udc_usb_ep->dev;
1125 ep = udc_usb_ep->pxa_ep;
1126 if (unlikely(!ep))
1127 return -EINVAL;
1128
1129 dev = ep->dev;
1130 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1131 ep_dbg(ep, "bogus device state\n");
1132 return -ESHUTDOWN;
1133 }
1134
1135 /* iso is always one packet per request, that's the only way
1136 * we can report per-packet status. that also helps with dma.
1137 */
1138 if (unlikely(EPXFERTYPE_is_ISO(ep)
1139 && req->req.length > ep->fifo_size))
1140 return -EMSGSIZE;
1141
1142 spin_lock_irqsave(&ep->lock, flags);
1143
1144 is_first_req = list_empty(&ep->queue);
1145 ep_dbg(ep, "queue req %p(first=%s), len %d buf %p\n",
1146 _req, is_first_req ? "yes" : "no",
1147 _req->length, _req->buf);
1148
1149 if (!ep->enabled) {
1150 _req->status = -ESHUTDOWN;
1151 rc = -ESHUTDOWN;
1152 goto out;
1153 }
1154
1155 if (req->in_use) {
1156 ep_err(ep, "refusing to queue req %p (already queued)\n", req);
1157 goto out;
1158 }
1159
1160 length = _req->length;
1161 _req->status = -EINPROGRESS;
1162 _req->actual = 0;
1163
1164 ep_add_request(ep, req);
1165
1166 if (is_ep0(ep)) {
1167 switch (dev->ep0state) {
1168 case WAIT_ACK_SET_CONF_INTERF:
1169 if (length == 0) {
1170 ep_end_in_req(ep, req);
1171 } else {
1172 ep_err(ep, "got a request of %d bytes while"
1173 "in state WATI_ACK_SET_CONF_INTERF\n",
1174 length);
1175 ep_del_request(ep, req);
1176 rc = -EL2HLT;
1177 }
1178 ep0_idle(ep->dev);
1179 break;
1180 case IN_DATA_STAGE:
1181 if (!ep_is_full(ep))
1182 if (write_ep0_fifo(ep, req))
1183 ep0_end_in_req(ep, req);
1184 break;
1185 case OUT_DATA_STAGE:
1186 if ((length == 0) || !epout_has_pkt(ep))
1187 if (read_ep0_fifo(ep, req))
1188 ep0_end_out_req(ep, req);
1189 break;
1190 default:
1191 ep_err(ep, "odd state %s to send me a request\n",
1192 EP0_STNAME(ep->dev));
1193 ep_del_request(ep, req);
1194 rc = -EL2HLT;
1195 break;
1196 }
1197 } else {
1198 handle_ep(ep);
1199 }
1200
1201out:
1202 spin_unlock_irqrestore(&ep->lock, flags);
1203 return rc;
1204}
1205
1206/**
1207 * pxa_ep_dequeue - Dequeue one request
1208 * @_ep: usb endpoint
1209 * @_req: usb request
1210 *
1211 * Return 0 if no error, -EINVAL or -ECONNRESET otherwise
1212 */
1213static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1214{
1215 struct pxa_ep *ep;
1216 struct udc_usb_ep *udc_usb_ep;
1217 struct pxa27x_request *req;
1218 unsigned long flags;
1219 int rc;
1220
1221 if (!_ep)
1222 return -EINVAL;
1223 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1224 ep = udc_usb_ep->pxa_ep;
1225 if (!ep || is_ep0(ep))
1226 return -EINVAL;
1227
1228 spin_lock_irqsave(&ep->lock, flags);
1229
1230 /* make sure it's actually queued on this endpoint */
1231 list_for_each_entry(req, &ep->queue, queue) {
1232 if (&req->req == _req)
1233 break;
1234 }
1235
1236 rc = -EINVAL;
1237 if (&req->req != _req)
1238 goto out;
1239
1240 rc = 0;
1241 req_done(ep, req, -ECONNRESET);
1242out:
1243 spin_unlock_irqrestore(&ep->lock, flags);
1244 return rc;
1245}
1246
1247/**
1248 * pxa_ep_set_halt - Halts operations on one endpoint
1249 * @_ep: usb endpoint
1250 * @value:
1251 *
1252 * Returns 0 if no error, -EINVAL, -EROFS, -EAGAIN otherwise
1253 */
1254static int pxa_ep_set_halt(struct usb_ep *_ep, int value)
1255{
1256 struct pxa_ep *ep;
1257 struct udc_usb_ep *udc_usb_ep;
1258 unsigned long flags;
1259 int rc;
1260
1261
1262 if (!_ep)
1263 return -EINVAL;
1264 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1265 ep = udc_usb_ep->pxa_ep;
1266 if (!ep || is_ep0(ep))
1267 return -EINVAL;
1268
1269 if (value == 0) {
1270 /*
1271 * This path (reset toggle+halt) is needed to implement
1272 * SET_INTERFACE on normal hardware. but it can't be
1273 * done from software on the PXA UDC, and the hardware
1274 * forgets to do it as part of SET_INTERFACE automagic.
1275 */
1276 ep_dbg(ep, "only host can clear halt\n");
1277 return -EROFS;
1278 }
1279
1280 spin_lock_irqsave(&ep->lock, flags);
1281
1282 rc = -EAGAIN;
1283 if (ep->dir_in && (ep_is_full(ep) || !list_empty(&ep->queue)))
1284 goto out;
1285
1286 /* FST, FEF bits are the same for control and non control endpoints */
1287 rc = 0;
1288 udc_ep_writel(ep, UDCCSR, UDCCSR_FST | UDCCSR_FEF);
1289 if (is_ep0(ep))
1290 set_ep0state(ep->dev, STALL);
1291
1292out:
1293 spin_unlock_irqrestore(&ep->lock, flags);
1294 return rc;
1295}
1296
1297/**
1298 * pxa_ep_fifo_status - Get how many bytes in physical endpoint
1299 * @_ep: usb endpoint
1300 *
1301 * Returns number of bytes in OUT fifos. Broken for IN fifos.
1302 */
1303static int pxa_ep_fifo_status(struct usb_ep *_ep)
1304{
1305 struct pxa_ep *ep;
1306 struct udc_usb_ep *udc_usb_ep;
1307
1308 if (!_ep)
1309 return -ENODEV;
1310 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1311 ep = udc_usb_ep->pxa_ep;
1312 if (!ep || is_ep0(ep))
1313 return -ENODEV;
1314
1315 if (ep->dir_in)
1316 return -EOPNOTSUPP;
1317 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN || ep_is_empty(ep))
1318 return 0;
1319 else
1320 return ep_count_bytes_remain(ep) + 1;
1321}
1322
1323/**
1324 * pxa_ep_fifo_flush - Flushes one endpoint
1325 * @_ep: usb endpoint
1326 *
1327 * Discards all data in one endpoint(IN or OUT), except control endpoint.
1328 */
1329static void pxa_ep_fifo_flush(struct usb_ep *_ep)
1330{
1331 struct pxa_ep *ep;
1332 struct udc_usb_ep *udc_usb_ep;
1333 unsigned long flags;
1334
1335 if (!_ep)
1336 return;
1337 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1338 ep = udc_usb_ep->pxa_ep;
1339 if (!ep || is_ep0(ep))
1340 return;
1341
1342 spin_lock_irqsave(&ep->lock, flags);
1343
1344 if (unlikely(!list_empty(&ep->queue)))
1345 ep_dbg(ep, "called while queue list not empty\n");
1346 ep_dbg(ep, "called\n");
1347
1348 /* for OUT, just read and discard the FIFO contents. */
1349 if (!ep->dir_in) {
1350 while (!ep_is_empty(ep))
1351 udc_ep_readl(ep, UDCDR);
1352 } else {
1353 /* most IN status is the same, but ISO can't stall */
1354 udc_ep_writel(ep, UDCCSR,
1355 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN
1356 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST));
1357 }
1358
1359 spin_unlock_irqrestore(&ep->lock, flags);
1360
1361 return;
1362}
1363
1364/**
1365 * pxa_ep_enable - Enables usb endpoint
1366 * @_ep: usb endpoint
1367 * @desc: usb endpoint descriptor
1368 *
1369 * Nothing much to do here, as ep configuration is done once and for all
1370 * before udc is enabled. After udc enable, no physical endpoint configuration
1371 * can be changed.
1372 * Function makes sanity checks and flushes the endpoint.
1373 */
1374static int pxa_ep_enable(struct usb_ep *_ep,
1375 const struct usb_endpoint_descriptor *desc)
1376{
1377 struct pxa_ep *ep;
1378 struct udc_usb_ep *udc_usb_ep;
1379 struct pxa_udc *udc;
1380
1381 if (!_ep || !desc)
1382 return -EINVAL;
1383
1384 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1385 if (udc_usb_ep->pxa_ep) {
1386 ep = udc_usb_ep->pxa_ep;
1387 ep_warn(ep, "usb_ep %s already enabled, doing nothing\n",
1388 _ep->name);
1389 } else {
1390 ep = find_pxa_ep(udc_usb_ep->dev, udc_usb_ep);
1391 }
1392
1393 if (!ep || is_ep0(ep)) {
1394 dev_err(udc_usb_ep->dev->dev,
1395 "unable to match pxa_ep for ep %s\n",
1396 _ep->name);
1397 return -EINVAL;
1398 }
1399
1400 if ((desc->bDescriptorType != USB_DT_ENDPOINT)
1401 || (ep->type != usb_endpoint_type(desc))) {
1402 ep_err(ep, "type mismatch\n");
1403 return -EINVAL;
1404 }
1405
1406 if (ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
1407 ep_err(ep, "bad maxpacket\n");
1408 return -ERANGE;
1409 }
1410
1411 udc_usb_ep->pxa_ep = ep;
1412 udc = ep->dev;
1413
1414 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1415 ep_err(ep, "bogus device state\n");
1416 return -ESHUTDOWN;
1417 }
1418
1419 ep->enabled = 1;
1420
1421 /* flush fifo (mostly for OUT buffers) */
1422 pxa_ep_fifo_flush(_ep);
1423
1424 ep_dbg(ep, "enabled\n");
1425 return 0;
1426}
1427
1428/**
1429 * pxa_ep_disable - Disable usb endpoint
1430 * @_ep: usb endpoint
1431 *
1432 * Same as for pxa_ep_enable, no physical endpoint configuration can be
1433 * changed.
1434 * Function flushes the endpoint and related requests.
1435 */
1436static int pxa_ep_disable(struct usb_ep *_ep)
1437{
1438 struct pxa_ep *ep;
1439 struct udc_usb_ep *udc_usb_ep;
1440 unsigned long flags;
1441
1442 if (!_ep)
1443 return -EINVAL;
1444
1445 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1446 ep = udc_usb_ep->pxa_ep;
1447 if (!ep || is_ep0(ep) || !list_empty(&ep->queue))
1448 return -EINVAL;
1449
1450 spin_lock_irqsave(&ep->lock, flags);
1451 ep->enabled = 0;
1452 nuke(ep, -ESHUTDOWN);
1453 spin_unlock_irqrestore(&ep->lock, flags);
1454
1455 pxa_ep_fifo_flush(_ep);
1456 udc_usb_ep->pxa_ep = NULL;
1457
1458 ep_dbg(ep, "disabled\n");
1459 return 0;
1460}
1461
1462static struct usb_ep_ops pxa_ep_ops = {
1463 .enable = pxa_ep_enable,
1464 .disable = pxa_ep_disable,
1465
1466 .alloc_request = pxa_ep_alloc_request,
1467 .free_request = pxa_ep_free_request,
1468
1469 .queue = pxa_ep_queue,
1470 .dequeue = pxa_ep_dequeue,
1471
1472 .set_halt = pxa_ep_set_halt,
1473 .fifo_status = pxa_ep_fifo_status,
1474 .fifo_flush = pxa_ep_fifo_flush,
1475};
1476
1477
1478/**
1479 * pxa_udc_get_frame - Returns usb frame number
1480 * @_gadget: usb gadget
1481 */
1482static int pxa_udc_get_frame(struct usb_gadget *_gadget)
1483{
1484 struct pxa_udc *udc = to_gadget_udc(_gadget);
1485
1486 return (udc_readl(udc, UDCFNR) & 0x7ff);
1487}
1488
1489/**
1490 * pxa_udc_wakeup - Force udc device out of suspend
1491 * @_gadget: usb gadget
1492 *
1493 * Returns 0 if succesfull, error code otherwise
1494 */
1495static int pxa_udc_wakeup(struct usb_gadget *_gadget)
1496{
1497 struct pxa_udc *udc = to_gadget_udc(_gadget);
1498
1499 /* host may not have enabled remote wakeup */
1500 if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0)
1501 return -EHOSTUNREACH;
1502 udc_set_mask_UDCCR(udc, UDCCR_UDR);
1503 return 0;
1504}
1505
1506static const struct usb_gadget_ops pxa_udc_ops = {
1507 .get_frame = pxa_udc_get_frame,
1508 .wakeup = pxa_udc_wakeup,
1509 /* current versions must always be self-powered */
1510};
1511
1512/**
1513 * udc_disable - disable udc device controller
1514 * @udc: udc device
1515 *
1516 * Disables the udc device : disables clocks, udc interrupts, control endpoint
1517 * interrupts.
1518 */
1519static void udc_disable(struct pxa_udc *udc)
1520{
1521 udc_writel(udc, UDCICR0, 0);
1522 udc_writel(udc, UDCICR1, 0);
1523
1524 udc_clear_mask_UDCCR(udc, UDCCR_UDE);
1525 clk_disable(udc->clk);
1526
1527 ep0_idle(udc);
1528 udc->gadget.speed = USB_SPEED_UNKNOWN;
1529 udc->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
1530}
1531
1532/**
1533 * udc_init_data - Initialize udc device data structures
1534 * @dev: udc device
1535 *
1536 * Initializes gadget endpoint list, endpoints locks. No action is taken
1537 * on the hardware.
1538 */
1539static __init void udc_init_data(struct pxa_udc *dev)
1540{
1541 int i;
1542 struct pxa_ep *ep;
1543
1544 /* device/ep0 records init */
1545 INIT_LIST_HEAD(&dev->gadget.ep_list);
1546 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1547 dev->udc_usb_ep[0].pxa_ep = &dev->pxa_ep[0];
1548 ep0_idle(dev);
1549 strcpy(dev->dev->bus_id, "");
1550
1551 /* PXA endpoints init */
1552 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
1553 ep = &dev->pxa_ep[i];
1554
1555 ep->enabled = is_ep0(ep);
1556 INIT_LIST_HEAD(&ep->queue);
1557 spin_lock_init(&ep->lock);
1558 }
1559
1560 /* USB endpoints init */
1561 for (i = 0; i < NR_USB_ENDPOINTS; i++)
1562 if (i != 0)
1563 list_add_tail(&dev->udc_usb_ep[i].usb_ep.ep_list,
1564 &dev->gadget.ep_list);
1565}
1566
1567/**
1568 * udc_enable - Enables the udc device
1569 * @dev: udc device
1570 *
1571 * Enables the udc device : enables clocks, udc interrupts, control endpoint
1572 * interrupts, sets usb as UDC client and setups endpoints.
1573 */
1574static void udc_enable(struct pxa_udc *udc)
1575{
1576 udc_writel(udc, UDCICR0, 0);
1577 udc_writel(udc, UDCICR1, 0);
1578 udc_writel(udc, UP2OCR, UP2OCR_HXOE);
1579 udc_clear_mask_UDCCR(udc, UDCCR_UDE);
1580
1581 clk_enable(udc->clk);
1582
1583 ep0_idle(udc);
1584 udc->gadget.speed = USB_SPEED_FULL;
1585 memset(&udc->stats, 0, sizeof(udc->stats));
1586
1587 udc_set_mask_UDCCR(udc, UDCCR_UDE);
1588 udelay(2);
1589 if (udc_readl(udc, UDCCR) & UDCCR_EMCE)
1590 dev_err(udc->dev, "Configuration errors, udc disabled\n");
1591
1592 /*
1593 * Caller must be able to sleep in order to cope with startup transients
1594 */
1595 msleep(100);
1596
1597 /* enable suspend/resume and reset irqs */
1598 udc_writel(udc, UDCICR1,
1599 UDCICR1_IECC | UDCICR1_IERU
1600 | UDCICR1_IESU | UDCICR1_IERS);
1601
1602 /* enable ep0 irqs */
1603 pio_irq_enable(&udc->pxa_ep[0]);
1604
1605 dev_info(udc->dev, "UDC connecting\n");
1606 if (udc->mach->udc_command)
1607 udc->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
1608}
1609
1610/**
1611 * usb_gadget_register_driver - Register gadget driver
1612 * @driver: gadget driver
1613 *
1614 * When a driver is successfully registered, it will receive control requests
1615 * including set_configuration(), which enables non-control requests. Then
1616 * usb traffic follows until a disconnect is reported. Then a host may connect
1617 * again, or the driver might get unbound.
1618 *
1619 * Returns 0 if no error, -EINVAL, -ENODEV, -EBUSY otherwise
1620 */
1621int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1622{
1623 struct pxa_udc *udc = the_controller;
1624 int retval;
1625
1626 if (!driver || driver->speed != USB_SPEED_FULL || !driver->bind
1627 || !driver->disconnect || !driver->setup)
1628 return -EINVAL;
1629 if (!udc)
1630 return -ENODEV;
1631 if (udc->driver)
1632 return -EBUSY;
1633
1634 /* first hook up the driver ... */
1635 udc->driver = driver;
1636 udc->gadget.dev.driver = &driver->driver;
1637
1638 retval = device_add(&udc->gadget.dev);
1639 if (retval) {
1640 dev_err(udc->dev, "device_add error %d\n", retval);
1641 goto add_fail;
1642 }
1643 retval = driver->bind(&udc->gadget);
1644 if (retval) {
1645 dev_err(udc->dev, "bind to driver %s --> error %d\n",
1646 driver->driver.name, retval);
1647 goto bind_fail;
1648 }
1649 dev_dbg(udc->dev, "registered gadget driver '%s'\n",
1650 driver->driver.name);
1651
1652 udc_enable(udc);
1653 return 0;
1654
1655bind_fail:
1656 device_del(&udc->gadget.dev);
1657add_fail:
1658 udc->driver = NULL;
1659 udc->gadget.dev.driver = NULL;
1660 return retval;
1661}
1662EXPORT_SYMBOL(usb_gadget_register_driver);
1663
1664
1665/**
1666 * stop_activity - Stops udc endpoints
1667 * @udc: udc device
1668 * @driver: gadget driver
1669 *
1670 * Disables all udc endpoints (even control endpoint), report disconnect to
1671 * the gadget user.
1672 */
1673static void stop_activity(struct pxa_udc *udc, struct usb_gadget_driver *driver)
1674{
1675 int i;
1676
1677 /* don't disconnect drivers more than once */
1678 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1679 driver = NULL;
1680 udc->gadget.speed = USB_SPEED_UNKNOWN;
1681
1682 for (i = 0; i < NR_USB_ENDPOINTS; i++)
1683 pxa_ep_disable(&udc->udc_usb_ep[i].usb_ep);
1684
1685 if (driver)
1686 driver->disconnect(&udc->gadget);
1687}
1688
1689/**
1690 * usb_gadget_unregister_driver - Unregister the gadget driver
1691 * @driver: gadget driver
1692 *
1693 * Returns 0 if no error, -ENODEV, -EINVAL otherwise
1694 */
1695int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1696{
1697 struct pxa_udc *udc = the_controller;
1698
1699 if (!udc)
1700 return -ENODEV;
1701 if (!driver || driver != udc->driver || !driver->unbind)
1702 return -EINVAL;
1703
1704 stop_activity(udc, driver);
1705 udc_disable(udc);
1706
1707 driver->unbind(&udc->gadget);
1708 udc->driver = NULL;
1709
1710 device_del(&udc->gadget.dev);
1711
1712 dev_info(udc->dev, "unregistered gadget driver '%s'\n",
1713 driver->driver.name);
1714 return 0;
1715}
1716EXPORT_SYMBOL(usb_gadget_unregister_driver);
1717
1718/**
1719 * handle_ep0_ctrl_req - handle control endpoint control request
1720 * @udc: udc device
1721 * @req: control request
1722 */
1723static void handle_ep0_ctrl_req(struct pxa_udc *udc,
1724 struct pxa27x_request *req)
1725{
1726 struct pxa_ep *ep = &udc->pxa_ep[0];
1727 union {
1728 struct usb_ctrlrequest r;
1729 u32 word[2];
1730 } u;
1731 int i;
1732 int have_extrabytes = 0;
1733
1734 nuke(ep, -EPROTO);
1735
1736 /* read SETUP packet */
1737 for (i = 0; i < 2; i++) {
1738 if (unlikely(ep_is_empty(ep)))
1739 goto stall;
1740 u.word[i] = udc_ep_readl(ep, UDCDR);
1741 }
1742
1743 have_extrabytes = !ep_is_empty(ep);
1744 while (!ep_is_empty(ep)) {
1745 i = udc_ep_readl(ep, UDCDR);
1746 ep_err(ep, "wrong to have extra bytes for setup : 0x%08x\n", i);
1747 }
1748
1749 le16_to_cpus(&u.r.wValue);
1750 le16_to_cpus(&u.r.wIndex);
1751 le16_to_cpus(&u.r.wLength);
1752
1753 ep_dbg(ep, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1754 u.r.bRequestType, u.r.bRequest,
1755 u.r.wValue, u.r.wIndex, u.r.wLength);
1756 if (unlikely(have_extrabytes))
1757 goto stall;
1758
1759 if (u.r.bRequestType & USB_DIR_IN)
1760 set_ep0state(udc, IN_DATA_STAGE);
1761 else
1762 set_ep0state(udc, OUT_DATA_STAGE);
1763
1764 /* Tell UDC to enter Data Stage */
1765 udc_ep_writel(ep, UDCCSR, UDCCSR0_SA | UDCCSR0_OPC);
1766
1767 i = udc->driver->setup(&udc->gadget, &u.r);
1768 if (i < 0)
1769 goto stall;
1770out:
1771 return;
1772stall:
1773 ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n",
1774 udc_ep_readl(ep, UDCCSR), i);
1775 udc_ep_writel(ep, UDCCSR, UDCCSR0_FST | UDCCSR0_FTF);
1776 set_ep0state(udc, STALL);
1777 goto out;
1778}
1779
1780/**
1781 * handle_ep0 - Handle control endpoint data transfers
1782 * @udc: udc device
1783 * @fifo_irq: 1 if triggered by fifo service type irq
1784 * @opc_irq: 1 if triggered by output packet complete type irq
1785 *
1786 * Context : when in_interrupt() or with ep->lock held
1787 *
1788 * Tries to transfer all pending request data into the endpoint and/or
1789 * transfer all pending data in the endpoint into usb requests.
1790 * Handles states of ep0 automata.
1791 *
1792 * PXA27x hardware handles several standard usb control requests without
1793 * driver notification. The requests fully handled by hardware are :
1794 * SET_ADDRESS, SET_FEATURE, CLEAR_FEATURE, GET_CONFIGURATION, GET_INTERFACE,
1795 * GET_STATUS
1796 * The requests handled by hardware, but with irq notification are :
1797 * SYNCH_FRAME, SET_CONFIGURATION, SET_INTERFACE
1798 * The remaining standard requests really handled by handle_ep0 are :
1799 * GET_DESCRIPTOR, SET_DESCRIPTOR, specific requests.
1800 * Requests standardized outside of USB 2.0 chapter 9 are handled more
1801 * uniformly, by gadget drivers.
1802 *
1803 * The control endpoint state machine is _not_ USB spec compliant, it's even
1804 * hardly compliant with Intel PXA270 developers guide.
1805 * The key points which inferred this state machine are :
1806 * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by
1807 * software.
1808 * - on every OUT packet received, UDCCSR0_OPC is raised and held until
1809 * cleared by software.
1810 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
1811 * before reading ep0.
1812 * - irq can be called on a "packet complete" event (opc_irq=1), while
1813 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
1814 * from experimentation).
1815 * - as UDCCSR0_SA can be activated while in irq handling, and clearing
1816 * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC
1817 * => we never actually read the "status stage" packet of an IN data stage
1818 * => this is not documented in Intel documentation
1819 * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA
1820 * STAGE. The driver add STATUS STAGE to send last zero length packet in
1821 * OUT_STATUS_STAGE.
1822 * - special attention was needed for IN_STATUS_STAGE. If a packet complete
1823 * event is detected, we terminate the status stage without ackowledging the
1824 * packet (not to risk to loose a potential SETUP packet)
1825 */
1826static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
1827{
1828 u32 udccsr0;
1829 struct pxa_ep *ep = &udc->pxa_ep[0];
1830 struct pxa27x_request *req = NULL;
1831 int completed = 0;
1832
1833 udccsr0 = udc_ep_readl(ep, UDCCSR);
1834 ep_dbg(ep, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n",
1835 EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, UDCBCR),
1836 (fifo_irq << 1 | opc_irq));
1837
1838 if (!list_empty(&ep->queue))
1839 req = list_entry(ep->queue.next, struct pxa27x_request, queue);
1840
1841 if (udccsr0 & UDCCSR0_SST) {
1842 ep_dbg(ep, "clearing stall status\n");
1843 nuke(ep, -EPIPE);
1844 udc_ep_writel(ep, UDCCSR, UDCCSR0_SST);
1845 ep0_idle(udc);
1846 }
1847
1848 if (udccsr0 & UDCCSR0_SA) {
1849 nuke(ep, 0);
1850 set_ep0state(udc, SETUP_STAGE);
1851 }
1852
1853 switch (udc->ep0state) {
1854 case WAIT_FOR_SETUP:
1855 /*
1856 * Hardware bug : beware, we cannot clear OPC, since we would
1857 * miss a potential OPC irq for a setup packet.
1858 * So, we only do ... nothing, and hope for a next irq with
1859 * UDCCSR0_SA set.
1860 */
1861 break;
1862 case SETUP_STAGE:
1863 udccsr0 &= UDCCSR0_CTRL_REQ_MASK;
1864 if (likely(udccsr0 == UDCCSR0_CTRL_REQ_MASK))
1865 handle_ep0_ctrl_req(udc, req);
1866 break;
1867 case IN_DATA_STAGE: /* GET_DESCRIPTOR */
1868 if (epout_has_pkt(ep))
1869 udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC);
1870 if (req && !ep_is_full(ep))
1871 completed = write_ep0_fifo(ep, req);
1872 if (completed)
1873 ep0_end_in_req(ep, req);
1874 break;
1875 case OUT_DATA_STAGE: /* SET_DESCRIPTOR */
1876 if (epout_has_pkt(ep) && req)
1877 completed = read_ep0_fifo(ep, req);
1878 if (completed)
1879 ep0_end_out_req(ep, req);
1880 break;
1881 case STALL:
1882 udc_ep_writel(ep, UDCCSR, UDCCSR0_FST);
1883 break;
1884 case IN_STATUS_STAGE:
1885 /*
1886 * Hardware bug : beware, we cannot clear OPC, since we would
1887 * miss a potential PC irq for a setup packet.
1888 * So, we only put the ep0 into WAIT_FOR_SETUP state.
1889 */
1890 if (opc_irq)
1891 ep0_idle(udc);
1892 break;
1893 case OUT_STATUS_STAGE:
1894 case WAIT_ACK_SET_CONF_INTERF:
1895 ep_warn(ep, "should never get in %s state here!!!\n",
1896 EP0_STNAME(ep->dev));
1897 ep0_idle(udc);
1898 break;
1899 }
1900}
1901
1902/**
1903 * handle_ep - Handle endpoint data tranfers
1904 * @ep: pxa physical endpoint
1905 *
1906 * Tries to transfer all pending request data into the endpoint and/or
1907 * transfer all pending data in the endpoint into usb requests.
1908 *
1909 * Is always called when in_interrupt() or with ep->lock held.
1910 */
1911static void handle_ep(struct pxa_ep *ep)
1912{
1913 struct pxa27x_request *req;
1914 int completed;
1915 u32 udccsr;
1916 int is_in = ep->dir_in;
1917 int loop = 0;
1918
1919 do {
1920 completed = 0;
1921 udccsr = udc_ep_readl(ep, UDCCSR);
1922 if (likely(!list_empty(&ep->queue)))
1923 req = list_entry(ep->queue.next,
1924 struct pxa27x_request, queue);
1925 else
1926 req = NULL;
1927
1928 ep_dbg(ep, "req:%p, udccsr 0x%03x loop=%d\n",
1929 req, udccsr, loop++);
1930
1931 if (unlikely(udccsr & (UDCCSR_SST | UDCCSR_TRN)))
1932 udc_ep_writel(ep, UDCCSR,
1933 udccsr & (UDCCSR_SST | UDCCSR_TRN));
1934 if (!req)
1935 break;
1936
1937 if (unlikely(is_in)) {
1938 if (likely(!ep_is_full(ep)))
1939 completed = write_fifo(ep, req);
1940 if (completed)
1941 ep_end_in_req(ep, req);
1942 } else {
1943 if (likely(epout_has_pkt(ep)))
1944 completed = read_fifo(ep, req);
1945 if (completed)
1946 ep_end_out_req(ep, req);
1947 }
1948 } while (completed);
1949}
1950
1951/**
1952 * pxa27x_change_configuration - Handle SET_CONF usb request notification
1953 * @udc: udc device
1954 * @config: usb configuration
1955 *
1956 * Post the request to upper level.
1957 * Don't use any pxa specific harware configuration capabilities
1958 */
1959static void pxa27x_change_configuration(struct pxa_udc *udc, int config)
1960{
1961 struct usb_ctrlrequest req ;
1962
1963 dev_dbg(udc->dev, "config=%d\n", config);
1964
1965 udc->config = config;
1966 udc->last_interface = 0;
1967 udc->last_alternate = 0;
1968
1969 req.bRequestType = 0;
1970 req.bRequest = USB_REQ_SET_CONFIGURATION;
1971 req.wValue = config;
1972 req.wIndex = 0;
1973 req.wLength = 0;
1974
1975 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
1976 udc->driver->setup(&udc->gadget, &req);
1977}
1978
1979/**
1980 * pxa27x_change_interface - Handle SET_INTERF usb request notification
1981 * @udc: udc device
1982 * @iface: interface number
1983 * @alt: alternate setting number
1984 *
1985 * Post the request to upper level.
1986 * Don't use any pxa specific harware configuration capabilities
1987 */
1988static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt)
1989{
1990 struct usb_ctrlrequest req;
1991
1992 dev_dbg(udc->dev, "interface=%d, alternate setting=%d\n", iface, alt);
1993
1994 udc->last_interface = iface;
1995 udc->last_alternate = alt;
1996
1997 req.bRequestType = USB_RECIP_INTERFACE;
1998 req.bRequest = USB_REQ_SET_INTERFACE;
1999 req.wValue = alt;
2000 req.wIndex = iface;
2001 req.wLength = 0;
2002
2003 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
2004 udc->driver->setup(&udc->gadget, &req);
2005}
2006
2007/*
2008 * irq_handle_data - Handle data transfer
2009 * @irq: irq IRQ number
2010 * @udc: dev pxa_udc device structure
2011 *
2012 * Called from irq handler, transferts data to or from endpoint to queue
2013 */
2014static void irq_handle_data(int irq, struct pxa_udc *udc)
2015{
2016 int i;
2017 struct pxa_ep *ep;
2018 u32 udcisr0 = udc_readl(udc, UDCISR0) & UDCCISR0_EP_MASK;
2019 u32 udcisr1 = udc_readl(udc, UDCISR1) & UDCCISR1_EP_MASK;
2020
2021 if (udcisr0 & UDCISR_INT_MASK) {
2022 udc->pxa_ep[0].stats.irqs++;
2023 udc_writel(udc, UDCISR0, UDCISR_INT(0, UDCISR_INT_MASK));
2024 handle_ep0(udc, !!(udcisr0 & UDCICR_FIFOERR),
2025 !!(udcisr0 & UDCICR_PKTCOMPL));
2026 }
2027
2028 udcisr0 >>= 2;
2029 for (i = 1; udcisr0 != 0 && i < 16; udcisr0 >>= 2, i++) {
2030 if (!(udcisr0 & UDCISR_INT_MASK))
2031 continue;
2032
2033 udc_writel(udc, UDCISR0, UDCISR_INT(i, UDCISR_INT_MASK));
2034 ep = &udc->pxa_ep[i];
2035 ep->stats.irqs++;
2036 handle_ep(ep);
2037 }
2038
2039 for (i = 16; udcisr1 != 0 && i < 24; udcisr1 >>= 2, i++) {
2040 udc_writel(udc, UDCISR1, UDCISR_INT(i - 16, UDCISR_INT_MASK));
2041 if (!(udcisr1 & UDCISR_INT_MASK))
2042 continue;
2043
2044 ep = &udc->pxa_ep[i];
2045 ep->stats.irqs++;
2046 handle_ep(ep);
2047 }
2048
2049}
2050
2051/**
2052 * irq_udc_suspend - Handle IRQ "UDC Suspend"
2053 * @udc: udc device
2054 */
2055static void irq_udc_suspend(struct pxa_udc *udc)
2056{
2057 udc_writel(udc, UDCISR1, UDCISR1_IRSU);
2058 udc->stats.irqs_suspend++;
2059
2060 if (udc->gadget.speed != USB_SPEED_UNKNOWN
2061 && udc->driver && udc->driver->suspend)
2062 udc->driver->suspend(&udc->gadget);
2063 ep0_idle(udc);
2064}
2065
2066/**
2067 * irq_udc_resume - Handle IRQ "UDC Resume"
2068 * @udc: udc device
2069 */
2070static void irq_udc_resume(struct pxa_udc *udc)
2071{
2072 udc_writel(udc, UDCISR1, UDCISR1_IRRU);
2073 udc->stats.irqs_resume++;
2074
2075 if (udc->gadget.speed != USB_SPEED_UNKNOWN
2076 && udc->driver && udc->driver->resume)
2077 udc->driver->resume(&udc->gadget);
2078}
2079
2080/**
2081 * irq_udc_reconfig - Handle IRQ "UDC Change Configuration"
2082 * @udc: udc device
2083 */
2084static void irq_udc_reconfig(struct pxa_udc *udc)
2085{
2086 unsigned config, interface, alternate, config_change;
2087 u32 udccr = udc_readl(udc, UDCCR);
2088
2089 udc_writel(udc, UDCISR1, UDCISR1_IRCC);
2090 udc->stats.irqs_reconfig++;
2091
2092 config = (udccr & UDCCR_ACN) >> UDCCR_ACN_S;
2093 config_change = (config != udc->config);
2094 pxa27x_change_configuration(udc, config);
2095
2096 interface = (udccr & UDCCR_AIN) >> UDCCR_AIN_S;
2097 alternate = (udccr & UDCCR_AAISN) >> UDCCR_AAISN_S;
2098 pxa27x_change_interface(udc, interface, alternate);
2099
2100 if (config_change)
2101 update_pxa_ep_matches(udc);
2102 udc_set_mask_UDCCR(udc, UDCCR_SMAC);
2103}
2104
2105/**
2106 * irq_udc_reset - Handle IRQ "UDC Reset"
2107 * @udc: udc device
2108 */
2109static void irq_udc_reset(struct pxa_udc *udc)
2110{
2111 u32 udccr = udc_readl(udc, UDCCR);
2112 struct pxa_ep *ep = &udc->pxa_ep[0];
2113
2114 dev_info(udc->dev, "USB reset\n");
2115 udc_writel(udc, UDCISR1, UDCISR1_IRRS);
2116 udc->stats.irqs_reset++;
2117
2118 if ((udccr & UDCCR_UDA) == 0) {
2119 dev_dbg(udc->dev, "USB reset start\n");
2120 stop_activity(udc, udc->driver);
2121 }
2122 udc->gadget.speed = USB_SPEED_FULL;
2123 memset(&udc->stats, 0, sizeof udc->stats);
2124
2125 nuke(ep, -EPROTO);
2126 udc_ep_writel(ep, UDCCSR, UDCCSR0_FTF | UDCCSR0_OPC);
2127 ep0_idle(udc);
2128}
2129
2130/**
2131 * pxa_udc_irq - Main irq handler
2132 * @irq: irq number
2133 * @_dev: udc device
2134 *
2135 * Handles all udc interrupts
2136 */
2137static irqreturn_t pxa_udc_irq(int irq, void *_dev)
2138{
2139 struct pxa_udc *udc = _dev;
2140 u32 udcisr0 = udc_readl(udc, UDCISR0);
2141 u32 udcisr1 = udc_readl(udc, UDCISR1);
2142 u32 udccr = udc_readl(udc, UDCCR);
2143 u32 udcisr1_spec;
2144
2145 dev_vdbg(udc->dev, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, "
2146 "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr);
2147
2148 udcisr1_spec = udcisr1 & 0xf8000000;
2149 if (unlikely(udcisr1_spec & UDCISR1_IRSU))
2150 irq_udc_suspend(udc);
2151 if (unlikely(udcisr1_spec & UDCISR1_IRRU))
2152 irq_udc_resume(udc);
2153 if (unlikely(udcisr1_spec & UDCISR1_IRCC))
2154 irq_udc_reconfig(udc);
2155 if (unlikely(udcisr1_spec & UDCISR1_IRRS))
2156 irq_udc_reset(udc);
2157
2158 if ((udcisr0 & UDCCISR0_EP_MASK) | (udcisr1 & UDCCISR1_EP_MASK))
2159 irq_handle_data(irq, udc);
2160
2161 return IRQ_HANDLED;
2162}
2163
2164static struct pxa_udc memory = {
2165 .gadget = {
2166 .ops = &pxa_udc_ops,
2167 .ep0 = &memory.udc_usb_ep[0].usb_ep,
2168 .name = driver_name,
2169 .dev = {
2170 .bus_id = "gadget",
2171 },
2172 },
2173
2174 .udc_usb_ep = {
2175 USB_EP_CTRL,
2176 USB_EP_OUT_BULK(1),
2177 USB_EP_IN_BULK(2),
2178 USB_EP_IN_ISO(3),
2179 USB_EP_OUT_ISO(4),
2180 USB_EP_IN_INT(5),
2181 },
2182
2183 .pxa_ep = {
2184 PXA_EP_CTRL,
2185 /* Endpoints for gadget zero */
2186 PXA_EP_OUT_BULK(1, 1, 3, 0, 0),
2187 PXA_EP_IN_BULK(2, 2, 3, 0, 0),
2188 /* Endpoints for ether gadget, file storage gadget */
2189 PXA_EP_OUT_BULK(3, 1, 1, 0, 0),
2190 PXA_EP_IN_BULK(4, 2, 1, 0, 0),
2191 PXA_EP_IN_ISO(5, 3, 1, 0, 0),
2192 PXA_EP_OUT_ISO(6, 4, 1, 0, 0),
2193 PXA_EP_IN_INT(7, 5, 1, 0, 0),
2194 /* Endpoints for RNDIS, serial */
2195 PXA_EP_OUT_BULK(8, 1, 2, 0, 0),
2196 PXA_EP_IN_BULK(9, 2, 2, 0, 0),
2197 PXA_EP_IN_INT(10, 5, 2, 0, 0),
2198 /*
2199 * All the following endpoints are only for completion. They
2200 * won't never work, as multiple interfaces are really broken on
2201 * the pxa.
2202 */
2203 PXA_EP_OUT_BULK(11, 1, 2, 1, 0),
2204 PXA_EP_IN_BULK(12, 2, 2, 1, 0),
2205 /* Endpoint for CDC Ether */
2206 PXA_EP_OUT_BULK(13, 1, 1, 1, 1),
2207 PXA_EP_IN_BULK(14, 2, 1, 1, 1),
2208 }
2209};
2210
2211/**
2212 * pxa_udc_probe - probes the udc device
2213 * @_dev: platform device
2214 *
2215 * Perform basic init : allocates udc clock, creates sysfs files, requests
2216 * irq.
2217 */
2218static int __init pxa_udc_probe(struct platform_device *pdev)
2219{
2220 struct resource *regs;
2221 struct pxa_udc *udc = &memory;
2222 int retval;
2223
2224 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2225 if (!regs)
2226 return -ENXIO;
2227 udc->irq = platform_get_irq(pdev, 0);
2228 if (udc->irq < 0)
2229 return udc->irq;
2230
2231 udc->dev = &pdev->dev;
2232 udc->mach = pdev->dev.platform_data;
2233
2234 udc->clk = clk_get(&pdev->dev, "UDCCLK");
2235 if (IS_ERR(udc->clk)) {
2236 retval = PTR_ERR(udc->clk);
2237 goto err_clk;
2238 }
2239
2240 retval = -ENOMEM;
2241 udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
2242 if (!udc->regs) {
2243 dev_err(&pdev->dev, "Unable to map UDC I/O memory\n");
2244 goto err_map;
2245 }
2246
2247 device_initialize(&udc->gadget.dev);
2248 udc->gadget.dev.parent = &pdev->dev;
2249 udc->gadget.dev.dma_mask = NULL;
2250
2251 the_controller = udc;
2252 platform_set_drvdata(pdev, udc);
2253 udc_init_data(udc);
2254 pxa_eps_setup(udc);
2255
2256 /* irq setup after old hardware state is cleaned up */
2257 retval = request_irq(udc->irq, pxa_udc_irq,
2258 IRQF_SHARED, driver_name, udc);
2259 if (retval != 0) {
2260 dev_err(udc->dev, "%s: can't get irq %i, err %d\n",
2261 driver_name, IRQ_USB, retval);
2262 goto err_irq;
2263 }
2264
2265 pxa_init_debugfs(udc);
2266 return 0;
2267err_irq:
2268 iounmap(udc->regs);
2269err_map:
2270 clk_put(udc->clk);
2271 udc->clk = NULL;
2272err_clk:
2273 return retval;
2274}
2275
2276/**
2277 * pxa_udc_remove - removes the udc device driver
2278 * @_dev: platform device
2279 */
2280static int __exit pxa_udc_remove(struct platform_device *_dev)
2281{
2282 struct pxa_udc *udc = platform_get_drvdata(_dev);
2283
2284 usb_gadget_unregister_driver(udc->driver);
2285 free_irq(udc->irq, udc);
2286 pxa_cleanup_debugfs(udc);
2287
2288 platform_set_drvdata(_dev, NULL);
2289 the_controller = NULL;
2290 clk_put(udc->clk);
2291
2292 return 0;
2293}
2294
2295static void pxa_udc_shutdown(struct platform_device *_dev)
2296{
2297 struct pxa_udc *udc = platform_get_drvdata(_dev);
2298
2299 udc_disable(udc);
2300}
2301
2302#ifdef CONFIG_PM
2303/**
2304 * pxa_udc_suspend - Suspend udc device
2305 * @_dev: platform device
2306 * @state: suspend state
2307 *
2308 * Suspends udc : saves configuration registers (UDCCR*), then disables the udc
2309 * device.
2310 */
2311static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state)
2312{
2313 int i;
2314 struct pxa_udc *udc = platform_get_drvdata(_dev);
2315 struct pxa_ep *ep;
2316
2317 ep = &udc->pxa_ep[0];
2318 udc->udccsr0 = udc_ep_readl(ep, UDCCSR);
2319 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
2320 ep = &udc->pxa_ep[i];
2321 ep->udccsr_value = udc_ep_readl(ep, UDCCSR);
2322 ep->udccr_value = udc_ep_readl(ep, UDCCR);
2323 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n",
2324 ep->udccsr_value, ep->udccr_value);
2325 }
2326
2327 udc_disable(udc);
2328
2329 return 0;
2330}
2331
2332/**
2333 * pxa_udc_resume - Resume udc device
2334 * @_dev: platform device
2335 *
2336 * Resumes udc : restores configuration registers (UDCCR*), then enables the udc
2337 * device.
2338 */
2339static int pxa_udc_resume(struct platform_device *_dev)
2340{
2341 int i;
2342 struct pxa_udc *udc = platform_get_drvdata(_dev);
2343 struct pxa_ep *ep;
2344
2345 ep = &udc->pxa_ep[0];
2346 udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME));
2347 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
2348 ep = &udc->pxa_ep[i];
2349 udc_ep_writel(ep, UDCCSR, ep->udccsr_value);
2350 udc_ep_writel(ep, UDCCR, ep->udccr_value);
2351 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n",
2352 ep->udccsr_value, ep->udccr_value);
2353 }
2354
2355 udc_enable(udc);
2356 /*
2357 * We do not handle OTG yet.
2358 *
2359 * OTGPH bit is set when sleep mode is entered.
2360 * it indicates that OTG pad is retaining its state.
2361 * Upon exit from sleep mode and before clearing OTGPH,
2362 * Software must configure the USB OTG pad, UDC, and UHC
2363 * to the state they were in before entering sleep mode.
2364 *
2365 * Should be : PSSR |= PSSR_OTGPH;
2366 */
2367
2368 return 0;
2369}
2370#endif
2371
2372/* work with hotplug and coldplug */
2373MODULE_ALIAS("platform:pxa2xx-udc");
2374
2375static struct platform_driver udc_driver = {
2376 .driver = {
2377 .name = "pxa2xx-udc",
2378 .owner = THIS_MODULE,
2379 },
2380 .remove = __exit_p(pxa_udc_remove),
2381 .shutdown = pxa_udc_shutdown,
2382#ifdef CONFIG_PM
2383 .suspend = pxa_udc_suspend,
2384 .resume = pxa_udc_resume
2385#endif
2386};
2387
2388static int __init udc_init(void)
2389{
2390 printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2391 return platform_driver_probe(&udc_driver, pxa_udc_probe);
2392}
2393module_init(udc_init);
2394
2395
2396static void __exit udc_exit(void)
2397{
2398 platform_driver_unregister(&udc_driver);
2399}
2400module_exit(udc_exit);
2401
2402MODULE_DESCRIPTION(DRIVER_DESC);
2403MODULE_AUTHOR("Robert Jarzmik");
2404MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h
new file mode 100644
index 000000000000..1d1b7936ee11
--- /dev/null
+++ b/drivers/usb/gadget/pxa27x_udc.h
@@ -0,0 +1,487 @@
1/*
2 * linux/drivers/usb/gadget/pxa27x_udc.h
3 * Intel PXA27x on-chip full speed USB device controller
4 *
5 * Inspired by original driver by Frank Becker, David Brownell, and others.
6 * Copyright (C) 2008 Robert Jarzmik
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __LINUX_USB_GADGET_PXA27X_H
24#define __LINUX_USB_GADGET_PXA27X_H
25
26#include <linux/types.h>
27#include <linux/spinlock.h>
28#include <linux/io.h>
29
30/*
31 * Register definitions
32 */
33/* Offsets */
34#define UDCCR 0x0000 /* UDC Control Register */
35#define UDCICR0 0x0004 /* UDC Interrupt Control Register0 */
36#define UDCICR1 0x0008 /* UDC Interrupt Control Register1 */
37#define UDCISR0 0x000C /* UDC Interrupt Status Register 0 */
38#define UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */
39#define UDCFNR 0x0014 /* UDC Frame Number Register */
40#define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */
41#define UP2OCR 0x0020 /* USB Port 2 Output Control register */
42#define UP3OCR 0x0024 /* USB Port 3 Output Control register */
43#define UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */
44#define UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */
45#define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */
46#define UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */
47
48#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
49#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
50 Protocol Port Support */
51#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
52 Support */
53#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
54 Enable */
55#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
56#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
57#define UDCCR_ACN_S 11
58#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
59#define UDCCR_AIN_S 8
60#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
61 Setting Number */
62#define UDCCR_AAISN_S 5
63#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
64 Configuration */
65#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
66 Error */
67#define UDCCR_UDR (1 << 2) /* UDC Resume */
68#define UDCCR_UDA (1 << 1) /* UDC Active */
69#define UDCCR_UDE (1 << 0) /* UDC Enable */
70
71#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
72#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
73#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
74#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
75#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
76#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
77#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
78#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
79#define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
80
81#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
82#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
83#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
84#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
85#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
86#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
87#define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
88
89#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
90#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
91 Rising Edge Interrupt Enable */
92#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
93 Falling Edge Interrupt Enable */
94#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
95 Interrupt Enable */
96#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
97 Interrupt Enable */
98#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
99 Interrupt Enable */
100#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
101 Interrupt Enable */
102#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
103 Interrupt Enable */
104#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
105 Interrupt Enable */
106#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
107 Edge Interrupt Enable */
108#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
109 Edge Interrupt Enable */
110#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
111 Interrupt Enable */
112#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
113 Interrupt Enable */
114
115/* Host Port 2 field bits */
116#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
117#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
118 /* Transceiver enablers */
119#define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */
120#define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */
121#define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */
122#define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */
123#define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */
124#define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */
125#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
126#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
127#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
128#define UP2OCR_HXS (1 << 16) /* Transceiver Output Select */
129#define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */
130#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
131
132#define UDCCSR0_SA (1 << 7) /* Setup Active */
133#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
134#define UDCCSR0_FST (1 << 5) /* Force Stall */
135#define UDCCSR0_SST (1 << 4) /* Sent Stall */
136#define UDCCSR0_DME (1 << 3) /* DMA Enable */
137#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
138#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
139#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
140
141#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
142#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
143#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
144#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
145#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
146#define UDCCSR_FST (1 << 5) /* Force STALL */
147#define UDCCSR_SST (1 << 4) /* Sent STALL */
148#define UDCCSR_DME (1 << 3) /* DMA Enable */
149#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
150#define UDCCSR_PC (1 << 1) /* Packet Complete */
151#define UDCCSR_FS (1 << 0) /* FIFO needs service */
152
153#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
154#define UDCCONR_CN_S 25
155#define UDCCONR_IN (0x07 << 22) /* Interface Number */
156#define UDCCONR_IN_S 22
157#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
158#define UDCCONR_AISN_S 19
159#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
160#define UDCCONR_EN_S 15
161#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
162#define UDCCONR_ET_S 13
163#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
164#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
165#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
166#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
167#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
168#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
169#define UDCCONR_MPS_S 2
170#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
171#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
172
173#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE)
174#define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST)
175#define UDC_FNR_MASK (0x7ff)
176#define UDC_BCR_MASK (0x3ff)
177
178/*
179 * UDCCR = UDC Endpoint Configuration Registers
180 * UDCCSR = UDC Control/Status Register for this EP
181 * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo)
182 * UDCDR = UDC Endpoint Data Register (the fifo)
183 */
184#define ofs_UDCCR(ep) (UDCCRn(ep->idx))
185#define ofs_UDCCSR(ep) (UDCCSRn(ep->idx))
186#define ofs_UDCBCR(ep) (UDCBCRn(ep->idx))
187#define ofs_UDCDR(ep) (UDCDRn(ep->idx))
188
189/* Register access macros */
190#define udc_ep_readl(ep, reg) \
191 __raw_readl((ep)->dev->regs + ofs_##reg(ep))
192#define udc_ep_writel(ep, reg, value) \
193 __raw_writel((value), ep->dev->regs + ofs_##reg(ep))
194#define udc_ep_readb(ep, reg) \
195 __raw_readb((ep)->dev->regs + ofs_##reg(ep))
196#define udc_ep_writeb(ep, reg, value) \
197 __raw_writeb((value), ep->dev->regs + ofs_##reg(ep))
198#define udc_readl(dev, reg) \
199 __raw_readl((dev)->regs + (reg))
200#define udc_writel(udc, reg, value) \
201 __raw_writel((value), (udc)->regs + (reg))
202
203#define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME)
204#define UDCCISR0_EP_MASK ~0
205#define UDCCISR1_EP_MASK 0xffff
206#define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)
207
208#define EPIDX(ep) (ep->idx)
209#define EPADDR(ep) (ep->addr)
210#define EPXFERTYPE(ep) (ep->type)
211#define EPNAME(ep) (ep->name)
212#define is_ep0(ep) (!ep->idx)
213#define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)
214
215/*
216 * Endpoint definitions
217 *
218 * Once enabled, pxa endpoint configuration is freezed, and cannot change
219 * unless a reset happens or the udc is disabled.
220 * Therefore, we must define all pxa potential endpoint definitions needed for
221 * all gadget and set them up before the udc is enabled.
222 *
223 * As the architecture chosen is fully static, meaning the pxa endpoint
224 * configurations are set up once and for all, we must provide a way to match
225 * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget
226 * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt)
227 * criteria, while the pxa architecture requires that.
228 *
229 * The solution is to define several pxa endpoints matching one usb_ep. Ex:
230 * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when
231 * the udc talks on (config=3, interface=0, alt=0)
232 * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when
233 * the udc talks on (config=3, interface=0, alt=1)
234 * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when
235 * the udc talks on (config=2, interface=0, alt=0)
236 *
237 * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...)
238 */
239
240/*
241 * Endpoint definition helpers
242 */
243#define USB_EP_DEF(addr, bname, dir, type, maxpkt) \
244{ .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \
245 .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \
246 .bmAttributes = type, \
247 .wMaxPacketSize = maxpkt, }, \
248 .dev = &memory \
249}
250#define USB_EP_BULK(addr, bname, dir) \
251 USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE)
252#define USB_EP_ISO(addr, bname, dir) \
253 USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE)
254#define USB_EP_INT(addr, bname, dir) \
255 USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE)
256#define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1)
257#define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0)
258#define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1)
259#define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0)
260#define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1)
261#define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE)
262
263#define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \
264{ \
265 .dev = &memory, \
266 .name = "ep" #_idx, \
267 .idx = _idx, .enabled = 0, \
268 .dir_in = dir, .addr = _addr, \
269 .config = _config, .interface = iface, .alternate = altset, \
270 .type = _type, .fifo_size = maxpkt, \
271}
272#define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \
273 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
274 config, iface, alt)
275#define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \
276 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
277 config, iface, alt)
278#define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \
279 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
280 config, iface, alt)
281#define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a)
282#define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a)
283#define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a)
284#define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a)
285#define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a)
286#define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)
287
288struct pxa27x_udc;
289
290struct stats {
291 unsigned long in_ops;
292 unsigned long out_ops;
293 unsigned long in_bytes;
294 unsigned long out_bytes;
295 unsigned long irqs;
296};
297
298/**
299 * struct udc_usb_ep - container of each usb_ep structure
300 * @usb_ep: usb endpoint
301 * @desc: usb descriptor, especially type and address
302 * @dev: udc managing this endpoint
303 * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call)
304 */
305struct udc_usb_ep {
306 struct usb_ep usb_ep;
307 struct usb_endpoint_descriptor desc;
308 struct pxa_udc *dev;
309 struct pxa_ep *pxa_ep;
310};
311
312/**
313 * struct pxa_ep - pxa endpoint
314 * @dev: udc device
315 * @queue: requests queue
316 * @lock: lock to pxa_ep data (queues and stats)
317 * @enabled: true when endpoint enabled (not stopped by gadget layer)
318 * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX)
319 * @name: endpoint name (for trace/debug purpose)
320 * @dir_in: 1 if IN endpoint, 0 if OUT endpoint
321 * @addr: usb endpoint number
322 * @config: configuration in which this endpoint is active
323 * @interface: interface in which this endpoint is active
324 * @alternate: altsetting in which this endpoitn is active
325 * @fifo_size: max packet size in the endpoint fifo
326 * @type: endpoint type (bulk, iso, int, ...)
327 * @udccsr_value: save register of UDCCSR0 for suspend/resume
328 * @udccr_value: save register of UDCCR for suspend/resume
329 * @stats: endpoint statistics
330 *
331 * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned
332 * (cares about config/interface/altsetting, thus placing needless limits on
333 * device capability) and full of implementation bugs forcing it to be set up
334 * for use more or less like a pxa255.
335 *
336 * As we define the pxa_ep statically, we must guess all needed pxa_ep for all
337 * gadget which may work with this udc driver.
338 */
339struct pxa_ep {
340 struct pxa_udc *dev;
341
342 struct list_head queue;
343 spinlock_t lock; /* Protects this structure */
344 /* (queues, stats) */
345 unsigned enabled:1;
346
347 unsigned idx:5;
348 char *name;
349
350 /*
351 * Specific pxa endpoint data, needed for hardware initialization
352 */
353 unsigned dir_in:1;
354 unsigned addr:3;
355 unsigned config:2;
356 unsigned interface:3;
357 unsigned alternate:3;
358 unsigned fifo_size;
359 unsigned type;
360
361#ifdef CONFIG_PM
362 u32 udccsr_value;
363 u32 udccr_value;
364#endif
365 struct stats stats;
366};
367
368/**
369 * struct pxa27x_request - container of each usb_request structure
370 * @req: usb request
371 * @udc_usb_ep: usb endpoint the request was submitted on
372 * @in_use: sanity check if request already queued on an pxa_ep
373 * @queue: linked list of requests, linked on pxa_ep->queue
374 */
375struct pxa27x_request {
376 struct usb_request req;
377 struct udc_usb_ep *udc_usb_ep;
378 unsigned in_use:1;
379 struct list_head queue;
380};
381
382enum ep0_state {
383 WAIT_FOR_SETUP,
384 SETUP_STAGE,
385 IN_DATA_STAGE,
386 OUT_DATA_STAGE,
387 IN_STATUS_STAGE,
388 OUT_STATUS_STAGE,
389 STALL,
390 WAIT_ACK_SET_CONF_INTERF
391};
392
393static char *ep0_state_name[] = {
394 "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE",
395 "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL",
396 "WAIT_ACK_SET_CONF_INTERF"
397};
398#define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
399
400#define EP0_FIFO_SIZE 16U
401#define BULK_FIFO_SIZE 64U
402#define ISO_FIFO_SIZE 256U
403#define INT_FIFO_SIZE 16U
404
405struct udc_stats {
406 unsigned long irqs_reset;
407 unsigned long irqs_suspend;
408 unsigned long irqs_resume;
409 unsigned long irqs_reconfig;
410};
411
412#define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */
413#define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */
414
415/**
416 * struct pxa_udc - udc structure
417 * @regs: mapped IO space
418 * @irq: udc irq
419 * @clk: udc clock
420 * @usb_gadget: udc gadget structure
421 * @driver: bound gadget (zero, g_ether, g_file_storage, ...)
422 * @dev: device
423 * @mach: machine info, used to activate specific GPIO
424 * @ep0state: control endpoint state machine state
425 * @stats: statistics on udc usage
426 * @udc_usb_ep: array of usb endpoints offered by the gadget
427 * @pxa_ep: array of pxa available endpoints
428 * @config: UDC active configuration
429 * @last_interface: UDC interface of the last SET_INTERFACE host request
430 * @last_alternate: UDC altsetting of the last SET_INTERFACE host request
431 * @udccsr0: save of udccsr0 in case of suspend
432 * @debugfs_root: root entry of debug filesystem
433 * @debugfs_state: debugfs entry for "udcstate"
434 * @debugfs_queues: debugfs entry for "queues"
435 * @debugfs_eps: debugfs entry for "epstate"
436 */
437struct pxa_udc {
438 void __iomem *regs;
439 int irq;
440 struct clk *clk;
441
442 struct usb_gadget gadget;
443 struct usb_gadget_driver *driver;
444 struct device *dev;
445 struct pxa2xx_udc_mach_info *mach;
446
447 enum ep0_state ep0state;
448 struct udc_stats stats;
449
450 struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS];
451 struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS];
452
453 unsigned config:2;
454 unsigned last_interface:3;
455 unsigned last_alternate:3;
456
457#ifdef CONFIG_PM
458 unsigned udccsr0;
459#endif
460#ifdef CONFIG_USB_GADGET_DEBUG_FS
461 struct dentry *debugfs_root;
462 struct dentry *debugfs_state;
463 struct dentry *debugfs_queues;
464 struct dentry *debugfs_eps;
465#endif
466};
467
468static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
469{
470 return container_of(gadget, struct pxa_udc, gadget);
471}
472
473/*
474 * Debugging/message support
475 */
476#define ep_dbg(ep, fmt, arg...) \
477 dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
478#define ep_vdbg(ep, fmt, arg...) \
479 dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
480#define ep_err(ep, fmt, arg...) \
481 dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
482#define ep_info(ep, fmt, arg...) \
483 dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
484#define ep_warn(ep, fmt, arg...) \
485 dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
486
487#endif /* __LINUX_USB_GADGET_PXA27X_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-05 11:21:23 -0400