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authorLukasz Majewski <l.majewski@samsung.com>2012-05-04 08:17:14 -0400
committerFelipe Balbi <balbi@ti.com>2012-05-04 08:53:17 -0400
commit94cb8fd637d7ec4a6685365c3287050969389cbe (patch)
tree68acde862fdbe021baf53a8d40ddf386b9d4e52e /drivers/usb
parentf026a52d4309e1e08752a8bd41ac74aeea815686 (diff)
usb:hsotg:samsung: Remove the S3C_ prefix from registers definition.
This code removes the S3C_ prefix from s3c-hsotg driver. This change provides more architecture independent code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/gadget/s3c-hsotg.c634
-rw-r--r--drivers/usb/gadget/s3c-hsotg.h718
2 files changed, 675 insertions, 677 deletions
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 520dc3db612b..34599dff37ff 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -256,14 +256,14 @@ static inline bool using_dma(struct s3c_hsotg *hsotg)
256 */ 256 */
257static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints) 257static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
258{ 258{
259 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK); 259 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
260 u32 new_gsintmsk; 260 u32 new_gsintmsk;
261 261
262 new_gsintmsk = gsintmsk | ints; 262 new_gsintmsk = gsintmsk | ints;
263 263
264 if (new_gsintmsk != gsintmsk) { 264 if (new_gsintmsk != gsintmsk) {
265 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); 265 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
266 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK); 266 writel(new_gsintmsk, hsotg->regs + GINTMSK);
267 } 267 }
268} 268}
269 269
@@ -274,13 +274,13 @@ static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
274 */ 274 */
275static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints) 275static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
276{ 276{
277 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK); 277 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
278 u32 new_gsintmsk; 278 u32 new_gsintmsk;
279 279
280 new_gsintmsk = gsintmsk & ~ints; 280 new_gsintmsk = gsintmsk & ~ints;
281 281
282 if (new_gsintmsk != gsintmsk) 282 if (new_gsintmsk != gsintmsk)
283 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK); 283 writel(new_gsintmsk, hsotg->regs + GINTMSK);
284} 284}
285 285
286/** 286/**
@@ -305,12 +305,12 @@ static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
305 bit <<= 16; 305 bit <<= 16;
306 306
307 local_irq_save(flags); 307 local_irq_save(flags);
308 daint = readl(hsotg->regs + S3C_DAINTMSK); 308 daint = readl(hsotg->regs + DAINTMSK);
309 if (en) 309 if (en)
310 daint |= bit; 310 daint |= bit;
311 else 311 else
312 daint &= ~bit; 312 daint &= ~bit;
313 writel(daint, hsotg->regs + S3C_DAINTMSK); 313 writel(daint, hsotg->regs + DAINTMSK);
314 local_irq_restore(flags); 314 local_irq_restore(flags);
315} 315}
316 316
@@ -328,10 +328,10 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
328 328
329 /* set FIFO sizes to 2048/1024 */ 329 /* set FIFO sizes to 2048/1024 */
330 330
331 writel(2048, hsotg->regs + S3C_GRXFSIZ); 331 writel(2048, hsotg->regs + GRXFSIZ);
332 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) | 332 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
333 S3C_GNPTXFSIZ_NPTxFDep(1024), 333 GNPTXFSIZ_NPTxFDep(1024),
334 hsotg->regs + S3C_GNPTXFSIZ); 334 hsotg->regs + GNPTXFSIZ);
335 335
336 /* 336 /*
337 * arange all the rest of the TX FIFOs, as some versions of this 337 * arange all the rest of the TX FIFOs, as some versions of this
@@ -351,10 +351,10 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
351 351
352 for (ep = 1; ep <= 15; ep++) { 352 for (ep = 1; ep <= 15; ep++) {
353 val = addr; 353 val = addr;
354 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT; 354 val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
355 addr += size; 355 addr += size;
356 356
357 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep)); 357 writel(val, hsotg->regs + DPTXFSIZn(ep));
358 } 358 }
359 359
360 /* 360 /*
@@ -362,15 +362,15 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
362 * all fifos are flushed before continuing 362 * all fifos are flushed before continuing
363 */ 363 */
364 364
365 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh | 365 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
366 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL); 366 GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
367 367
368 /* wait until the fifos are both flushed */ 368 /* wait until the fifos are both flushed */
369 timeout = 100; 369 timeout = 100;
370 while (1) { 370 while (1) {
371 val = readl(hsotg->regs + S3C_GRSTCTL); 371 val = readl(hsotg->regs + GRSTCTL);
372 372
373 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0) 373 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
374 break; 374 break;
375 375
376 if (--timeout == 0) { 376 if (--timeout == 0) {
@@ -473,7 +473,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
473 struct s3c_hsotg_req *hs_req) 473 struct s3c_hsotg_req *hs_req)
474{ 474{
475 bool periodic = is_ep_periodic(hs_ep); 475 bool periodic = is_ep_periodic(hs_ep);
476 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS); 476 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
477 int buf_pos = hs_req->req.actual; 477 int buf_pos = hs_req->req.actual;
478 int to_write = hs_ep->size_loaded; 478 int to_write = hs_ep->size_loaded;
479 void *data; 479 void *data;
@@ -487,7 +487,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
487 return 0; 487 return 0;
488 488
489 if (periodic && !hsotg->dedicated_fifos) { 489 if (periodic && !hsotg->dedicated_fifos) {
490 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index)); 490 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
491 int size_left; 491 int size_left;
492 int size_done; 492 int size_done;
493 493
@@ -496,14 +496,14 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
496 * how much data is left in the fifo. 496 * how much data is left in the fifo.
497 */ 497 */
498 498
499 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); 499 size_left = DxEPTSIZ_XferSize_GET(epsize);
500 500
501 /* 501 /*
502 * if shared fifo, we cannot write anything until the 502 * if shared fifo, we cannot write anything until the
503 * previous data has been completely sent. 503 * previous data has been completely sent.
504 */ 504 */
505 if (hs_ep->fifo_load != 0) { 505 if (hs_ep->fifo_load != 0) {
506 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp); 506 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
507 return -ENOSPC; 507 return -ENOSPC;
508 } 508 }
509 509
@@ -524,25 +524,25 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
524 __func__, can_write); 524 __func__, can_write);
525 525
526 if (can_write <= 0) { 526 if (can_write <= 0) {
527 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp); 527 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
528 return -ENOSPC; 528 return -ENOSPC;
529 } 529 }
530 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { 530 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
531 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index)); 531 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
532 532
533 can_write &= 0xffff; 533 can_write &= 0xffff;
534 can_write *= 4; 534 can_write *= 4;
535 } else { 535 } else {
536 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) { 536 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
537 dev_dbg(hsotg->dev, 537 dev_dbg(hsotg->dev,
538 "%s: no queue slots available (0x%08x)\n", 538 "%s: no queue slots available (0x%08x)\n",
539 __func__, gnptxsts); 539 __func__, gnptxsts);
540 540
541 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp); 541 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
542 return -ENOSPC; 542 return -ENOSPC;
543 } 543 }
544 544
545 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts); 545 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
546 can_write *= 4; /* fifo size is in 32bit quantities. */ 546 can_write *= 4; /* fifo size is in 32bit quantities. */
547 } 547 }
548 548
@@ -566,8 +566,8 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
566 to_write = hs_ep->ep.maxpacket; 566 to_write = hs_ep->ep.maxpacket;
567 567
568 s3c_hsotg_en_gsint(hsotg, 568 s3c_hsotg_en_gsint(hsotg,
569 periodic ? S3C_GINTSTS_PTxFEmp : 569 periodic ? GINTSTS_PTxFEmp :
570 S3C_GINTSTS_NPTxFEmp); 570 GINTSTS_NPTxFEmp);
571 } 571 }
572 572
573 /* see if we can write data */ 573 /* see if we can write data */
@@ -593,8 +593,8 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
593 */ 593 */
594 594
595 s3c_hsotg_en_gsint(hsotg, 595 s3c_hsotg_en_gsint(hsotg,
596 periodic ? S3C_GINTSTS_PTxFEmp : 596 periodic ? GINTSTS_PTxFEmp :
597 S3C_GINTSTS_NPTxFEmp); 597 GINTSTS_NPTxFEmp);
598 } 598 }
599 599
600 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", 600 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
@@ -612,7 +612,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
612 to_write = DIV_ROUND_UP(to_write, 4); 612 to_write = DIV_ROUND_UP(to_write, 4);
613 data = hs_req->req.buf + buf_pos; 613 data = hs_req->req.buf + buf_pos;
614 614
615 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write); 615 writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
616 616
617 return (to_write >= can_write) ? -ENOSPC : 0; 617 return (to_write >= can_write) ? -ENOSPC : 0;
618} 618}
@@ -631,12 +631,12 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
631 unsigned maxpkt; 631 unsigned maxpkt;
632 632
633 if (index != 0) { 633 if (index != 0) {
634 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1; 634 maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
635 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1; 635 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
636 } else { 636 } else {
637 maxsize = 64+64; 637 maxsize = 64+64;
638 if (hs_ep->dir_in) 638 if (hs_ep->dir_in)
639 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1; 639 maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
640 else 640 else
641 maxpkt = 2; 641 maxpkt = 2;
642 } 642 }
@@ -695,8 +695,8 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
695 } 695 }
696 } 696 }
697 697
698 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); 698 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
699 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index); 699 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
700 700
701 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", 701 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
702 __func__, readl(hsotg->regs + epctrl_reg), index, 702 __func__, readl(hsotg->regs + epctrl_reg), index,
@@ -705,7 +705,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
705 /* If endpoint is stalled, we will restart request later */ 705 /* If endpoint is stalled, we will restart request later */
706 ctrl = readl(hsotg->regs + epctrl_reg); 706 ctrl = readl(hsotg->regs + epctrl_reg);
707 707
708 if (ctrl & S3C_DxEPCTL_Stall) { 708 if (ctrl & DxEPCTL_Stall) {
709 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); 709 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
710 return; 710 return;
711 } 711 }
@@ -739,7 +739,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
739 packets = 1; /* send one packet if length is zero. */ 739 packets = 1; /* send one packet if length is zero. */
740 740
741 if (dir_in && index != 0) 741 if (dir_in && index != 0)
742 epsize = S3C_DxEPTSIZ_MC(1); 742 epsize = DxEPTSIZ_MC(1);
743 else 743 else
744 epsize = 0; 744 epsize = 0;
745 745
@@ -753,8 +753,8 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
753 packets++; 753 packets++;
754 } 754 }
755 755
756 epsize |= S3C_DxEPTSIZ_PktCnt(packets); 756 epsize |= DxEPTSIZ_PktCnt(packets);
757 epsize |= S3C_DxEPTSIZ_XferSize(length); 757 epsize |= DxEPTSIZ_XferSize(length);
758 758
759 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", 759 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
760 __func__, packets, length, ureq->length, epsize, epsize_reg); 760 __func__, packets, length, ureq->length, epsize, epsize_reg);
@@ -773,15 +773,15 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
773 * synced by s3c_hsotg_ep_queue(). 773 * synced by s3c_hsotg_ep_queue().
774 */ 774 */
775 775
776 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index); 776 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
777 writel(ureq->dma, hsotg->regs + dma_reg); 777 writel(ureq->dma, hsotg->regs + dma_reg);
778 778
779 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n", 779 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
780 __func__, ureq->dma, dma_reg); 780 __func__, ureq->dma, dma_reg);
781 } 781 }
782 782
783 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */ 783 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
784 ctrl |= S3C_DxEPCTL_USBActEp; 784 ctrl |= DxEPCTL_USBActEp;
785 785
786 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup); 786 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
787 787
@@ -789,7 +789,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
789 if (hsotg->setup && index == 0) 789 if (hsotg->setup && index == 0)
790 hsotg->setup = 0; 790 hsotg->setup = 0;
791 else 791 else
792 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */ 792 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
793 793
794 794
795 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 795 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
@@ -815,8 +815,8 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
815 * to debugging to see what is going on. 815 * to debugging to see what is going on.
816 */ 816 */
817 if (dir_in) 817 if (dir_in)
818 writel(S3C_DIEPMSK_INTknTXFEmpMsk, 818 writel(DIEPMSK_INTknTXFEmpMsk,
819 hsotg->regs + S3C_DIEPINT(index)); 819 hsotg->regs + DIEPINT(index));
820 820
821 /* 821 /*
822 * Note, trying to clear the NAK here causes problems with transmit 822 * Note, trying to clear the NAK here causes problems with transmit
@@ -824,7 +824,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
824 */ 824 */
825 825
826 /* check ep is enabled */ 826 /* check ep is enabled */
827 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna)) 827 if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
828 dev_warn(hsotg->dev, 828 dev_warn(hsotg->dev,
829 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n", 829 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
830 index, readl(hsotg->regs + epctrl_reg)); 830 index, readl(hsotg->regs + epctrl_reg));
@@ -1209,10 +1209,10 @@ static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1209 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1209 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1210 switch (ctrl->bRequest) { 1210 switch (ctrl->bRequest) {
1211 case USB_REQ_SET_ADDRESS: 1211 case USB_REQ_SET_ADDRESS:
1212 dcfg = readl(hsotg->regs + S3C_DCFG); 1212 dcfg = readl(hsotg->regs + DCFG);
1213 dcfg &= ~S3C_DCFG_DevAddr_MASK; 1213 dcfg &= ~DCFG_DevAddr_MASK;
1214 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT; 1214 dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
1215 writel(dcfg, hsotg->regs + S3C_DCFG); 1215 writel(dcfg, hsotg->regs + DCFG);
1216 1216
1217 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); 1217 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1218 1218
@@ -1248,16 +1248,16 @@ static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1248 u32 ctrl; 1248 u32 ctrl;
1249 1249
1250 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); 1250 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1251 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0; 1251 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1252 1252
1253 /* 1253 /*
1254 * S3C_DxEPCTL_Stall will be cleared by EP once it has 1254 * DxEPCTL_Stall will be cleared by EP once it has
1255 * taken effect, so no need to clear later. 1255 * taken effect, so no need to clear later.
1256 */ 1256 */
1257 1257
1258 ctrl = readl(hsotg->regs + reg); 1258 ctrl = readl(hsotg->regs + reg);
1259 ctrl |= S3C_DxEPCTL_Stall; 1259 ctrl |= DxEPCTL_Stall;
1260 ctrl |= S3C_DxEPCTL_CNAK; 1260 ctrl |= DxEPCTL_CNAK;
1261 writel(ctrl, hsotg->regs + reg); 1261 writel(ctrl, hsotg->regs + reg);
1262 1262
1263 dev_dbg(hsotg->dev, 1263 dev_dbg(hsotg->dev,
@@ -1439,13 +1439,13 @@ static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1439{ 1439{
1440 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx]; 1440 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1441 struct s3c_hsotg_req *hs_req = hs_ep->req; 1441 struct s3c_hsotg_req *hs_req = hs_ep->req;
1442 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx); 1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1443 int to_read; 1443 int to_read;
1444 int max_req; 1444 int max_req;
1445 int read_ptr; 1445 int read_ptr;
1446 1446
1447 if (!hs_req) { 1447 if (!hs_req) {
1448 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx)); 1448 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1449 int ptr; 1449 int ptr;
1450 1450
1451 dev_warn(hsotg->dev, 1451 dev_warn(hsotg->dev,
@@ -1525,14 +1525,14 @@ static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1525 dev_dbg(hsotg->dev, "sending zero-length packet\n"); 1525 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1526 1526
1527 /* issue a zero-sized packet to terminate this */ 1527 /* issue a zero-sized packet to terminate this */
1528 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) | 1528 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1529 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0)); 1529 DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
1530 1530
1531 ctrl = readl(hsotg->regs + S3C_DIEPCTL0); 1531 ctrl = readl(hsotg->regs + DIEPCTL0);
1532 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */ 1532 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
1533 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */ 1533 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
1534 ctrl |= S3C_DxEPCTL_USBActEp; 1534 ctrl |= DxEPCTL_USBActEp;
1535 writel(ctrl, hsotg->regs + S3C_DIEPCTL0); 1535 writel(ctrl, hsotg->regs + DIEPCTL0);
1536} 1536}
1537 1537
1538/** 1538/**
@@ -1548,11 +1548,11 @@ static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1548static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg, 1548static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1549 int epnum, bool was_setup) 1549 int epnum, bool was_setup)
1550{ 1550{
1551 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum)); 1551 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1552 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; 1552 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1553 struct s3c_hsotg_req *hs_req = hs_ep->req; 1553 struct s3c_hsotg_req *hs_req = hs_ep->req;
1554 struct usb_request *req = &hs_req->req; 1554 struct usb_request *req = &hs_req->req;
1555 unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); 1555 unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
1556 int result = 0; 1556 int result = 0;
1557 1557
1558 if (!hs_req) { 1558 if (!hs_req) {
@@ -1622,9 +1622,9 @@ static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1622{ 1622{
1623 u32 dsts; 1623 u32 dsts;
1624 1624
1625 dsts = readl(hsotg->regs + S3C_DSTS); 1625 dsts = readl(hsotg->regs + DSTS);
1626 dsts &= S3C_DSTS_SOFFN_MASK; 1626 dsts &= DSTS_SOFFN_MASK;
1627 dsts >>= S3C_DSTS_SOFFN_SHIFT; 1627 dsts >>= DSTS_SOFFN_SHIFT;
1628 1628
1629 return dsts; 1629 return dsts;
1630} 1630}
@@ -1647,29 +1647,29 @@ static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1647 */ 1647 */
1648static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg) 1648static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1649{ 1649{
1650 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP); 1650 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1651 u32 epnum, status, size; 1651 u32 epnum, status, size;
1652 1652
1653 WARN_ON(using_dma(hsotg)); 1653 WARN_ON(using_dma(hsotg));
1654 1654
1655 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK; 1655 epnum = grxstsr & GRXSTS_EPNum_MASK;
1656 status = grxstsr & S3C_GRXSTS_PktSts_MASK; 1656 status = grxstsr & GRXSTS_PktSts_MASK;
1657 1657
1658 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK; 1658 size = grxstsr & GRXSTS_ByteCnt_MASK;
1659 size >>= S3C_GRXSTS_ByteCnt_SHIFT; 1659 size >>= GRXSTS_ByteCnt_SHIFT;
1660 1660
1661 if (1) 1661 if (1)
1662 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", 1662 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1663 __func__, grxstsr, size, epnum); 1663 __func__, grxstsr, size, epnum);
1664 1664
1665#define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT) 1665#define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1666 1666
1667 switch (status >> S3C_GRXSTS_PktSts_SHIFT) { 1667 switch (status >> GRXSTS_PktSts_SHIFT) {
1668 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK): 1668 case __status(GRXSTS_PktSts_GlobalOutNAK):
1669 dev_dbg(hsotg->dev, "GlobalOutNAK\n"); 1669 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1670 break; 1670 break;
1671 1671
1672 case __status(S3C_GRXSTS_PktSts_OutDone): 1672 case __status(GRXSTS_PktSts_OutDone):
1673 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", 1673 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1674 s3c_hsotg_read_frameno(hsotg)); 1674 s3c_hsotg_read_frameno(hsotg));
1675 1675
@@ -1677,24 +1677,24 @@ static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1677 s3c_hsotg_handle_outdone(hsotg, epnum, false); 1677 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1678 break; 1678 break;
1679 1679
1680 case __status(S3C_GRXSTS_PktSts_SetupDone): 1680 case __status(GRXSTS_PktSts_SetupDone):
1681 dev_dbg(hsotg->dev, 1681 dev_dbg(hsotg->dev,
1682 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 1682 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1683 s3c_hsotg_read_frameno(hsotg), 1683 s3c_hsotg_read_frameno(hsotg),
1684 readl(hsotg->regs + S3C_DOEPCTL(0))); 1684 readl(hsotg->regs + DOEPCTL(0)));
1685 1685
1686 s3c_hsotg_handle_outdone(hsotg, epnum, true); 1686 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1687 break; 1687 break;
1688 1688
1689 case __status(S3C_GRXSTS_PktSts_OutRX): 1689 case __status(GRXSTS_PktSts_OutRX):
1690 s3c_hsotg_rx_data(hsotg, epnum, size); 1690 s3c_hsotg_rx_data(hsotg, epnum, size);
1691 break; 1691 break;
1692 1692
1693 case __status(S3C_GRXSTS_PktSts_SetupRX): 1693 case __status(GRXSTS_PktSts_SetupRX):
1694 dev_dbg(hsotg->dev, 1694 dev_dbg(hsotg->dev,
1695 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 1695 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1696 s3c_hsotg_read_frameno(hsotg), 1696 s3c_hsotg_read_frameno(hsotg),
1697 readl(hsotg->regs + S3C_DOEPCTL(0))); 1697 readl(hsotg->regs + DOEPCTL(0)));
1698 1698
1699 s3c_hsotg_rx_data(hsotg, epnum, size); 1699 s3c_hsotg_rx_data(hsotg, epnum, size);
1700 break; 1700 break;
@@ -1716,13 +1716,13 @@ static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1716{ 1716{
1717 switch (mps) { 1717 switch (mps) {
1718 case 64: 1718 case 64:
1719 return S3C_D0EPCTL_MPS_64; 1719 return D0EPCTL_MPS_64;
1720 case 32: 1720 case 32:
1721 return S3C_D0EPCTL_MPS_32; 1721 return D0EPCTL_MPS_32;
1722 case 16: 1722 case 16:
1723 return S3C_D0EPCTL_MPS_16; 1723 return D0EPCTL_MPS_16;
1724 case 8: 1724 case 8:
1725 return S3C_D0EPCTL_MPS_8; 1725 return D0EPCTL_MPS_8;
1726 } 1726 }
1727 1727
1728 /* bad max packet size, warn and return invalid result */ 1728 /* bad max packet size, warn and return invalid result */
@@ -1753,7 +1753,7 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1753 if (mpsval > 3) 1753 if (mpsval > 3)
1754 goto bad_mps; 1754 goto bad_mps;
1755 } else { 1755 } else {
1756 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1) 1756 if (mps >= DxEPCTL_MPS_LIMIT+1)
1757 goto bad_mps; 1757 goto bad_mps;
1758 1758
1759 mpsval = mps; 1759 mpsval = mps;
@@ -1766,16 +1766,16 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1766 * if one of the directions may not be in use. 1766 * if one of the directions may not be in use.
1767 */ 1767 */
1768 1768
1769 reg = readl(regs + S3C_DIEPCTL(ep)); 1769 reg = readl(regs + DIEPCTL(ep));
1770 reg &= ~S3C_DxEPCTL_MPS_MASK; 1770 reg &= ~DxEPCTL_MPS_MASK;
1771 reg |= mpsval; 1771 reg |= mpsval;
1772 writel(reg, regs + S3C_DIEPCTL(ep)); 1772 writel(reg, regs + DIEPCTL(ep));
1773 1773
1774 if (ep) { 1774 if (ep) {
1775 reg = readl(regs + S3C_DOEPCTL(ep)); 1775 reg = readl(regs + DOEPCTL(ep));
1776 reg &= ~S3C_DxEPCTL_MPS_MASK; 1776 reg &= ~DxEPCTL_MPS_MASK;
1777 reg |= mpsval; 1777 reg |= mpsval;
1778 writel(reg, regs + S3C_DOEPCTL(ep)); 1778 writel(reg, regs + DOEPCTL(ep));
1779 } 1779 }
1780 1780
1781 return; 1781 return;
@@ -1794,16 +1794,16 @@ static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1794 int timeout; 1794 int timeout;
1795 int val; 1795 int val;
1796 1796
1797 writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh, 1797 writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
1798 hsotg->regs + S3C_GRSTCTL); 1798 hsotg->regs + GRSTCTL);
1799 1799
1800 /* wait until the fifo is flushed */ 1800 /* wait until the fifo is flushed */
1801 timeout = 100; 1801 timeout = 100;
1802 1802
1803 while (1) { 1803 while (1) {
1804 val = readl(hsotg->regs + S3C_GRSTCTL); 1804 val = readl(hsotg->regs + GRSTCTL);
1805 1805
1806 if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0) 1806 if ((val & (GRSTCTL_TxFFlsh)) == 0)
1807 break; 1807 break;
1808 1808
1809 if (--timeout == 0) { 1809 if (--timeout == 0) {
@@ -1853,7 +1853,7 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1853 struct s3c_hsotg_ep *hs_ep) 1853 struct s3c_hsotg_ep *hs_ep)
1854{ 1854{
1855 struct s3c_hsotg_req *hs_req = hs_ep->req; 1855 struct s3c_hsotg_req *hs_req = hs_ep->req;
1856 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index)); 1856 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1857 int size_left, size_done; 1857 int size_left, size_done;
1858 1858
1859 if (!hs_req) { 1859 if (!hs_req) {
@@ -1878,7 +1878,7 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1878 * aligned). 1878 * aligned).
1879 */ 1879 */
1880 1880
1881 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); 1881 size_left = DxEPTSIZ_XferSize_GET(epsize);
1882 1882
1883 size_done = hs_ep->size_loaded - size_left; 1883 size_done = hs_ep->size_loaded - size_left;
1884 size_done += hs_ep->last_load; 1884 size_done += hs_ep->last_load;
@@ -1930,9 +1930,9 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1930 int dir_in) 1930 int dir_in)
1931{ 1931{
1932 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx]; 1932 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1933 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx); 1933 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1934 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx); 1934 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1935 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx); 1935 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1936 u32 ints; 1936 u32 ints;
1937 1937
1938 ints = readl(hsotg->regs + epint_reg); 1938 ints = readl(hsotg->regs + epint_reg);
@@ -1943,7 +1943,7 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1943 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", 1943 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1944 __func__, idx, dir_in ? "in" : "out", ints); 1944 __func__, idx, dir_in ? "in" : "out", ints);
1945 1945
1946 if (ints & S3C_DxEPINT_XferCompl) { 1946 if (ints & DxEPINT_XferCompl) {
1947 dev_dbg(hsotg->dev, 1947 dev_dbg(hsotg->dev,
1948 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n", 1948 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1949 __func__, readl(hsotg->regs + epctl_reg), 1949 __func__, readl(hsotg->regs + epctl_reg),
@@ -1968,7 +1968,7 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1968 } 1968 }
1969 } 1969 }
1970 1970
1971 if (ints & S3C_DxEPINT_EPDisbld) { 1971 if (ints & DxEPINT_EPDisbld) {
1972 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); 1972 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1973 1973
1974 if (dir_in) { 1974 if (dir_in) {
@@ -1976,20 +1976,20 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1976 1976
1977 s3c_hsotg_txfifo_flush(hsotg, idx); 1977 s3c_hsotg_txfifo_flush(hsotg, idx);
1978 1978
1979 if ((epctl & S3C_DxEPCTL_Stall) && 1979 if ((epctl & DxEPCTL_Stall) &&
1980 (epctl & S3C_DxEPCTL_EPType_Bulk)) { 1980 (epctl & DxEPCTL_EPType_Bulk)) {
1981 int dctl = readl(hsotg->regs + S3C_DCTL); 1981 int dctl = readl(hsotg->regs + DCTL);
1982 1982
1983 dctl |= S3C_DCTL_CGNPInNAK; 1983 dctl |= DCTL_CGNPInNAK;
1984 writel(dctl, hsotg->regs + S3C_DCTL); 1984 writel(dctl, hsotg->regs + DCTL);
1985 } 1985 }
1986 } 1986 }
1987 } 1987 }
1988 1988
1989 if (ints & S3C_DxEPINT_AHBErr) 1989 if (ints & DxEPINT_AHBErr)
1990 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); 1990 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1991 1991
1992 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */ 1992 if (ints & DxEPINT_Setup) { /* Setup or Timeout */
1993 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); 1993 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1994 1994
1995 if (using_dma(hsotg) && idx == 0) { 1995 if (using_dma(hsotg) && idx == 0) {
@@ -2007,25 +2007,25 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
2007 } 2007 }
2008 } 2008 }
2009 2009
2010 if (ints & S3C_DxEPINT_Back2BackSetup) 2010 if (ints & DxEPINT_Back2BackSetup)
2011 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); 2011 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2012 2012
2013 if (dir_in) { 2013 if (dir_in) {
2014 /* not sure if this is important, but we'll clear it anyway */ 2014 /* not sure if this is important, but we'll clear it anyway */
2015 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) { 2015 if (ints & DIEPMSK_INTknTXFEmpMsk) {
2016 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", 2016 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2017 __func__, idx); 2017 __func__, idx);
2018 } 2018 }
2019 2019
2020 /* this probably means something bad is happening */ 2020 /* this probably means something bad is happening */
2021 if (ints & S3C_DIEPMSK_INTknEPMisMsk) { 2021 if (ints & DIEPMSK_INTknEPMisMsk) {
2022 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", 2022 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2023 __func__, idx); 2023 __func__, idx);
2024 } 2024 }
2025 2025
2026 /* FIFO has space or is empty (see GAHBCFG) */ 2026 /* FIFO has space or is empty (see GAHBCFG) */
2027 if (hsotg->dedicated_fifos && 2027 if (hsotg->dedicated_fifos &&
2028 ints & S3C_DIEPMSK_TxFIFOEmpty) { 2028 ints & DIEPMSK_TxFIFOEmpty) {
2029 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", 2029 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2030 __func__, idx); 2030 __func__, idx);
2031 if (!using_dma(hsotg)) 2031 if (!using_dma(hsotg))
@@ -2043,7 +2043,7 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
2043 */ 2043 */
2044static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg) 2044static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2045{ 2045{
2046 u32 dsts = readl(hsotg->regs + S3C_DSTS); 2046 u32 dsts = readl(hsotg->regs + DSTS);
2047 int ep0_mps = 0, ep_mps; 2047 int ep0_mps = 0, ep_mps;
2048 2048
2049 /* 2049 /*
@@ -2061,21 +2061,21 @@ static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2061 */ 2061 */
2062 2062
2063 /* catch both EnumSpd_FS and EnumSpd_FS48 */ 2063 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2064 switch (dsts & S3C_DSTS_EnumSpd_MASK) { 2064 switch (dsts & DSTS_EnumSpd_MASK) {
2065 case S3C_DSTS_EnumSpd_FS: 2065 case DSTS_EnumSpd_FS:
2066 case S3C_DSTS_EnumSpd_FS48: 2066 case DSTS_EnumSpd_FS48:
2067 hsotg->gadget.speed = USB_SPEED_FULL; 2067 hsotg->gadget.speed = USB_SPEED_FULL;
2068 ep0_mps = EP0_MPS_LIMIT; 2068 ep0_mps = EP0_MPS_LIMIT;
2069 ep_mps = 64; 2069 ep_mps = 64;
2070 break; 2070 break;
2071 2071
2072 case S3C_DSTS_EnumSpd_HS: 2072 case DSTS_EnumSpd_HS:
2073 hsotg->gadget.speed = USB_SPEED_HIGH; 2073 hsotg->gadget.speed = USB_SPEED_HIGH;
2074 ep0_mps = EP0_MPS_LIMIT; 2074 ep0_mps = EP0_MPS_LIMIT;
2075 ep_mps = 512; 2075 ep_mps = 512;
2076 break; 2076 break;
2077 2077
2078 case S3C_DSTS_EnumSpd_LS: 2078 case DSTS_EnumSpd_LS:
2079 hsotg->gadget.speed = USB_SPEED_LOW; 2079 hsotg->gadget.speed = USB_SPEED_LOW;
2080 /* 2080 /*
2081 * note, we don't actually support LS in this driver at the 2081 * note, we don't actually support LS in this driver at the
@@ -2104,8 +2104,8 @@ static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2104 s3c_hsotg_enqueue_setup(hsotg); 2104 s3c_hsotg_enqueue_setup(hsotg);
2105 2105
2106 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 2106 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2107 readl(hsotg->regs + S3C_DIEPCTL0), 2107 readl(hsotg->regs + DIEPCTL0),
2108 readl(hsotg->regs + S3C_DOEPCTL0)); 2108 readl(hsotg->regs + DOEPCTL0));
2109} 2109}
2110 2110
2111/** 2111/**
@@ -2195,9 +2195,9 @@ static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2195} 2195}
2196 2196
2197/* IRQ flags which will trigger a retry around the IRQ loop */ 2197/* IRQ flags which will trigger a retry around the IRQ loop */
2198#define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \ 2198#define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2199 S3C_GINTSTS_PTxFEmp | \ 2199 GINTSTS_PTxFEmp | \
2200 S3C_GINTSTS_RxFLvl) 2200 GINTSTS_RxFLvl)
2201 2201
2202/** 2202/**
2203 * s3c_hsotg_corereset - issue softreset to the core 2203 * s3c_hsotg_corereset - issue softreset to the core
@@ -2213,14 +2213,14 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2213 dev_dbg(hsotg->dev, "resetting core\n"); 2213 dev_dbg(hsotg->dev, "resetting core\n");
2214 2214
2215 /* issue soft reset */ 2215 /* issue soft reset */
2216 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL); 2216 writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
2217 2217
2218 timeout = 1000; 2218 timeout = 1000;
2219 do { 2219 do {
2220 grstctl = readl(hsotg->regs + S3C_GRSTCTL); 2220 grstctl = readl(hsotg->regs + GRSTCTL);
2221 } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0); 2221 } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
2222 2222
2223 if (grstctl & S3C_GRSTCTL_CSftRst) { 2223 if (grstctl & GRSTCTL_CSftRst) {
2224 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); 2224 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2225 return -EINVAL; 2225 return -EINVAL;
2226 } 2226 }
@@ -2228,7 +2228,7 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2228 timeout = 1000; 2228 timeout = 1000;
2229 2229
2230 while (1) { 2230 while (1) {
2231 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL); 2231 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2232 2232
2233 if (timeout-- < 0) { 2233 if (timeout-- < 0) {
2234 dev_info(hsotg->dev, 2234 dev_info(hsotg->dev,
@@ -2237,7 +2237,7 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2237 return -ETIMEDOUT; 2237 return -ETIMEDOUT;
2238 } 2238 }
2239 2239
2240 if (!(grstctl & S3C_GRSTCTL_AHBIdle)) 2240 if (!(grstctl & GRSTCTL_AHBIdle))
2241 continue; 2241 continue;
2242 2242
2243 break; /* reset done */ 2243 break; /* reset done */
@@ -2263,34 +2263,34 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2263 */ 2263 */
2264 2264
2265 /* set the PLL on, remove the HNP/SRP and set the PHY */ 2265 /* set the PLL on, remove the HNP/SRP and set the PHY */
2266 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | 2266 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
2267 (0x5 << 10), hsotg->regs + S3C_GUSBCFG); 2267 (0x5 << 10), hsotg->regs + GUSBCFG);
2268 2268
2269 s3c_hsotg_init_fifo(hsotg); 2269 s3c_hsotg_init_fifo(hsotg);
2270 2270
2271 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); 2271 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2272 2272
2273 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG); 2273 writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG);
2274 2274
2275 /* Clear any pending OTG interrupts */ 2275 /* Clear any pending OTG interrupts */
2276 writel(0xffffffff, hsotg->regs + S3C_GOTGINT); 2276 writel(0xffffffff, hsotg->regs + GOTGINT);
2277 2277
2278 /* Clear any pending interrupts */ 2278 /* Clear any pending interrupts */
2279 writel(0xffffffff, hsotg->regs + S3C_GINTSTS); 2279 writel(0xffffffff, hsotg->regs + GINTSTS);
2280 2280
2281 writel(S3C_GINTSTS_ErlySusp | S3C_GINTSTS_SessReqInt | 2281 writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
2282 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff | 2282 GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
2283 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst | 2283 GINTSTS_ConIDStsChng | GINTSTS_USBRst |
2284 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt | 2284 GINTSTS_EnumDone | GINTSTS_OTGInt |
2285 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt, 2285 GINTSTS_USBSusp | GINTSTS_WkUpInt,
2286 hsotg->regs + S3C_GINTMSK); 2286 hsotg->regs + GINTMSK);
2287 2287
2288 if (using_dma(hsotg)) 2288 if (using_dma(hsotg))
2289 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn | 2289 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
2290 S3C_GAHBCFG_HBstLen_Incr4, 2290 GAHBCFG_HBstLen_Incr4,
2291 hsotg->regs + S3C_GAHBCFG); 2291 hsotg->regs + GAHBCFG);
2292 else 2292 else
2293 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG); 2293 writel(GAHBCFG_GlblIntrEn, hsotg->regs + GAHBCFG);
2294 2294
2295 /* 2295 /*
2296 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end 2296 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
@@ -2298,30 +2298,30 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2298 * endpoint to try and read data. 2298 * endpoint to try and read data.
2299 */ 2299 */
2300 2300
2301 writel(((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0) | 2301 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty : 0) |
2302 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk | 2302 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
2303 S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk | 2303 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2304 S3C_DIEPMSK_INTknEPMisMsk, 2304 DIEPMSK_INTknEPMisMsk,
2305 hsotg->regs + S3C_DIEPMSK); 2305 hsotg->regs + DIEPMSK);
2306 2306
2307 /* 2307 /*
2308 * don't need XferCompl, we get that from RXFIFO in slave mode. In 2308 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2309 * DMA mode we may need this. 2309 * DMA mode we may need this.
2310 */ 2310 */
2311 writel((using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk | 2311 writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
2312 S3C_DIEPMSK_TimeOUTMsk) : 0) | 2312 DIEPMSK_TimeOUTMsk) : 0) |
2313 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_AHBErrMsk | 2313 DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
2314 S3C_DOEPMSK_SetupMsk, 2314 DOEPMSK_SetupMsk,
2315 hsotg->regs + S3C_DOEPMSK); 2315 hsotg->regs + DOEPMSK);
2316 2316
2317 writel(0, hsotg->regs + S3C_DAINTMSK); 2317 writel(0, hsotg->regs + DAINTMSK);
2318 2318
2319 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 2319 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2320 readl(hsotg->regs + S3C_DIEPCTL0), 2320 readl(hsotg->regs + DIEPCTL0),
2321 readl(hsotg->regs + S3C_DOEPCTL0)); 2321 readl(hsotg->regs + DOEPCTL0));
2322 2322
2323 /* enable in and out endpoint interrupts */ 2323 /* enable in and out endpoint interrupts */
2324 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt); 2324 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
2325 2325
2326 /* 2326 /*
2327 * Enable the RXFIFO when in slave mode, as this is how we collect 2327 * Enable the RXFIFO when in slave mode, as this is how we collect
@@ -2329,51 +2329,51 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2329 * things we cannot process, so do not use it. 2329 * things we cannot process, so do not use it.
2330 */ 2330 */
2331 if (!using_dma(hsotg)) 2331 if (!using_dma(hsotg))
2332 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl); 2332 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
2333 2333
2334 /* Enable interrupts for EP0 in and out */ 2334 /* Enable interrupts for EP0 in and out */
2335 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); 2335 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2336 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); 2336 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2337 2337
2338 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone); 2338 __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2339 udelay(10); /* see openiboot */ 2339 udelay(10); /* see openiboot */
2340 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone); 2340 __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2341 2341
2342 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL)); 2342 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2343 2343
2344 /* 2344 /*
2345 * S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by 2345 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2346 * writing to the EPCTL register.. 2346 * writing to the EPCTL register..
2347 */ 2347 */
2348 2348
2349 /* set to read 1 8byte packet */ 2349 /* set to read 1 8byte packet */
2350 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) | 2350 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2351 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0); 2351 DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2352 2352
2353 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | 2353 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2354 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna | 2354 DxEPCTL_CNAK | DxEPCTL_EPEna |
2355 S3C_DxEPCTL_USBActEp, 2355 DxEPCTL_USBActEp,
2356 hsotg->regs + S3C_DOEPCTL0); 2356 hsotg->regs + DOEPCTL0);
2357 2357
2358 /* enable, but don't activate EP0in */ 2358 /* enable, but don't activate EP0in */
2359 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | 2359 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2360 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0); 2360 DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
2361 2361
2362 s3c_hsotg_enqueue_setup(hsotg); 2362 s3c_hsotg_enqueue_setup(hsotg);
2363 2363
2364 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 2364 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2365 readl(hsotg->regs + S3C_DIEPCTL0), 2365 readl(hsotg->regs + DIEPCTL0),
2366 readl(hsotg->regs + S3C_DOEPCTL0)); 2366 readl(hsotg->regs + DOEPCTL0));
2367 2367
2368 /* clear global NAKs */ 2368 /* clear global NAKs */
2369 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK, 2369 writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
2370 hsotg->regs + S3C_DCTL); 2370 hsotg->regs + DCTL);
2371 2371
2372 /* must be at-least 3ms to allow bus to see disconnect */ 2372 /* must be at-least 3ms to allow bus to see disconnect */
2373 mdelay(3); 2373 mdelay(3);
2374 2374
2375 /* remove the soft-disconnect and let's go */ 2375 /* remove the soft-disconnect and let's go */
2376 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); 2376 __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
2377} 2377}
2378 2378
2379/** 2379/**
@@ -2389,45 +2389,45 @@ static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2389 u32 gintmsk; 2389 u32 gintmsk;
2390 2390
2391irq_retry: 2391irq_retry:
2392 gintsts = readl(hsotg->regs + S3C_GINTSTS); 2392 gintsts = readl(hsotg->regs + GINTSTS);
2393 gintmsk = readl(hsotg->regs + S3C_GINTMSK); 2393 gintmsk = readl(hsotg->regs + GINTMSK);
2394 2394
2395 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", 2395 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2396 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); 2396 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2397 2397
2398 gintsts &= gintmsk; 2398 gintsts &= gintmsk;
2399 2399
2400 if (gintsts & S3C_GINTSTS_OTGInt) { 2400 if (gintsts & GINTSTS_OTGInt) {
2401 u32 otgint = readl(hsotg->regs + S3C_GOTGINT); 2401 u32 otgint = readl(hsotg->regs + GOTGINT);
2402 2402
2403 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); 2403 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2404 2404
2405 writel(otgint, hsotg->regs + S3C_GOTGINT); 2405 writel(otgint, hsotg->regs + GOTGINT);
2406 } 2406 }
2407 2407
2408 if (gintsts & S3C_GINTSTS_SessReqInt) { 2408 if (gintsts & GINTSTS_SessReqInt) {
2409 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); 2409 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2410 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS); 2410 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
2411 } 2411 }
2412 2412
2413 if (gintsts & S3C_GINTSTS_EnumDone) { 2413 if (gintsts & GINTSTS_EnumDone) {
2414 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS); 2414 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
2415 2415
2416 s3c_hsotg_irq_enumdone(hsotg); 2416 s3c_hsotg_irq_enumdone(hsotg);
2417 } 2417 }
2418 2418
2419 if (gintsts & S3C_GINTSTS_ConIDStsChng) { 2419 if (gintsts & GINTSTS_ConIDStsChng) {
2420 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", 2420 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2421 readl(hsotg->regs + S3C_DSTS), 2421 readl(hsotg->regs + DSTS),
2422 readl(hsotg->regs + S3C_GOTGCTL)); 2422 readl(hsotg->regs + GOTGCTL));
2423 2423
2424 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS); 2424 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
2425 } 2425 }
2426 2426
2427 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) { 2427 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
2428 u32 daint = readl(hsotg->regs + S3C_DAINT); 2428 u32 daint = readl(hsotg->regs + DAINT);
2429 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT; 2429 u32 daint_out = daint >> DAINT_OutEP_SHIFT;
2430 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT); 2430 u32 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
2431 int ep; 2431 int ep;
2432 2432
2433 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); 2433 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
@@ -2443,17 +2443,17 @@ irq_retry:
2443 } 2443 }
2444 } 2444 }
2445 2445
2446 if (gintsts & S3C_GINTSTS_USBRst) { 2446 if (gintsts & GINTSTS_USBRst) {
2447 2447
2448 u32 usb_status = readl(hsotg->regs + S3C_GOTGCTL); 2448 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2449 2449
2450 dev_info(hsotg->dev, "%s: USBRst\n", __func__); 2450 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2451 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", 2451 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2452 readl(hsotg->regs + S3C_GNPTXSTS)); 2452 readl(hsotg->regs + GNPTXSTS));
2453 2453
2454 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS); 2454 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
2455 2455
2456 if (usb_status & S3C_GOTGCTL_BSESVLD) { 2456 if (usb_status & GOTGCTL_BSESVLD) {
2457 if (time_after(jiffies, hsotg->last_rst + 2457 if (time_after(jiffies, hsotg->last_rst +
2458 msecs_to_jiffies(200))) { 2458 msecs_to_jiffies(200))) {
2459 2459
@@ -2468,7 +2468,7 @@ irq_retry:
2468 2468
2469 /* check both FIFOs */ 2469 /* check both FIFOs */
2470 2470
2471 if (gintsts & S3C_GINTSTS_NPTxFEmp) { 2471 if (gintsts & GINTSTS_NPTxFEmp) {
2472 dev_dbg(hsotg->dev, "NPTxFEmp\n"); 2472 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2473 2473
2474 /* 2474 /*
@@ -2477,20 +2477,20 @@ irq_retry:
2477 * it needs re-enabling 2477 * it needs re-enabling
2478 */ 2478 */
2479 2479
2480 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp); 2480 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
2481 s3c_hsotg_irq_fifoempty(hsotg, false); 2481 s3c_hsotg_irq_fifoempty(hsotg, false);
2482 } 2482 }
2483 2483
2484 if (gintsts & S3C_GINTSTS_PTxFEmp) { 2484 if (gintsts & GINTSTS_PTxFEmp) {
2485 dev_dbg(hsotg->dev, "PTxFEmp\n"); 2485 dev_dbg(hsotg->dev, "PTxFEmp\n");
2486 2486
2487 /* See note in S3C_GINTSTS_NPTxFEmp */ 2487 /* See note in GINTSTS_NPTxFEmp */
2488 2488
2489 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp); 2489 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
2490 s3c_hsotg_irq_fifoempty(hsotg, true); 2490 s3c_hsotg_irq_fifoempty(hsotg, true);
2491 } 2491 }
2492 2492
2493 if (gintsts & S3C_GINTSTS_RxFLvl) { 2493 if (gintsts & GINTSTS_RxFLvl) {
2494 /* 2494 /*
2495 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, 2495 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2496 * we need to retry s3c_hsotg_handle_rx if this is still 2496 * we need to retry s3c_hsotg_handle_rx if this is still
@@ -2500,29 +2500,29 @@ irq_retry:
2500 s3c_hsotg_handle_rx(hsotg); 2500 s3c_hsotg_handle_rx(hsotg);
2501 } 2501 }
2502 2502
2503 if (gintsts & S3C_GINTSTS_ModeMis) { 2503 if (gintsts & GINTSTS_ModeMis) {
2504 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); 2504 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2505 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS); 2505 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
2506 } 2506 }
2507 2507
2508 if (gintsts & S3C_GINTSTS_USBSusp) { 2508 if (gintsts & GINTSTS_USBSusp) {
2509 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n"); 2509 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2510 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS); 2510 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
2511 2511
2512 call_gadget(hsotg, suspend); 2512 call_gadget(hsotg, suspend);
2513 s3c_hsotg_disconnect(hsotg); 2513 s3c_hsotg_disconnect(hsotg);
2514 } 2514 }
2515 2515
2516 if (gintsts & S3C_GINTSTS_WkUpInt) { 2516 if (gintsts & GINTSTS_WkUpInt) {
2517 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n"); 2517 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2518 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS); 2518 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
2519 2519
2520 call_gadget(hsotg, resume); 2520 call_gadget(hsotg, resume);
2521 } 2521 }
2522 2522
2523 if (gintsts & S3C_GINTSTS_ErlySusp) { 2523 if (gintsts & GINTSTS_ErlySusp) {
2524 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n"); 2524 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2525 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS); 2525 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
2526 2526
2527 s3c_hsotg_disconnect(hsotg); 2527 s3c_hsotg_disconnect(hsotg);
2528 } 2528 }
@@ -2533,18 +2533,18 @@ irq_retry:
2533 * the occurrence. 2533 * the occurrence.
2534 */ 2534 */
2535 2535
2536 if (gintsts & S3C_GINTSTS_GOUTNakEff) { 2536 if (gintsts & GINTSTS_GOUTNakEff) {
2537 dev_info(hsotg->dev, "GOUTNakEff triggered\n"); 2537 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2538 2538
2539 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL); 2539 writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
2540 2540
2541 s3c_hsotg_dump(hsotg); 2541 s3c_hsotg_dump(hsotg);
2542 } 2542 }
2543 2543
2544 if (gintsts & S3C_GINTSTS_GINNakEff) { 2544 if (gintsts & GINTSTS_GINNakEff) {
2545 dev_info(hsotg->dev, "GINNakEff triggered\n"); 2545 dev_info(hsotg->dev, "GINNakEff triggered\n");
2546 2546
2547 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL); 2547 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
2548 2548
2549 s3c_hsotg_dump(hsotg); 2549 s3c_hsotg_dump(hsotg);
2550 } 2550 }
@@ -2598,7 +2598,7 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2598 2598
2599 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ 2599 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2600 2600
2601 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); 2601 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2602 epctrl = readl(hsotg->regs + epctrl_reg); 2602 epctrl = readl(hsotg->regs + epctrl_reg);
2603 2603
2604 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", 2604 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
@@ -2606,14 +2606,14 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2606 2606
2607 spin_lock_irqsave(&hs_ep->lock, flags); 2607 spin_lock_irqsave(&hs_ep->lock, flags);
2608 2608
2609 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK); 2609 epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
2610 epctrl |= S3C_DxEPCTL_MPS(mps); 2610 epctrl |= DxEPCTL_MPS(mps);
2611 2611
2612 /* 2612 /*
2613 * mark the endpoint as active, otherwise the core may ignore 2613 * mark the endpoint as active, otherwise the core may ignore
2614 * transactions entirely for this endpoint 2614 * transactions entirely for this endpoint
2615 */ 2615 */
2616 epctrl |= S3C_DxEPCTL_USBActEp; 2616 epctrl |= DxEPCTL_USBActEp;
2617 2617
2618 /* 2618 /*
2619 * set the NAK status on the endpoint, otherwise we might try and 2619 * set the NAK status on the endpoint, otherwise we might try and
@@ -2622,7 +2622,7 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2622 * size register hasn't been set. 2622 * size register hasn't been set.
2623 */ 2623 */
2624 2624
2625 epctrl |= S3C_DxEPCTL_SNAK; 2625 epctrl |= DxEPCTL_SNAK;
2626 2626
2627 /* update the endpoint state */ 2627 /* update the endpoint state */
2628 hs_ep->ep.maxpacket = mps; 2628 hs_ep->ep.maxpacket = mps;
@@ -2637,7 +2637,7 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2637 goto out; 2637 goto out;
2638 2638
2639 case USB_ENDPOINT_XFER_BULK: 2639 case USB_ENDPOINT_XFER_BULK:
2640 epctrl |= S3C_DxEPCTL_EPType_Bulk; 2640 epctrl |= DxEPCTL_EPType_Bulk;
2641 break; 2641 break;
2642 2642
2643 case USB_ENDPOINT_XFER_INT: 2643 case USB_ENDPOINT_XFER_INT:
@@ -2650,14 +2650,14 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2650 */ 2650 */
2651 2651
2652 hs_ep->periodic = 1; 2652 hs_ep->periodic = 1;
2653 epctrl |= S3C_DxEPCTL_TxFNum(index); 2653 epctrl |= DxEPCTL_TxFNum(index);
2654 } 2654 }
2655 2655
2656 epctrl |= S3C_DxEPCTL_EPType_Intterupt; 2656 epctrl |= DxEPCTL_EPType_Intterupt;
2657 break; 2657 break;
2658 2658
2659 case USB_ENDPOINT_XFER_CONTROL: 2659 case USB_ENDPOINT_XFER_CONTROL:
2660 epctrl |= S3C_DxEPCTL_EPType_Control; 2660 epctrl |= DxEPCTL_EPType_Control;
2661 break; 2661 break;
2662 } 2662 }
2663 2663
@@ -2666,11 +2666,11 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2666 * a unique tx-fifo even if it is non-periodic. 2666 * a unique tx-fifo even if it is non-periodic.
2667 */ 2667 */
2668 if (dir_in && hsotg->dedicated_fifos) 2668 if (dir_in && hsotg->dedicated_fifos)
2669 epctrl |= S3C_DxEPCTL_TxFNum(index); 2669 epctrl |= DxEPCTL_TxFNum(index);
2670 2670
2671 /* for non control endpoints, set PID to D0 */ 2671 /* for non control endpoints, set PID to D0 */
2672 if (index) 2672 if (index)
2673 epctrl |= S3C_DxEPCTL_SetD0PID; 2673 epctrl |= DxEPCTL_SetD0PID;
2674 2674
2675 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", 2675 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2676 __func__, epctrl); 2676 __func__, epctrl);
@@ -2708,7 +2708,7 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2708 return -EINVAL; 2708 return -EINVAL;
2709 } 2709 }
2710 2710
2711 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); 2711 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2712 2712
2713 /* terminate all requests with shutdown */ 2713 /* terminate all requests with shutdown */
2714 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false); 2714 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
@@ -2716,9 +2716,9 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2716 spin_lock_irqsave(&hs_ep->lock, flags); 2716 spin_lock_irqsave(&hs_ep->lock, flags);
2717 2717
2718 ctrl = readl(hsotg->regs + epctrl_reg); 2718 ctrl = readl(hsotg->regs + epctrl_reg);
2719 ctrl &= ~S3C_DxEPCTL_EPEna; 2719 ctrl &= ~DxEPCTL_EPEna;
2720 ctrl &= ~S3C_DxEPCTL_USBActEp; 2720 ctrl &= ~DxEPCTL_USBActEp;
2721 ctrl |= S3C_DxEPCTL_SNAK; 2721 ctrl |= DxEPCTL_SNAK;
2722 2722
2723 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 2723 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2724 writel(ctrl, hsotg->regs + epctrl_reg); 2724 writel(ctrl, hsotg->regs + epctrl_reg);
@@ -2795,34 +2795,34 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2795 2795
2796 /* write both IN and OUT control registers */ 2796 /* write both IN and OUT control registers */
2797 2797
2798 epreg = S3C_DIEPCTL(index); 2798 epreg = DIEPCTL(index);
2799 epctl = readl(hs->regs + epreg); 2799 epctl = readl(hs->regs + epreg);
2800 2800
2801 if (value) { 2801 if (value) {
2802 epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK; 2802 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
2803 if (epctl & S3C_DxEPCTL_EPEna) 2803 if (epctl & DxEPCTL_EPEna)
2804 epctl |= S3C_DxEPCTL_EPDis; 2804 epctl |= DxEPCTL_EPDis;
2805 } else { 2805 } else {
2806 epctl &= ~S3C_DxEPCTL_Stall; 2806 epctl &= ~DxEPCTL_Stall;
2807 xfertype = epctl & S3C_DxEPCTL_EPType_MASK; 2807 xfertype = epctl & DxEPCTL_EPType_MASK;
2808 if (xfertype == S3C_DxEPCTL_EPType_Bulk || 2808 if (xfertype == DxEPCTL_EPType_Bulk ||
2809 xfertype == S3C_DxEPCTL_EPType_Intterupt) 2809 xfertype == DxEPCTL_EPType_Intterupt)
2810 epctl |= S3C_DxEPCTL_SetD0PID; 2810 epctl |= DxEPCTL_SetD0PID;
2811 } 2811 }
2812 2812
2813 writel(epctl, hs->regs + epreg); 2813 writel(epctl, hs->regs + epreg);
2814 2814
2815 epreg = S3C_DOEPCTL(index); 2815 epreg = DOEPCTL(index);
2816 epctl = readl(hs->regs + epreg); 2816 epctl = readl(hs->regs + epreg);
2817 2817
2818 if (value) 2818 if (value)
2819 epctl |= S3C_DxEPCTL_Stall; 2819 epctl |= DxEPCTL_Stall;
2820 else { 2820 else {
2821 epctl &= ~S3C_DxEPCTL_Stall; 2821 epctl &= ~DxEPCTL_Stall;
2822 xfertype = epctl & S3C_DxEPCTL_EPType_MASK; 2822 xfertype = epctl & DxEPCTL_EPType_MASK;
2823 if (xfertype == S3C_DxEPCTL_EPType_Bulk || 2823 if (xfertype == DxEPCTL_EPType_Bulk ||
2824 xfertype == S3C_DxEPCTL_EPType_Intterupt) 2824 xfertype == DxEPCTL_EPType_Intterupt)
2825 epctl |= S3C_DxEPCTL_SetD0PID; 2825 epctl |= DxEPCTL_SetD0PID;
2826 } 2826 }
2827 2827
2828 writel(epctl, hs->regs + epreg); 2828 writel(epctl, hs->regs + epreg);
@@ -2882,39 +2882,39 @@ static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2882{ 2882{
2883 /* unmask subset of endpoint interrupts */ 2883 /* unmask subset of endpoint interrupts */
2884 2884
2885 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk | 2885 writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2886 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk, 2886 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
2887 hsotg->regs + S3C_DIEPMSK); 2887 hsotg->regs + DIEPMSK);
2888 2888
2889 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk | 2889 writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
2890 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk, 2890 DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
2891 hsotg->regs + S3C_DOEPMSK); 2891 hsotg->regs + DOEPMSK);
2892 2892
2893 writel(0, hsotg->regs + S3C_DAINTMSK); 2893 writel(0, hsotg->regs + DAINTMSK);
2894 2894
2895 /* Be in disconnected state until gadget is registered */ 2895 /* Be in disconnected state until gadget is registered */
2896 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); 2896 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2897 2897
2898 if (0) { 2898 if (0) {
2899 /* post global nak until we're ready */ 2899 /* post global nak until we're ready */
2900 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak, 2900 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
2901 hsotg->regs + S3C_DCTL); 2901 hsotg->regs + DCTL);
2902 } 2902 }
2903 2903
2904 /* setup fifos */ 2904 /* setup fifos */
2905 2905
2906 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 2906 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2907 readl(hsotg->regs + S3C_GRXFSIZ), 2907 readl(hsotg->regs + GRXFSIZ),
2908 readl(hsotg->regs + S3C_GNPTXFSIZ)); 2908 readl(hsotg->regs + GNPTXFSIZ));
2909 2909
2910 s3c_hsotg_init_fifo(hsotg); 2910 s3c_hsotg_init_fifo(hsotg);
2911 2911
2912 /* set the PLL on, remove the HNP/SRP and set the PHY */ 2912 /* set the PLL on, remove the HNP/SRP and set the PHY */
2913 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10), 2913 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
2914 hsotg->regs + S3C_GUSBCFG); 2914 hsotg->regs + GUSBCFG);
2915 2915
2916 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0, 2916 writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
2917 hsotg->regs + S3C_GAHBCFG); 2917 hsotg->regs + GAHBCFG);
2918} 2918}
2919 2919
2920/** 2920/**
@@ -3080,8 +3080,8 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3080 * code is changed to make each endpoint's direction changeable. 3080 * code is changed to make each endpoint's direction changeable.
3081 */ 3081 */
3082 3082
3083 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum)); 3083 ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
3084 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4; 3084 hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
3085 3085
3086 /* 3086 /*
3087 * if we're using dma, we need to set the next-endpoint pointer 3087 * if we're using dma, we need to set the next-endpoint pointer
@@ -3089,9 +3089,9 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3089 */ 3089 */
3090 3090
3091 if (using_dma(hsotg)) { 3091 if (using_dma(hsotg)) {
3092 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15); 3092 u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
3093 writel(next, hsotg->regs + S3C_DIEPCTL(epnum)); 3093 writel(next, hsotg->regs + DIEPCTL(epnum));
3094 writel(next, hsotg->regs + S3C_DOEPCTL(epnum)); 3094 writel(next, hsotg->regs + DOEPCTL(epnum));
3095 } 3095 }
3096} 3096}
3097 3097
@@ -3131,42 +3131,42 @@ static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3131 int idx; 3131 int idx;
3132 3132
3133 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", 3133 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3134 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL), 3134 readl(regs + DCFG), readl(regs + DCTL),
3135 readl(regs + S3C_DIEPMSK)); 3135 readl(regs + DIEPMSK));
3136 3136
3137 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", 3137 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3138 readl(regs + S3C_GAHBCFG), readl(regs + 0x44)); 3138 readl(regs + GAHBCFG), readl(regs + 0x44));
3139 3139
3140 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 3140 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3141 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ)); 3141 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3142 3142
3143 /* show periodic fifo settings */ 3143 /* show periodic fifo settings */
3144 3144
3145 for (idx = 1; idx <= 15; idx++) { 3145 for (idx = 1; idx <= 15; idx++) {
3146 val = readl(regs + S3C_DPTXFSIZn(idx)); 3146 val = readl(regs + DPTXFSIZn(idx));
3147 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, 3147 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3148 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT, 3148 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3149 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK); 3149 val & DPTXFSIZn_DPTxFStAddr_MASK);
3150 } 3150 }
3151 3151
3152 for (idx = 0; idx < 15; idx++) { 3152 for (idx = 0; idx < 15; idx++) {
3153 dev_info(dev, 3153 dev_info(dev,
3154 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, 3154 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3155 readl(regs + S3C_DIEPCTL(idx)), 3155 readl(regs + DIEPCTL(idx)),
3156 readl(regs + S3C_DIEPTSIZ(idx)), 3156 readl(regs + DIEPTSIZ(idx)),
3157 readl(regs + S3C_DIEPDMA(idx))); 3157 readl(regs + DIEPDMA(idx)));
3158 3158
3159 val = readl(regs + S3C_DOEPCTL(idx)); 3159 val = readl(regs + DOEPCTL(idx));
3160 dev_info(dev, 3160 dev_info(dev,
3161 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", 3161 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3162 idx, readl(regs + S3C_DOEPCTL(idx)), 3162 idx, readl(regs + DOEPCTL(idx)),
3163 readl(regs + S3C_DOEPTSIZ(idx)), 3163 readl(regs + DOEPTSIZ(idx)),
3164 readl(regs + S3C_DOEPDMA(idx))); 3164 readl(regs + DOEPDMA(idx)));
3165 3165
3166 } 3166 }
3167 3167
3168 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", 3168 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3169 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE)); 3169 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3170#endif 3170#endif
3171} 3171}
3172 3172
@@ -3186,38 +3186,38 @@ static int state_show(struct seq_file *seq, void *v)
3186 int idx; 3186 int idx;
3187 3187
3188 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", 3188 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3189 readl(regs + S3C_DCFG), 3189 readl(regs + DCFG),
3190 readl(regs + S3C_DCTL), 3190 readl(regs + DCTL),
3191 readl(regs + S3C_DSTS)); 3191 readl(regs + DSTS));
3192 3192
3193 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", 3193 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3194 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK)); 3194 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3195 3195
3196 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", 3196 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3197 readl(regs + S3C_GINTMSK), 3197 readl(regs + GINTMSK),
3198 readl(regs + S3C_GINTSTS)); 3198 readl(regs + GINTSTS));
3199 3199
3200 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", 3200 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3201 readl(regs + S3C_DAINTMSK), 3201 readl(regs + DAINTMSK),
3202 readl(regs + S3C_DAINT)); 3202 readl(regs + DAINT));
3203 3203
3204 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", 3204 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3205 readl(regs + S3C_GNPTXSTS), 3205 readl(regs + GNPTXSTS),
3206 readl(regs + S3C_GRXSTSR)); 3206 readl(regs + GRXSTSR));
3207 3207
3208 seq_printf(seq, "\nEndpoint status:\n"); 3208 seq_printf(seq, "\nEndpoint status:\n");
3209 3209
3210 for (idx = 0; idx < 15; idx++) { 3210 for (idx = 0; idx < 15; idx++) {
3211 u32 in, out; 3211 u32 in, out;
3212 3212
3213 in = readl(regs + S3C_DIEPCTL(idx)); 3213 in = readl(regs + DIEPCTL(idx));
3214 out = readl(regs + S3C_DOEPCTL(idx)); 3214 out = readl(regs + DOEPCTL(idx));
3215 3215
3216 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", 3216 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3217 idx, in, out); 3217 idx, in, out);
3218 3218
3219 in = readl(regs + S3C_DIEPTSIZ(idx)); 3219 in = readl(regs + DIEPTSIZ(idx));
3220 out = readl(regs + S3C_DOEPTSIZ(idx)); 3220 out = readl(regs + DOEPTSIZ(idx));
3221 3221
3222 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", 3222 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3223 in, out); 3223 in, out);
@@ -3257,21 +3257,21 @@ static int fifo_show(struct seq_file *seq, void *v)
3257 int idx; 3257 int idx;
3258 3258
3259 seq_printf(seq, "Non-periodic FIFOs:\n"); 3259 seq_printf(seq, "Non-periodic FIFOs:\n");
3260 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ)); 3260 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3261 3261
3262 val = readl(regs + S3C_GNPTXFSIZ); 3262 val = readl(regs + GNPTXFSIZ);
3263 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", 3263 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3264 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT, 3264 val >> GNPTXFSIZ_NPTxFDep_SHIFT,
3265 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK); 3265 val & GNPTXFSIZ_NPTxFStAddr_MASK);
3266 3266
3267 seq_printf(seq, "\nPeriodic TXFIFOs:\n"); 3267 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3268 3268
3269 for (idx = 1; idx <= 15; idx++) { 3269 for (idx = 1; idx <= 15; idx++) {
3270 val = readl(regs + S3C_DPTXFSIZn(idx)); 3270 val = readl(regs + DPTXFSIZn(idx));
3271 3271
3272 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, 3272 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3273 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT, 3273 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3274 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK); 3274 val & DPTXFSIZn_DPTxFStAddr_MASK);
3275 } 3275 }
3276 3276
3277 return 0; 3277 return 0;
@@ -3320,20 +3320,20 @@ static int ep_show(struct seq_file *seq, void *v)
3320 /* first show the register state */ 3320 /* first show the register state */
3321 3321
3322 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", 3322 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3323 readl(regs + S3C_DIEPCTL(index)), 3323 readl(regs + DIEPCTL(index)),
3324 readl(regs + S3C_DOEPCTL(index))); 3324 readl(regs + DOEPCTL(index)));
3325 3325
3326 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", 3326 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3327 readl(regs + S3C_DIEPDMA(index)), 3327 readl(regs + DIEPDMA(index)),
3328 readl(regs + S3C_DOEPDMA(index))); 3328 readl(regs + DOEPDMA(index)));
3329 3329
3330 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", 3330 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3331 readl(regs + S3C_DIEPINT(index)), 3331 readl(regs + DIEPINT(index)),
3332 readl(regs + S3C_DOEPINT(index))); 3332 readl(regs + DOEPINT(index)));
3333 3333
3334 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", 3334 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3335 readl(regs + S3C_DIEPTSIZ(index)), 3335 readl(regs + DIEPTSIZ(index)),
3336 readl(regs + S3C_DOEPTSIZ(index))); 3336 readl(regs + DOEPTSIZ(index)));
3337 3337
3338 seq_printf(seq, "\n"); 3338 seq_printf(seq, "\n");
3339 seq_printf(seq, "mps %d\n", ep->ep.maxpacket); 3339 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
diff --git a/drivers/usb/gadget/s3c-hsotg.h b/drivers/usb/gadget/s3c-hsotg.h
index 4c4ccc44b577..d650b1295831 100644
--- a/drivers/usb/gadget/s3c-hsotg.h
+++ b/drivers/usb/gadget/s3c-hsotg.h
@@ -1,379 +1,377 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h 1/* drivers/usb/gadget/s3c-hsotg.h
2 * 2 *
3 * Copyright 2008 Openmoko, Inc. 3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/ 5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk> 6 * Ben Dooks <ben@simtec.co.uk>
7 * 7 *
8 * S3C - USB2.0 Highspeed/OtG device block registers 8 * USB2.0 Highspeed/OtG Synopsis DWC2 device block registers
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H 15#ifndef __REGS_USB_HSOTG_H
16#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__ 16#define __REGS_USB_HSOTG_H __FILE__
17 17
18#define S3C_HSOTG_REG(x) (x) 18#define HSOTG_REG(x) (x)
19 19
20#define S3C_GOTGCTL S3C_HSOTG_REG(0x000) 20#define GOTGCTL HSOTG_REG(0x000)
21#define S3C_GOTGCTL_BSESVLD (1 << 19) 21#define GOTGCTL_BSESVLD (1 << 19)
22#define S3C_GOTGCTL_ASESVLD (1 << 18) 22#define GOTGCTL_ASESVLD (1 << 18)
23#define S3C_GOTGCTL_DBNC_SHORT (1 << 17) 23#define GOTGCTL_DBNC_SHORT (1 << 17)
24#define S3C_GOTGCTL_CONID_B (1 << 16) 24#define GOTGCTL_CONID_B (1 << 16)
25#define S3C_GOTGCTL_DEVHNPEN (1 << 11) 25#define GOTGCTL_DEVHNPEN (1 << 11)
26#define S3C_GOTGCTL_HSSETHNPEN (1 << 10) 26#define GOTGCTL_HSSETHNPEN (1 << 10)
27#define S3C_GOTGCTL_HNPREQ (1 << 9) 27#define GOTGCTL_HNPREQ (1 << 9)
28#define S3C_GOTGCTL_HSTNEGSCS (1 << 8) 28#define GOTGCTL_HSTNEGSCS (1 << 8)
29#define S3C_GOTGCTL_SESREQ (1 << 1) 29#define GOTGCTL_SESREQ (1 << 1)
30#define S3C_GOTGCTL_SESREQSCS (1 << 0) 30#define GOTGCTL_SESREQSCS (1 << 0)
31 31
32#define S3C_GOTGINT S3C_HSOTG_REG(0x004) 32#define GOTGINT HSOTG_REG(0x004)
33#define S3C_GOTGINT_DbnceDone (1 << 19) 33#define GOTGINT_DbnceDone (1 << 19)
34#define S3C_GOTGINT_ADevTOUTChg (1 << 18) 34#define GOTGINT_ADevTOUTChg (1 << 18)
35#define S3C_GOTGINT_HstNegDet (1 << 17) 35#define GOTGINT_HstNegDet (1 << 17)
36#define S3C_GOTGINT_HstnegSucStsChng (1 << 9) 36#define GOTGINT_HstnegSucStsChng (1 << 9)
37#define S3C_GOTGINT_SesReqSucStsChng (1 << 8) 37#define GOTGINT_SesReqSucStsChng (1 << 8)
38#define S3C_GOTGINT_SesEndDet (1 << 2) 38#define GOTGINT_SesEndDet (1 << 2)
39 39
40#define S3C_GAHBCFG S3C_HSOTG_REG(0x008) 40#define GAHBCFG HSOTG_REG(0x008)
41#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8) 41#define GAHBCFG_PTxFEmpLvl (1 << 8)
42#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7) 42#define GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define S3C_GAHBCFG_DMAEn (1 << 5) 43#define GAHBCFG_DMAEn (1 << 5)
44#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1) 44#define GAHBCFG_HBstLen_MASK (0xf << 1)
45#define S3C_GAHBCFG_HBstLen_SHIFT (1) 45#define GAHBCFG_HBstLen_SHIFT (1)
46#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1) 46#define GAHBCFG_HBstLen_Single (0x0 << 1)
47#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1) 47#define GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1) 48#define GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1) 49#define GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1) 50#define GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define S3C_GAHBCFG_GlblIntrEn (1 << 0) 51#define GAHBCFG_GlblIntrEn (1 << 0)
52 52
53#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C) 53#define GUSBCFG HSOTG_REG(0x00C)
54#define S3C_GUSBCFG_PHYLPClkSel (1 << 15) 54#define GUSBCFG_PHYLPClkSel (1 << 15)
55#define S3C_GUSBCFG_HNPCap (1 << 9) 55#define GUSBCFG_HNPCap (1 << 9)
56#define S3C_GUSBCFG_SRPCap (1 << 8) 56#define GUSBCFG_SRPCap (1 << 8)
57#define S3C_GUSBCFG_PHYIf16 (1 << 3) 57#define GUSBCFG_PHYIf16 (1 << 3)
58#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0) 58#define GUSBCFG_TOutCal_MASK (0x7 << 0)
59#define S3C_GUSBCFG_TOutCal_SHIFT (0) 59#define GUSBCFG_TOutCal_SHIFT (0)
60#define S3C_GUSBCFG_TOutCal_LIMIT (0x7) 60#define GUSBCFG_TOutCal_LIMIT (0x7)
61#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0) 61#define GUSBCFG_TOutCal(_x) ((_x) << 0)
62 62
63#define S3C_GRSTCTL S3C_HSOTG_REG(0x010) 63#define GRSTCTL HSOTG_REG(0x010)
64 64
65#define S3C_GRSTCTL_AHBIdle (1 << 31) 65#define GRSTCTL_AHBIdle (1 << 31)
66#define S3C_GRSTCTL_DMAReq (1 << 30) 66#define GRSTCTL_DMAReq (1 << 30)
67#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6) 67#define GRSTCTL_TxFNum_MASK (0x1f << 6)
68#define S3C_GRSTCTL_TxFNum_SHIFT (6) 68#define GRSTCTL_TxFNum_SHIFT (6)
69#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f) 69#define GRSTCTL_TxFNum_LIMIT (0x1f)
70#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6) 70#define GRSTCTL_TxFNum(_x) ((_x) << 6)
71#define S3C_GRSTCTL_TxFFlsh (1 << 5) 71#define GRSTCTL_TxFFlsh (1 << 5)
72#define S3C_GRSTCTL_RxFFlsh (1 << 4) 72#define GRSTCTL_RxFFlsh (1 << 4)
73#define S3C_GRSTCTL_INTknQFlsh (1 << 3) 73#define GRSTCTL_INTknQFlsh (1 << 3)
74#define S3C_GRSTCTL_FrmCntrRst (1 << 2) 74#define GRSTCTL_FrmCntrRst (1 << 2)
75#define S3C_GRSTCTL_HSftRst (1 << 1) 75#define GRSTCTL_HSftRst (1 << 1)
76#define S3C_GRSTCTL_CSftRst (1 << 0) 76#define GRSTCTL_CSftRst (1 << 0)
77 77
78#define S3C_GINTSTS S3C_HSOTG_REG(0x014) 78#define GINTSTS HSOTG_REG(0x014)
79#define S3C_GINTMSK S3C_HSOTG_REG(0x018) 79#define GINTMSK HSOTG_REG(0x018)
80 80
81#define S3C_GINTSTS_WkUpInt (1 << 31) 81#define GINTSTS_WkUpInt (1 << 31)
82#define S3C_GINTSTS_SessReqInt (1 << 30) 82#define GINTSTS_SessReqInt (1 << 30)
83#define S3C_GINTSTS_DisconnInt (1 << 29) 83#define GINTSTS_DisconnInt (1 << 29)
84#define S3C_GINTSTS_ConIDStsChng (1 << 28) 84#define GINTSTS_ConIDStsChng (1 << 28)
85#define S3C_GINTSTS_PTxFEmp (1 << 26) 85#define GINTSTS_PTxFEmp (1 << 26)
86#define S3C_GINTSTS_HChInt (1 << 25) 86#define GINTSTS_HChInt (1 << 25)
87#define S3C_GINTSTS_PrtInt (1 << 24) 87#define GINTSTS_PrtInt (1 << 24)
88#define S3C_GINTSTS_FetSusp (1 << 22) 88#define GINTSTS_FetSusp (1 << 22)
89#define S3C_GINTSTS_incompIP (1 << 21) 89#define GINTSTS_incompIP (1 << 21)
90#define S3C_GINTSTS_IncomplSOIN (1 << 20) 90#define GINTSTS_IncomplSOIN (1 << 20)
91#define S3C_GINTSTS_OEPInt (1 << 19) 91#define GINTSTS_OEPInt (1 << 19)
92#define S3C_GINTSTS_IEPInt (1 << 18) 92#define GINTSTS_IEPInt (1 << 18)
93#define S3C_GINTSTS_EPMis (1 << 17) 93#define GINTSTS_EPMis (1 << 17)
94#define S3C_GINTSTS_EOPF (1 << 15) 94#define GINTSTS_EOPF (1 << 15)
95#define S3C_GINTSTS_ISOutDrop (1 << 14) 95#define GINTSTS_ISOutDrop (1 << 14)
96#define S3C_GINTSTS_EnumDone (1 << 13) 96#define GINTSTS_EnumDone (1 << 13)
97#define S3C_GINTSTS_USBRst (1 << 12) 97#define GINTSTS_USBRst (1 << 12)
98#define S3C_GINTSTS_USBSusp (1 << 11) 98#define GINTSTS_USBSusp (1 << 11)
99#define S3C_GINTSTS_ErlySusp (1 << 10) 99#define GINTSTS_ErlySusp (1 << 10)
100#define S3C_GINTSTS_GOUTNakEff (1 << 7) 100#define GINTSTS_GOUTNakEff (1 << 7)
101#define S3C_GINTSTS_GINNakEff (1 << 6) 101#define GINTSTS_GINNakEff (1 << 6)
102#define S3C_GINTSTS_NPTxFEmp (1 << 5) 102#define GINTSTS_NPTxFEmp (1 << 5)
103#define S3C_GINTSTS_RxFLvl (1 << 4) 103#define GINTSTS_RxFLvl (1 << 4)
104#define S3C_GINTSTS_SOF (1 << 3) 104#define GINTSTS_SOF (1 << 3)
105#define S3C_GINTSTS_OTGInt (1 << 2) 105#define GINTSTS_OTGInt (1 << 2)
106#define S3C_GINTSTS_ModeMis (1 << 1) 106#define GINTSTS_ModeMis (1 << 1)
107#define S3C_GINTSTS_CurMod_Host (1 << 0) 107#define GINTSTS_CurMod_Host (1 << 0)
108 108
109#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C) 109#define GRXSTSR HSOTG_REG(0x01C)
110#define S3C_GRXSTSP S3C_HSOTG_REG(0x020) 110#define GRXSTSP HSOTG_REG(0x020)
111 111
112#define S3C_GRXSTS_FN_MASK (0x7f << 25) 112#define GRXSTS_FN_MASK (0x7f << 25)
113#define S3C_GRXSTS_FN_SHIFT (25) 113#define GRXSTS_FN_SHIFT (25)
114 114
115#define S3C_GRXSTS_PktSts_MASK (0xf << 17) 115#define GRXSTS_PktSts_MASK (0xf << 17)
116#define S3C_GRXSTS_PktSts_SHIFT (17) 116#define GRXSTS_PktSts_SHIFT (17)
117#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17) 117#define GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
118#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17) 118#define GRXSTS_PktSts_OutRX (0x2 << 17)
119#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17) 119#define GRXSTS_PktSts_OutDone (0x3 << 17)
120#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17) 120#define GRXSTS_PktSts_SetupDone (0x4 << 17)
121#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17) 121#define GRXSTS_PktSts_SetupRX (0x6 << 17)
122 122
123#define S3C_GRXSTS_DPID_MASK (0x3 << 15) 123#define GRXSTS_DPID_MASK (0x3 << 15)
124#define S3C_GRXSTS_DPID_SHIFT (15) 124#define GRXSTS_DPID_SHIFT (15)
125#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4) 125#define GRXSTS_ByteCnt_MASK (0x7ff << 4)
126#define S3C_GRXSTS_ByteCnt_SHIFT (4) 126#define GRXSTS_ByteCnt_SHIFT (4)
127#define S3C_GRXSTS_EPNum_MASK (0xf << 0) 127#define GRXSTS_EPNum_MASK (0xf << 0)
128#define S3C_GRXSTS_EPNum_SHIFT (0) 128#define GRXSTS_EPNum_SHIFT (0)
129 129
130#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024) 130#define GRXFSIZ HSOTG_REG(0x024)
131 131
132#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028) 132#define GNPTXFSIZ HSOTG_REG(0x028)
133 133
134#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16) 134#define GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
135#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16) 135#define GNPTXFSIZ_NPTxFDep_SHIFT (16)
136#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff) 136#define GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
137#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16) 137#define GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
138#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0) 138#define GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
139#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0) 139#define GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
140#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff) 140#define GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
141#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0) 141#define GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
142 142
143#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C) 143#define GNPTXSTS HSOTG_REG(0x02C)
144 144
145#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24) 145#define GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
146#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24) 146#define GNPTXSTS_NPtxQTop_SHIFT (24)
147 147
148#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16) 148#define GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
149#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16) 149#define GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
150#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff) 150#define GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
151 151
152#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0) 152#define GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
153#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0) 153#define GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
154#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff) 154#define GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
155 155
156 156
157#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100) 157#define HPTXFSIZ HSOTG_REG(0x100)
158 158
159#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4)) 159#define DPTXFSIZn(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
160 160
161#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16) 161#define DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
162#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16) 162#define DPTXFSIZn_DPTxFSize_SHIFT (16)
163#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff) 163#define DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
164#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff) 164#define DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
165#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16) 165#define DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
166 166
167#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0) 167#define DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
168#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0) 168#define DPTXFSIZn_DPTxFStAddr_SHIFT (0)
169 169
170/* Device mode registers */ 170/* Device mode registers */
171#define S3C_DCFG S3C_HSOTG_REG(0x800) 171#define DCFG HSOTG_REG(0x800)
172 172
173#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18) 173#define DCFG_EPMisCnt_MASK (0x1f << 18)
174#define S3C_DCFG_EPMisCnt_SHIFT (18) 174#define DCFG_EPMisCnt_SHIFT (18)
175#define S3C_DCFG_EPMisCnt_LIMIT (0x1f) 175#define DCFG_EPMisCnt_LIMIT (0x1f)
176#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18) 176#define DCFG_EPMisCnt(_x) ((_x) << 18)
177 177
178#define S3C_DCFG_PerFrInt_MASK (0x3 << 11) 178#define DCFG_PerFrInt_MASK (0x3 << 11)
179#define S3C_DCFG_PerFrInt_SHIFT (11) 179#define DCFG_PerFrInt_SHIFT (11)
180#define S3C_DCFG_PerFrInt_LIMIT (0x3) 180#define DCFG_PerFrInt_LIMIT (0x3)
181#define S3C_DCFG_PerFrInt(_x) ((_x) << 11) 181#define DCFG_PerFrInt(_x) ((_x) << 11)
182 182
183#define S3C_DCFG_DevAddr_MASK (0x7f << 4) 183#define DCFG_DevAddr_MASK (0x7f << 4)
184#define S3C_DCFG_DevAddr_SHIFT (4) 184#define DCFG_DevAddr_SHIFT (4)
185#define S3C_DCFG_DevAddr_LIMIT (0x7f) 185#define DCFG_DevAddr_LIMIT (0x7f)
186#define S3C_DCFG_DevAddr(_x) ((_x) << 4) 186#define DCFG_DevAddr(_x) ((_x) << 4)
187 187
188#define S3C_DCFG_NZStsOUTHShk (1 << 2) 188#define DCFG_NZStsOUTHShk (1 << 2)
189 189
190#define S3C_DCFG_DevSpd_MASK (0x3 << 0) 190#define DCFG_DevSpd_MASK (0x3 << 0)
191#define S3C_DCFG_DevSpd_SHIFT (0) 191#define DCFG_DevSpd_SHIFT (0)
192#define S3C_DCFG_DevSpd_HS (0x0 << 0) 192#define DCFG_DevSpd_HS (0x0 << 0)
193#define S3C_DCFG_DevSpd_FS (0x1 << 0) 193#define DCFG_DevSpd_FS (0x1 << 0)
194#define S3C_DCFG_DevSpd_LS (0x2 << 0) 194#define DCFG_DevSpd_LS (0x2 << 0)
195#define S3C_DCFG_DevSpd_FS48 (0x3 << 0) 195#define DCFG_DevSpd_FS48 (0x3 << 0)
196 196
197#define S3C_DCTL S3C_HSOTG_REG(0x804) 197#define DCTL HSOTG_REG(0x804)
198 198
199#define S3C_DCTL_PWROnPrgDone (1 << 11) 199#define DCTL_PWROnPrgDone (1 << 11)
200#define S3C_DCTL_CGOUTNak (1 << 10) 200#define DCTL_CGOUTNak (1 << 10)
201#define S3C_DCTL_SGOUTNak (1 << 9) 201#define DCTL_SGOUTNak (1 << 9)
202#define S3C_DCTL_CGNPInNAK (1 << 8) 202#define DCTL_CGNPInNAK (1 << 8)
203#define S3C_DCTL_SGNPInNAK (1 << 7) 203#define DCTL_SGNPInNAK (1 << 7)
204#define S3C_DCTL_TstCtl_MASK (0x7 << 4) 204#define DCTL_TstCtl_MASK (0x7 << 4)
205#define S3C_DCTL_TstCtl_SHIFT (4) 205#define DCTL_TstCtl_SHIFT (4)
206#define S3C_DCTL_GOUTNakSts (1 << 3) 206#define DCTL_GOUTNakSts (1 << 3)
207#define S3C_DCTL_GNPINNakSts (1 << 2) 207#define DCTL_GNPINNakSts (1 << 2)
208#define S3C_DCTL_SftDiscon (1 << 1) 208#define DCTL_SftDiscon (1 << 1)
209#define S3C_DCTL_RmtWkUpSig (1 << 0) 209#define DCTL_RmtWkUpSig (1 << 0)
210 210
211#define S3C_DSTS S3C_HSOTG_REG(0x808) 211#define DSTS HSOTG_REG(0x808)
212 212
213#define S3C_DSTS_SOFFN_MASK (0x3fff << 8) 213#define DSTS_SOFFN_MASK (0x3fff << 8)
214#define S3C_DSTS_SOFFN_SHIFT (8) 214#define DSTS_SOFFN_SHIFT (8)
215#define S3C_DSTS_SOFFN_LIMIT (0x3fff) 215#define DSTS_SOFFN_LIMIT (0x3fff)
216#define S3C_DSTS_SOFFN(_x) ((_x) << 8) 216#define DSTS_SOFFN(_x) ((_x) << 8)
217#define S3C_DSTS_ErraticErr (1 << 3) 217#define DSTS_ErraticErr (1 << 3)
218#define S3C_DSTS_EnumSpd_MASK (0x3 << 1) 218#define DSTS_EnumSpd_MASK (0x3 << 1)
219#define S3C_DSTS_EnumSpd_SHIFT (1) 219#define DSTS_EnumSpd_SHIFT (1)
220#define S3C_DSTS_EnumSpd_HS (0x0 << 1) 220#define DSTS_EnumSpd_HS (0x0 << 1)
221#define S3C_DSTS_EnumSpd_FS (0x1 << 1) 221#define DSTS_EnumSpd_FS (0x1 << 1)
222#define S3C_DSTS_EnumSpd_LS (0x2 << 1) 222#define DSTS_EnumSpd_LS (0x2 << 1)
223#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1) 223#define DSTS_EnumSpd_FS48 (0x3 << 1)
224 224
225#define S3C_DSTS_SuspSts (1 << 0) 225#define DSTS_SuspSts (1 << 0)
226 226
227#define S3C_DIEPMSK S3C_HSOTG_REG(0x810) 227#define DIEPMSK HSOTG_REG(0x810)
228 228
229#define S3C_DIEPMSK_TxFIFOEmpty (1 << 7) 229#define DIEPMSK_TxFIFOEmpty (1 << 7)
230#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6) 230#define DIEPMSK_INEPNakEffMsk (1 << 6)
231#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5) 231#define DIEPMSK_INTknEPMisMsk (1 << 5)
232#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4) 232#define DIEPMSK_INTknTXFEmpMsk (1 << 4)
233#define S3C_DIEPMSK_TimeOUTMsk (1 << 3) 233#define DIEPMSK_TimeOUTMsk (1 << 3)
234#define S3C_DIEPMSK_AHBErrMsk (1 << 2) 234#define DIEPMSK_AHBErrMsk (1 << 2)
235#define S3C_DIEPMSK_EPDisbldMsk (1 << 1) 235#define DIEPMSK_EPDisbldMsk (1 << 1)
236#define S3C_DIEPMSK_XferComplMsk (1 << 0) 236#define DIEPMSK_XferComplMsk (1 << 0)
237 237
238#define S3C_DOEPMSK S3C_HSOTG_REG(0x814) 238#define DOEPMSK HSOTG_REG(0x814)
239 239
240#define S3C_DOEPMSK_Back2BackSetup (1 << 6) 240#define DOEPMSK_Back2BackSetup (1 << 6)
241#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4) 241#define DOEPMSK_OUTTknEPdisMsk (1 << 4)
242#define S3C_DOEPMSK_SetupMsk (1 << 3) 242#define DOEPMSK_SetupMsk (1 << 3)
243#define S3C_DOEPMSK_AHBErrMsk (1 << 2) 243#define DOEPMSK_AHBErrMsk (1 << 2)
244#define S3C_DOEPMSK_EPDisbldMsk (1 << 1) 244#define DOEPMSK_EPDisbldMsk (1 << 1)
245#define S3C_DOEPMSK_XferComplMsk (1 << 0) 245#define DOEPMSK_XferComplMsk (1 << 0)
246 246
247#define S3C_DAINT S3C_HSOTG_REG(0x818) 247#define DAINT HSOTG_REG(0x818)
248#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C) 248#define DAINTMSK HSOTG_REG(0x81C)
249 249
250#define S3C_DAINT_OutEP_SHIFT (16) 250#define DAINT_OutEP_SHIFT (16)
251#define S3C_DAINT_OutEP(x) (1 << ((x) + 16)) 251#define DAINT_OutEP(x) (1 << ((x) + 16))
252#define S3C_DAINT_InEP(x) (1 << (x)) 252#define DAINT_InEP(x) (1 << (x))
253 253
254#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820) 254#define DTKNQR1 HSOTG_REG(0x820)
255#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824) 255#define DTKNQR2 HSOTG_REG(0x824)
256#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830) 256#define DTKNQR3 HSOTG_REG(0x830)
257#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834) 257#define DTKNQR4 HSOTG_REG(0x834)
258 258
259#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828) 259#define DVBUSDIS HSOTG_REG(0x828)
260#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C) 260#define DVBUSPULSE HSOTG_REG(0x82C)
261 261
262#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900) 262#define DIEPCTL0 HSOTG_REG(0x900)
263#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00) 263#define DOEPCTL0 HSOTG_REG(0xB00)
264#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20)) 264#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
265#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20)) 265#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
266 266
267/* EP0 specialness: 267/* EP0 specialness:
268 * bits[29..28] - reserved (no SetD0PID, SetD1PID) 268 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
269 * bits[25..22] - should always be zero, this isn't a periodic endpoint 269 * bits[25..22] - should always be zero, this isn't a periodic endpoint
270 * bits[10..0] - MPS setting differenct for EP0 270 * bits[10..0] - MPS setting differenct for EP0
271*/ 271 */
272#define S3C_D0EPCTL_MPS_MASK (0x3 << 0) 272#define D0EPCTL_MPS_MASK (0x3 << 0)
273#define S3C_D0EPCTL_MPS_SHIFT (0) 273#define D0EPCTL_MPS_SHIFT (0)
274#define S3C_D0EPCTL_MPS_64 (0x0 << 0) 274#define D0EPCTL_MPS_64 (0x0 << 0)
275#define S3C_D0EPCTL_MPS_32 (0x1 << 0) 275#define D0EPCTL_MPS_32 (0x1 << 0)
276#define S3C_D0EPCTL_MPS_16 (0x2 << 0) 276#define D0EPCTL_MPS_16 (0x2 << 0)
277#define S3C_D0EPCTL_MPS_8 (0x3 << 0) 277#define D0EPCTL_MPS_8 (0x3 << 0)
278 278
279#define S3C_DxEPCTL_EPEna (1 << 31) 279#define DxEPCTL_EPEna (1 << 31)
280#define S3C_DxEPCTL_EPDis (1 << 30) 280#define DxEPCTL_EPDis (1 << 30)
281#define S3C_DxEPCTL_SetD1PID (1 << 29) 281#define DxEPCTL_SetD1PID (1 << 29)
282#define S3C_DxEPCTL_SetOddFr (1 << 29) 282#define DxEPCTL_SetOddFr (1 << 29)
283#define S3C_DxEPCTL_SetD0PID (1 << 28) 283#define DxEPCTL_SetD0PID (1 << 28)
284#define S3C_DxEPCTL_SetEvenFr (1 << 28) 284#define DxEPCTL_SetEvenFr (1 << 28)
285#define S3C_DxEPCTL_SNAK (1 << 27) 285#define DxEPCTL_SNAK (1 << 27)
286#define S3C_DxEPCTL_CNAK (1 << 26) 286#define DxEPCTL_CNAK (1 << 26)
287#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22) 287#define DxEPCTL_TxFNum_MASK (0xf << 22)
288#define S3C_DxEPCTL_TxFNum_SHIFT (22) 288#define DxEPCTL_TxFNum_SHIFT (22)
289#define S3C_DxEPCTL_TxFNum_LIMIT (0xf) 289#define DxEPCTL_TxFNum_LIMIT (0xf)
290#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22) 290#define DxEPCTL_TxFNum(_x) ((_x) << 22)
291 291
292#define S3C_DxEPCTL_Stall (1 << 21) 292#define DxEPCTL_Stall (1 << 21)
293#define S3C_DxEPCTL_Snp (1 << 20) 293#define DxEPCTL_Snp (1 << 20)
294#define S3C_DxEPCTL_EPType_MASK (0x3 << 18) 294#define DxEPCTL_EPType_MASK (0x3 << 18)
295#define S3C_DxEPCTL_EPType_SHIFT (18) 295#define DxEPCTL_EPType_SHIFT (18)
296#define S3C_DxEPCTL_EPType_Control (0x0 << 18) 296#define DxEPCTL_EPType_Control (0x0 << 18)
297#define S3C_DxEPCTL_EPType_Iso (0x1 << 18) 297#define DxEPCTL_EPType_Iso (0x1 << 18)
298#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18) 298#define DxEPCTL_EPType_Bulk (0x2 << 18)
299#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18) 299#define DxEPCTL_EPType_Intterupt (0x3 << 18)
300 300
301#define S3C_DxEPCTL_NAKsts (1 << 17) 301#define DxEPCTL_NAKsts (1 << 17)
302#define S3C_DxEPCTL_DPID (1 << 16) 302#define DxEPCTL_DPID (1 << 16)
303#define S3C_DxEPCTL_EOFrNum (1 << 16) 303#define DxEPCTL_EOFrNum (1 << 16)
304#define S3C_DxEPCTL_USBActEp (1 << 15) 304#define DxEPCTL_USBActEp (1 << 15)
305#define S3C_DxEPCTL_NextEp_MASK (0xf << 11) 305#define DxEPCTL_NextEp_MASK (0xf << 11)
306#define S3C_DxEPCTL_NextEp_SHIFT (11) 306#define DxEPCTL_NextEp_SHIFT (11)
307#define S3C_DxEPCTL_NextEp_LIMIT (0xf) 307#define DxEPCTL_NextEp_LIMIT (0xf)
308#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11) 308#define DxEPCTL_NextEp(_x) ((_x) << 11)
309 309
310#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0) 310#define DxEPCTL_MPS_MASK (0x7ff << 0)
311#define S3C_DxEPCTL_MPS_SHIFT (0) 311#define DxEPCTL_MPS_SHIFT (0)
312#define S3C_DxEPCTL_MPS_LIMIT (0x7ff) 312#define DxEPCTL_MPS_LIMIT (0x7ff)
313#define S3C_DxEPCTL_MPS(_x) ((_x) << 0) 313#define DxEPCTL_MPS(_x) ((_x) << 0)
314 314
315#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20)) 315#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
316#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20)) 316#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
317 317
318#define S3C_DxEPINT_INEPNakEff (1 << 6) 318#define DxEPINT_INEPNakEff (1 << 6)
319#define S3C_DxEPINT_Back2BackSetup (1 << 6) 319#define DxEPINT_Back2BackSetup (1 << 6)
320#define S3C_DxEPINT_INTknEPMis (1 << 5) 320#define DxEPINT_INTknEPMis (1 << 5)
321#define S3C_DxEPINT_INTknTXFEmp (1 << 4) 321#define DxEPINT_INTknTXFEmp (1 << 4)
322#define S3C_DxEPINT_OUTTknEPdis (1 << 4) 322#define DxEPINT_OUTTknEPdis (1 << 4)
323#define S3C_DxEPINT_Timeout (1 << 3) 323#define DxEPINT_Timeout (1 << 3)
324#define S3C_DxEPINT_Setup (1 << 3) 324#define DxEPINT_Setup (1 << 3)
325#define S3C_DxEPINT_AHBErr (1 << 2) 325#define DxEPINT_AHBErr (1 << 2)
326#define S3C_DxEPINT_EPDisbld (1 << 1) 326#define DxEPINT_EPDisbld (1 << 1)
327#define S3C_DxEPINT_XferCompl (1 << 0) 327#define DxEPINT_XferCompl (1 << 0)
328 328
329#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910) 329#define DIEPTSIZ0 HSOTG_REG(0x910)
330 330
331#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19) 331#define DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
332#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19) 332#define DIEPTSIZ0_PktCnt_SHIFT (19)
333#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3) 333#define DIEPTSIZ0_PktCnt_LIMIT (0x3)
334#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19) 334#define DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
335 335
336#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0) 336#define DIEPTSIZ0_XferSize_MASK (0x7f << 0)
337#define S3C_DIEPTSIZ0_XferSize_SHIFT (0) 337#define DIEPTSIZ0_XferSize_SHIFT (0)
338#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f) 338#define DIEPTSIZ0_XferSize_LIMIT (0x7f)
339#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0) 339#define DIEPTSIZ0_XferSize(_x) ((_x) << 0)
340 340
341 341#define DOEPTSIZ0 HSOTG_REG(0xB10)
342#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10) 342#define DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
343#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29) 343#define DOEPTSIZ0_SUPCnt_SHIFT (29)
344#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29) 344#define DOEPTSIZ0_SUPCnt_LIMIT (0x3)
345#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3) 345#define DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
346#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29) 346
347 347#define DOEPTSIZ0_PktCnt (1 << 19)
348#define S3C_DOEPTSIZ0_PktCnt (1 << 19) 348#define DOEPTSIZ0_XferSize_MASK (0x7f << 0)
349#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0) 349#define DOEPTSIZ0_XferSize_SHIFT (0)
350#define S3C_DOEPTSIZ0_XferSize_SHIFT (0) 350
351 351#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
352#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20)) 352#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
353#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20)) 353
354 354#define DxEPTSIZ_MC_MASK (0x3 << 29)
355#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29) 355#define DxEPTSIZ_MC_SHIFT (29)
356#define S3C_DxEPTSIZ_MC_SHIFT (29) 356#define DxEPTSIZ_MC_LIMIT (0x3)
357#define S3C_DxEPTSIZ_MC_LIMIT (0x3) 357#define DxEPTSIZ_MC(_x) ((_x) << 29)
358#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29) 358
359 359#define DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
360#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19) 360#define DxEPTSIZ_PktCnt_SHIFT (19)
361#define S3C_DxEPTSIZ_PktCnt_SHIFT (19) 361#define DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
362#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff) 362#define DxEPTSIZ_PktCnt_LIMIT (0x3ff)
363#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff) 363#define DxEPTSIZ_PktCnt(_x) ((_x) << 19)
364#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19) 364
365 365#define DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
366#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0) 366#define DxEPTSIZ_XferSize_SHIFT (0)
367#define S3C_DxEPTSIZ_XferSize_SHIFT (0) 367#define DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
368#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff) 368#define DxEPTSIZ_XferSize_LIMIT (0x7ffff)
369#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff) 369#define DxEPTSIZ_XferSize(_x) ((_x) << 0)
370#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0) 370
371 371#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
372 372#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
373#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20)) 373#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
374#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20)) 374
375#define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20)) 375#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
376 376
377#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000)) 377#endif /* __REGS_USB_HSOTG_H */
378
379#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
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