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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-02-04 15:46:33 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-02-04 15:46:33 -0500
commit5c2740280fef1c2da7835dea3856b5e9fc2a4bfd (patch)
tree14f7678bc1db213a56c09d457e6c29e558f1ff78 /drivers/usb
parent38dbfb59d1175ef458d006556061adeaa8751b72 (diff)
parentf7b2e4032d52deff480e0c303fbd9180276f8dfc (diff)
Merge tag 'for-usb-linus-2014-02-04' of git://git.kernel.org/pub/scm/linux/kernel/git/sarah/xhci into usb-linus
Sarah writes: xhci: Fix some regressions introduced in 3.14. Hi Greg, Here's four patches for 3.14. One of them adds an xHCI host quirk, and the other three of them fix regressions introduced in 3.14. One regression causes USB 3.0 Link PM to be enabled on all xHCI hosts (even those that may not support it), which causes some USB 3.0 devices to not enumerate. A second regression causes some xHCI hosts that don't support 64-bit addressing to stop responding to commands and die. Note, these patches don't fix the recent usbfs regression that was caused by commit 35773dac5f862cb1c82ea151eba3e2f6de51ec3e "usb: xhci: Link TRB must not occur within a USB payload burst". I'm waiting for those patches to be tested. Please pull usb-linus into usb-next, as I have feature patches that rely on 140e3026a57a Revert "usbcore: set lpm_capable field for LPM capable root hubs" Sarah Sharp
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/core/hcd.c1
-rw-r--r--drivers/usb/core/hub.c7
-rw-r--r--drivers/usb/core/usb.h1
-rw-r--r--drivers/usb/host/xhci-dbg.c6
-rw-r--r--drivers/usb/host/xhci-mem.c14
-rw-r--r--drivers/usb/host/xhci-pci.c5
-rw-r--r--drivers/usb/host/xhci-ring.c14
-rw-r--r--drivers/usb/host/xhci.c20
-rw-r--r--drivers/usb/host/xhci.h39
9 files changed, 62 insertions, 45 deletions
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 199aaea6bfe0..2518c3250750 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -1032,7 +1032,6 @@ static int register_root_hub(struct usb_hcd *hcd)
1032 dev_name(&usb_dev->dev), retval); 1032 dev_name(&usb_dev->dev), retval);
1033 return retval; 1033 return retval;
1034 } 1034 }
1035 usb_dev->lpm_capable = usb_device_supports_lpm(usb_dev);
1036 } 1035 }
1037 1036
1038 retval = usb_new_device (usb_dev); 1037 retval = usb_new_device (usb_dev);
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index babba885978d..64ea21971be2 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -128,7 +128,7 @@ struct usb_hub *usb_hub_to_struct_hub(struct usb_device *hdev)
128 return usb_get_intfdata(hdev->actconfig->interface[0]); 128 return usb_get_intfdata(hdev->actconfig->interface[0]);
129} 129}
130 130
131int usb_device_supports_lpm(struct usb_device *udev) 131static int usb_device_supports_lpm(struct usb_device *udev)
132{ 132{
133 /* USB 2.1 (and greater) devices indicate LPM support through 133 /* USB 2.1 (and greater) devices indicate LPM support through
134 * their USB 2.0 Extended Capabilities BOS descriptor. 134 * their USB 2.0 Extended Capabilities BOS descriptor.
@@ -149,11 +149,6 @@ int usb_device_supports_lpm(struct usb_device *udev)
149 "Power management will be impacted.\n"); 149 "Power management will be impacted.\n");
150 return 0; 150 return 0;
151 } 151 }
152
153 /* udev is root hub */
154 if (!udev->parent)
155 return 1;
156
157 if (udev->parent->lpm_capable) 152 if (udev->parent->lpm_capable)
158 return 1; 153 return 1;
159 154
diff --git a/drivers/usb/core/usb.h b/drivers/usb/core/usb.h
index c49383669cd8..823857767a16 100644
--- a/drivers/usb/core/usb.h
+++ b/drivers/usb/core/usb.h
@@ -35,7 +35,6 @@ extern int usb_get_device_descriptor(struct usb_device *dev,
35 unsigned int size); 35 unsigned int size);
36extern int usb_get_bos_descriptor(struct usb_device *dev); 36extern int usb_get_bos_descriptor(struct usb_device *dev);
37extern void usb_release_bos_descriptor(struct usb_device *dev); 37extern void usb_release_bos_descriptor(struct usb_device *dev);
38extern int usb_device_supports_lpm(struct usb_device *udev);
39extern char *usb_cache_string(struct usb_device *udev, int index); 38extern char *usb_cache_string(struct usb_device *udev, int index);
40extern int usb_set_configuration(struct usb_device *dev, int configuration); 39extern int usb_set_configuration(struct usb_device *dev, int configuration);
41extern int usb_choose_configuration(struct usb_device *udev); 40extern int usb_choose_configuration(struct usb_device *udev);
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
index b016d38199f2..eb009a457fb5 100644
--- a/drivers/usb/host/xhci-dbg.c
+++ b/drivers/usb/host/xhci-dbg.c
@@ -203,12 +203,12 @@ void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
203 addr, (unsigned int)temp); 203 addr, (unsigned int)temp);
204 204
205 addr = &ir_set->erst_base; 205 addr = &ir_set->erst_base;
206 temp_64 = readq(addr); 206 temp_64 = xhci_read_64(xhci, addr);
207 xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n", 207 xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
208 addr, temp_64); 208 addr, temp_64);
209 209
210 addr = &ir_set->erst_dequeue; 210 addr = &ir_set->erst_dequeue;
211 temp_64 = readq(addr); 211 temp_64 = xhci_read_64(xhci, addr);
212 xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n", 212 xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
213 addr, temp_64); 213 addr, temp_64);
214} 214}
@@ -412,7 +412,7 @@ void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
412{ 412{
413 u64 val; 413 u64 val;
414 414
415 val = readq(&xhci->op_regs->cmd_ring); 415 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
416 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n", 416 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
417 lower_32_bits(val)); 417 lower_32_bits(val));
418 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n", 418 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 873c272b3ef5..bce4391a0e7d 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1958,7 +1958,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1958 xhci_warn(xhci, "WARN something wrong with SW event ring " 1958 xhci_warn(xhci, "WARN something wrong with SW event ring "
1959 "dequeue ptr.\n"); 1959 "dequeue ptr.\n");
1960 /* Update HC event ring dequeue pointer */ 1960 /* Update HC event ring dequeue pointer */
1961 temp = readq(&xhci->ir_set->erst_dequeue); 1961 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1962 temp &= ERST_PTR_MASK; 1962 temp &= ERST_PTR_MASK;
1963 /* Don't clear the EHB bit (which is RW1C) because 1963 /* Don't clear the EHB bit (which is RW1C) because
1964 * there might be more events to service. 1964 * there might be more events to service.
@@ -1967,7 +1967,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1967 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 1967 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1968 "// Write event ring dequeue pointer, " 1968 "// Write event ring dequeue pointer, "
1969 "preserving EHB bit"); 1969 "preserving EHB bit");
1970 writeq(((u64) deq & (u64) ~ERST_PTR_MASK) | temp, 1970 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1971 &xhci->ir_set->erst_dequeue); 1971 &xhci->ir_set->erst_dequeue);
1972} 1972}
1973 1973
@@ -2269,7 +2269,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2269 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2269 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2270 "// Device context base array address = 0x%llx (DMA), %p (virt)", 2270 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2271 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); 2271 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2272 writeq(dma, &xhci->op_regs->dcbaa_ptr); 2272 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2273 2273
2274 /* 2274 /*
2275 * Initialize the ring segment pool. The ring must be a contiguous 2275 * Initialize the ring segment pool. The ring must be a contiguous
@@ -2312,13 +2312,13 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2312 (unsigned long long)xhci->cmd_ring->first_seg->dma); 2312 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2313 2313
2314 /* Set the address in the Command Ring Control register */ 2314 /* Set the address in the Command Ring Control register */
2315 val_64 = readq(&xhci->op_regs->cmd_ring); 2315 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2316 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | 2316 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2317 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | 2317 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2318 xhci->cmd_ring->cycle_state; 2318 xhci->cmd_ring->cycle_state;
2319 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2319 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2320 "// Setting command ring address to 0x%x", val); 2320 "// Setting command ring address to 0x%x", val);
2321 writeq(val_64, &xhci->op_regs->cmd_ring); 2321 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2322 xhci_dbg_cmd_ptrs(xhci); 2322 xhci_dbg_cmd_ptrs(xhci);
2323 2323
2324 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags); 2324 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
@@ -2396,10 +2396,10 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2396 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 2396 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2397 "// Set ERST base address for ir_set 0 = 0x%llx", 2397 "// Set ERST base address for ir_set 0 = 0x%llx",
2398 (unsigned long long)xhci->erst.erst_dma_addr); 2398 (unsigned long long)xhci->erst.erst_dma_addr);
2399 val_64 = readq(&xhci->ir_set->erst_base); 2399 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2400 val_64 &= ERST_PTR_MASK; 2400 val_64 &= ERST_PTR_MASK;
2401 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); 2401 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2402 writeq(val_64, &xhci->ir_set->erst_base); 2402 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2403 2403
2404 /* Set the event ring dequeue address */ 2404 /* Set the event ring dequeue address */
2405 xhci_set_hc_event_deq(xhci); 2405 xhci_set_hc_event_deq(xhci);
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 3c898c12a06b..04f986d9234f 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -142,6 +142,11 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
142 "QUIRK: Resetting on resume"); 142 "QUIRK: Resetting on resume");
143 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 143 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
144 } 144 }
145 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
146 pdev->device == 0x0015 &&
147 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
148 pdev->subsystem_device == 0xc0cd)
149 xhci->quirks |= XHCI_RESET_ON_RESUME;
145 if (pdev->vendor == PCI_VENDOR_ID_VIA) 150 if (pdev->vendor == PCI_VENDOR_ID_VIA)
146 xhci->quirks |= XHCI_RESET_ON_RESUME; 151 xhci->quirks |= XHCI_RESET_ON_RESUME;
147} 152}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index a0b248c34526..909b32a4412f 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -307,13 +307,14 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
307 return 0; 307 return 0;
308 } 308 }
309 309
310 temp_64 = readq(&xhci->op_regs->cmd_ring); 310 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
311 if (!(temp_64 & CMD_RING_RUNNING)) { 311 if (!(temp_64 & CMD_RING_RUNNING)) {
312 xhci_dbg(xhci, "Command ring had been stopped\n"); 312 xhci_dbg(xhci, "Command ring had been stopped\n");
313 return 0; 313 return 0;
314 } 314 }
315 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; 315 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
316 writeq(temp_64 | CMD_RING_ABORT, &xhci->op_regs->cmd_ring); 316 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
317 &xhci->op_regs->cmd_ring);
317 318
318 /* Section 4.6.1.2 of xHCI 1.0 spec says software should 319 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
319 * time the completion od all xHCI commands, including 320 * time the completion od all xHCI commands, including
@@ -2864,8 +2865,9 @@ hw_died:
2864 /* Clear the event handler busy flag (RW1C); 2865 /* Clear the event handler busy flag (RW1C);
2865 * the event ring should be empty. 2866 * the event ring should be empty.
2866 */ 2867 */
2867 temp_64 = readq(&xhci->ir_set->erst_dequeue); 2868 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2868 writeq(temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue); 2869 xhci_write_64(xhci, temp_64 | ERST_EHB,
2870 &xhci->ir_set->erst_dequeue);
2869 spin_unlock(&xhci->lock); 2871 spin_unlock(&xhci->lock);
2870 2872
2871 return IRQ_HANDLED; 2873 return IRQ_HANDLED;
@@ -2877,7 +2879,7 @@ hw_died:
2877 */ 2879 */
2878 while (xhci_handle_event(xhci) > 0) {} 2880 while (xhci_handle_event(xhci) > 0) {}
2879 2881
2880 temp_64 = readq(&xhci->ir_set->erst_dequeue); 2882 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2881 /* If necessary, update the HW's version of the event ring deq ptr. */ 2883 /* If necessary, update the HW's version of the event ring deq ptr. */
2882 if (event_ring_deq != xhci->event_ring->dequeue) { 2884 if (event_ring_deq != xhci->event_ring->dequeue) {
2883 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, 2885 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
@@ -2892,7 +2894,7 @@ hw_died:
2892 2894
2893 /* Clear the event handler busy flag (RW1C); event ring is empty. */ 2895 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2894 temp_64 |= ERST_EHB; 2896 temp_64 |= ERST_EHB;
2895 writeq(temp_64, &xhci->ir_set->erst_dequeue); 2897 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2896 2898
2897 spin_unlock(&xhci->lock); 2899 spin_unlock(&xhci->lock);
2898 2900
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index ad364394885a..3712359d18ba 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -611,7 +611,7 @@ int xhci_run(struct usb_hcd *hcd)
611 xhci_dbg(xhci, "Event ring:\n"); 611 xhci_dbg(xhci, "Event ring:\n");
612 xhci_debug_ring(xhci, xhci->event_ring); 612 xhci_debug_ring(xhci, xhci->event_ring);
613 xhci_dbg_ring_ptrs(xhci, xhci->event_ring); 613 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
614 temp_64 = readq(&xhci->ir_set->erst_dequeue); 614 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
615 temp_64 &= ~ERST_PTR_MASK; 615 temp_64 &= ~ERST_PTR_MASK;
616 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 616 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
617 "ERST deq = 64'h%0lx", (long unsigned int) temp_64); 617 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
@@ -756,11 +756,11 @@ static void xhci_save_registers(struct xhci_hcd *xhci)
756{ 756{
757 xhci->s3.command = readl(&xhci->op_regs->command); 757 xhci->s3.command = readl(&xhci->op_regs->command);
758 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); 758 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
759 xhci->s3.dcbaa_ptr = readq(&xhci->op_regs->dcbaa_ptr); 759 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
760 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); 760 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
761 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); 761 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
762 xhci->s3.erst_base = readq(&xhci->ir_set->erst_base); 762 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
763 xhci->s3.erst_dequeue = readq(&xhci->ir_set->erst_dequeue); 763 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
764 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); 764 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
765 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); 765 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
766} 766}
@@ -769,11 +769,11 @@ static void xhci_restore_registers(struct xhci_hcd *xhci)
769{ 769{
770 writel(xhci->s3.command, &xhci->op_regs->command); 770 writel(xhci->s3.command, &xhci->op_regs->command);
771 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); 771 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
772 writeq(xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); 772 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
773 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); 773 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
774 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); 774 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
775 writeq(xhci->s3.erst_base, &xhci->ir_set->erst_base); 775 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
776 writeq(xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); 776 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
777 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); 777 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
778 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); 778 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
779} 779}
@@ -783,7 +783,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
783 u64 val_64; 783 u64 val_64;
784 784
785 /* step 2: initialize command ring buffer */ 785 /* step 2: initialize command ring buffer */
786 val_64 = readq(&xhci->op_regs->cmd_ring); 786 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
787 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | 787 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
788 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 788 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
789 xhci->cmd_ring->dequeue) & 789 xhci->cmd_ring->dequeue) &
@@ -792,7 +792,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
792 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 792 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
793 "// Setting command ring address to 0x%llx", 793 "// Setting command ring address to 0x%llx",
794 (long unsigned long) val_64); 794 (long unsigned long) val_64);
795 writeq(val_64, &xhci->op_regs->cmd_ring); 795 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
796} 796}
797 797
798/* 798/*
@@ -3842,7 +3842,7 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3842 if (ret) { 3842 if (ret) {
3843 return ret; 3843 return ret;
3844 } 3844 }
3845 temp_64 = readq(&xhci->op_regs->dcbaa_ptr); 3845 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3846 xhci_dbg_trace(xhci, trace_xhci_dbg_address, 3846 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3847 "Op regs DCBAA ptr = %#016llx", temp_64); 3847 "Op regs DCBAA ptr = %#016llx", temp_64);
3848 xhci_dbg_trace(xhci, trace_xhci_dbg_address, 3848 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index f8416639bf31..9154fd6cf24c 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -28,17 +28,6 @@
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/usb/hcd.h> 29#include <linux/usb/hcd.h>
30 30
31/*
32 * Registers should always be accessed with double word or quad word accesses.
33 *
34 * Some xHCI implementations may support 64-bit address pointers. Registers
35 * with 64-bit address pointers should be written to with dword accesses by
36 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
37 * xHCI implementations that do not support 64-bit address pointers will ignore
38 * the high dword, and write order is irrelevant.
39 */
40#include <asm-generic/io-64-nonatomic-lo-hi.h>
41
42/* Code sharing between pci-quirks and xhci hcd */ 31/* Code sharing between pci-quirks and xhci hcd */
43#include "xhci-ext-caps.h" 32#include "xhci-ext-caps.h"
44#include "pci-quirks.h" 33#include "pci-quirks.h"
@@ -1614,6 +1603,34 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1614#define xhci_warn_ratelimited(xhci, fmt, args...) \ 1603#define xhci_warn_ratelimited(xhci, fmt, args...) \
1615 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1604 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1616 1605
1606/*
1607 * Registers should always be accessed with double word or quad word accesses.
1608 *
1609 * Some xHCI implementations may support 64-bit address pointers. Registers
1610 * with 64-bit address pointers should be written to with dword accesses by
1611 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1612 * xHCI implementations that do not support 64-bit address pointers will ignore
1613 * the high dword, and write order is irrelevant.
1614 */
1615static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1616 __le64 __iomem *regs)
1617{
1618 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1619 u64 val_lo = readl(ptr);
1620 u64 val_hi = readl(ptr + 1);
1621 return val_lo + (val_hi << 32);
1622}
1623static inline void xhci_write_64(struct xhci_hcd *xhci,
1624 const u64 val, __le64 __iomem *regs)
1625{
1626 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1627 u32 val_lo = lower_32_bits(val);
1628 u32 val_hi = upper_32_bits(val);
1629
1630 writel(val_lo, ptr);
1631 writel(val_hi, ptr + 1);
1632}
1633
1617static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1634static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1618{ 1635{
1619 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1636 return xhci->quirks & XHCI_LINK_TRB_QUIRK;