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authorPeter Chen <peter.chen@freescale.com>2012-02-29 07:19:46 -0500
committerFelipe Balbi <balbi@ti.com>2012-04-10 12:11:44 -0400
commitf79a60b8785409f5a77767780315ce6d3ea04a44 (patch)
tree4289b1e4502ab9c1eb80b1af84a35ca7809ec8d7 /drivers/usb
parentc04352a590538123f8c93bd87ef1d4bb9e3a64c7 (diff)
usb: fsl_udc_core: prime status stage once data stage has primed
- For Control Read transfer, the ACK handshake on an IN transaction may be corrupted, so the device may not receive the ACK for data stage, the complete irq will not occur at this situation. Therefore, we need to move prime status stage from complete irq routine to the place where the data stage has just primed, or the host will never get ACK for status stage. The above issue has been described at USB2.0 spec chapter 8.5.3.3. - After adding prime status stage just after prime the data stage, there is a potential problem when the status dTD is added before the data stage has primed by hardware. The reason is the device's dTD descriptor has NO direction bit, if data stage (IN) prime hasn't finished, the status stage(OUT) dTD will be added at data stage dTD's Next dTD Pointer, so when the data stage transfer has finished, the status dTD will be primed as IN by hardware, then the host will never receive ACK from the device side for status stage. - Delete below code at fsl_ep_queue: /* Update ep0 state */ if ((ep_index(ep) == 0)) udc->ep0_state = DATA_STATE_XMIT; the udc->ep0_state will be updated again after udc->driver->setup finishes. It is tested at i.mx51 bbg board with g_mass_storage, g_ether, g_serial. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/gadget/fsl_udc_core.c25
1 files changed, 16 insertions, 9 deletions
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 5f94e79cd6b9..55abfb6bd612 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -730,7 +730,7 @@ static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
730 : (1 << (ep_index(ep))); 730 : (1 << (ep_index(ep)));
731 731
732 /* check if the pipe is empty */ 732 /* check if the pipe is empty */
733 if (!(list_empty(&ep->queue))) { 733 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
734 /* Add td to the end */ 734 /* Add td to the end */
735 struct fsl_req *lastreq; 735 struct fsl_req *lastreq;
736 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); 736 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
@@ -918,10 +918,6 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
918 return -ENOMEM; 918 return -ENOMEM;
919 } 919 }
920 920
921 /* Update ep0 state */
922 if ((ep_index(ep) == 0))
923 udc->ep0_state = DATA_STATE_XMIT;
924
925 /* irq handler advances the queue */ 921 /* irq handler advances the queue */
926 if (req != NULL) 922 if (req != NULL)
927 list_add_tail(&req->queue, &ep->queue); 923 list_add_tail(&req->queue, &ep->queue);
@@ -1279,7 +1275,8 @@ static int ep0_prime_status(struct fsl_udc *udc, int direction)
1279 udc->ep0_dir = USB_DIR_OUT; 1275 udc->ep0_dir = USB_DIR_OUT;
1280 1276
1281 ep = &udc->eps[0]; 1277 ep = &udc->eps[0];
1282 udc->ep0_state = WAIT_FOR_OUT_STATUS; 1278 if (udc->ep0_state != DATA_STATE_XMIT)
1279 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1283 1280
1284 req->ep = ep; 1281 req->ep = ep;
1285 req->req.length = 0; 1282 req->req.length = 0;
@@ -1384,6 +1381,9 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1384 1381
1385 list_add_tail(&req->queue, &ep->queue); 1382 list_add_tail(&req->queue, &ep->queue);
1386 udc->ep0_state = DATA_STATE_XMIT; 1383 udc->ep0_state = DATA_STATE_XMIT;
1384 if (ep0_prime_status(udc, EP_DIR_OUT))
1385 ep0stall(udc);
1386
1387 return; 1387 return;
1388stall: 1388stall:
1389 ep0stall(udc); 1389 ep0stall(udc);
@@ -1492,6 +1492,14 @@ static void setup_received_irq(struct fsl_udc *udc,
1492 spin_lock(&udc->lock); 1492 spin_lock(&udc->lock);
1493 udc->ep0_state = (setup->bRequestType & USB_DIR_IN) 1493 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1494 ? DATA_STATE_XMIT : DATA_STATE_RECV; 1494 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1495 /*
1496 * If the data stage is IN, send status prime immediately.
1497 * See 2.0 Spec chapter 8.5.3.3 for detail.
1498 */
1499 if (udc->ep0_state == DATA_STATE_XMIT)
1500 if (ep0_prime_status(udc, EP_DIR_OUT))
1501 ep0stall(udc);
1502
1495 } else { 1503 } else {
1496 /* No data phase, IN status from gadget */ 1504 /* No data phase, IN status from gadget */
1497 udc->ep0_dir = USB_DIR_IN; 1505 udc->ep0_dir = USB_DIR_IN;
@@ -1520,9 +1528,8 @@ static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1520 1528
1521 switch (udc->ep0_state) { 1529 switch (udc->ep0_state) {
1522 case DATA_STATE_XMIT: 1530 case DATA_STATE_XMIT:
1523 /* receive status phase */ 1531 /* already primed at setup_received_irq */
1524 if (ep0_prime_status(udc, EP_DIR_OUT)) 1532 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1525 ep0stall(udc);
1526 break; 1533 break;
1527 case DATA_STATE_RECV: 1534 case DATA_STATE_RECV:
1528 /* send status phase */ 1535 /* send status phase */