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authorMagnus Damm <damm@igel.co.jp>2009-07-22 10:32:03 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-07-23 00:04:10 -0400
commitcf4f1e76c49dacfde0680b170b9a9b6a42f296bb (patch)
tree411f619099e2a4a891080b5c1e227a771a9329ae /drivers/usb
parentc0b96cf639aa1bfa8983f734d4225091aa813e00 (diff)
usb: move r8a66597 register defines
Move r8a66597 hardware register definitions from the host controller header file to the platform data header file. With this change in place we can easily share register definitions between the host controller driver and a future gadget driver. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/host/r8a66597.h366
1 files changed, 0 insertions, 366 deletions
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index eecbd917bc81..228e3fb23854 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -32,372 +32,6 @@
32 32
33#include <linux/usb/r8a66597.h> 33#include <linux/usb/r8a66597.h>
34 34
35#define SYSCFG0 0x00
36#define SYSCFG1 0x02
37#define SYSSTS0 0x04
38#define SYSSTS1 0x06
39#define DVSTCTR0 0x08
40#define DVSTCTR1 0x0A
41#define TESTMODE 0x0C
42#define PINCFG 0x0E
43#define DMA0CFG 0x10
44#define DMA1CFG 0x12
45#define CFIFO 0x14
46#define D0FIFO 0x18
47#define D1FIFO 0x1C
48#define CFIFOSEL 0x20
49#define CFIFOCTR 0x22
50#define CFIFOSIE 0x24
51#define D0FIFOSEL 0x28
52#define D0FIFOCTR 0x2A
53#define D1FIFOSEL 0x2C
54#define D1FIFOCTR 0x2E
55#define INTENB0 0x30
56#define INTENB1 0x32
57#define INTENB2 0x34
58#define BRDYENB 0x36
59#define NRDYENB 0x38
60#define BEMPENB 0x3A
61#define SOFCFG 0x3C
62#define INTSTS0 0x40
63#define INTSTS1 0x42
64#define INTSTS2 0x44
65#define BRDYSTS 0x46
66#define NRDYSTS 0x48
67#define BEMPSTS 0x4A
68#define FRMNUM 0x4C
69#define UFRMNUM 0x4E
70#define USBADDR 0x50
71#define USBREQ 0x54
72#define USBVAL 0x56
73#define USBINDX 0x58
74#define USBLENG 0x5A
75#define DCPCFG 0x5C
76#define DCPMAXP 0x5E
77#define DCPCTR 0x60
78#define PIPESEL 0x64
79#define PIPECFG 0x68
80#define PIPEBUF 0x6A
81#define PIPEMAXP 0x6C
82#define PIPEPERI 0x6E
83#define PIPE1CTR 0x70
84#define PIPE2CTR 0x72
85#define PIPE3CTR 0x74
86#define PIPE4CTR 0x76
87#define PIPE5CTR 0x78
88#define PIPE6CTR 0x7A
89#define PIPE7CTR 0x7C
90#define PIPE8CTR 0x7E
91#define PIPE9CTR 0x80
92#define PIPE1TRE 0x90
93#define PIPE1TRN 0x92
94#define PIPE2TRE 0x94
95#define PIPE2TRN 0x96
96#define PIPE3TRE 0x98
97#define PIPE3TRN 0x9A
98#define PIPE4TRE 0x9C
99#define PIPE4TRN 0x9E
100#define PIPE5TRE 0xA0
101#define PIPE5TRN 0xA2
102#define DEVADD0 0xD0
103#define DEVADD1 0xD2
104#define DEVADD2 0xD4
105#define DEVADD3 0xD6
106#define DEVADD4 0xD8
107#define DEVADD5 0xDA
108#define DEVADD6 0xDC
109#define DEVADD7 0xDE
110#define DEVADD8 0xE0
111#define DEVADD9 0xE2
112#define DEVADDA 0xE4
113
114/* System Configuration Control Register */
115#define XTAL 0xC000 /* b15-14: Crystal selection */
116#define XTAL48 0x8000 /* 48MHz */
117#define XTAL24 0x4000 /* 24MHz */
118#define XTAL12 0x0000 /* 12MHz */
119#define XCKE 0x2000 /* b13: External clock enable */
120#define PLLC 0x0800 /* b11: PLL control */
121#define SCKE 0x0400 /* b10: USB clock enable */
122#define PCSDIS 0x0200 /* b9: not CS wakeup */
123#define LPSME 0x0100 /* b8: Low power sleep mode */
124#define HSE 0x0080 /* b7: Hi-speed enable */
125#define DCFM 0x0040 /* b6: Controller function select */
126#define DRPD 0x0020 /* b5: D+/- pull down control */
127#define DPRPU 0x0010 /* b4: D+ pull up control */
128#define USBE 0x0001 /* b0: USB module operation enable */
129
130/* System Configuration Status Register */
131#define OVCBIT 0x8000 /* b15-14: Over-current bit */
132#define OVCMON 0xC000 /* b15-14: Over-current monitor */
133#define SOFEA 0x0020 /* b5: SOF monitor */
134#define IDMON 0x0004 /* b3: ID-pin monitor */
135#define LNST 0x0003 /* b1-0: D+, D- line status */
136#define SE1 0x0003 /* SE1 */
137#define FS_KSTS 0x0002 /* Full-Speed K State */
138#define FS_JSTS 0x0001 /* Full-Speed J State */
139#define LS_JSTS 0x0002 /* Low-Speed J State */
140#define LS_KSTS 0x0001 /* Low-Speed K State */
141#define SE0 0x0000 /* SE0 */
142
143/* Device State Control Register */
144#define EXTLP0 0x0400 /* b10: External port */
145#define VBOUT 0x0200 /* b9: VBUS output */
146#define WKUP 0x0100 /* b8: Remote wakeup */
147#define RWUPE 0x0080 /* b7: Remote wakeup sense */
148#define USBRST 0x0040 /* b6: USB reset enable */
149#define RESUME 0x0020 /* b5: Resume enable */
150#define UACT 0x0010 /* b4: USB bus enable */
151#define RHST 0x0007 /* b1-0: Reset handshake status */
152#define HSPROC 0x0004 /* HS handshake is processing */
153#define HSMODE 0x0003 /* Hi-Speed mode */
154#define FSMODE 0x0002 /* Full-Speed mode */
155#define LSMODE 0x0001 /* Low-Speed mode */
156#define UNDECID 0x0000 /* Undecided */
157
158/* Test Mode Register */
159#define UTST 0x000F /* b3-0: Test select */
160#define H_TST_PACKET 0x000C /* HOST TEST Packet */
161#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
162#define H_TST_K 0x000A /* HOST TEST K */
163#define H_TST_J 0x0009 /* HOST TEST J */
164#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
165#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
166#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
167#define P_TST_K 0x0002 /* PERI TEST K */
168#define P_TST_J 0x0001 /* PERI TEST J */
169#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
170
171/* Data Pin Configuration Register */
172#define LDRV 0x8000 /* b15: Drive Current Adjust */
173#define VIF1 0x0000 /* VIF = 1.8V */
174#define VIF3 0x8000 /* VIF = 3.3V */
175#define INTA 0x0001 /* b1: USB INT-pin active */
176
177/* DMAx Pin Configuration Register */
178#define DREQA 0x4000 /* b14: Dreq active select */
179#define BURST 0x2000 /* b13: Burst mode */
180#define DACKA 0x0400 /* b10: Dack active select */
181#define DFORM 0x0380 /* b9-7: DMA mode select */
182#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
183#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
184#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
185#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
186#define DENDA 0x0040 /* b6: Dend active select */
187#define PKTM 0x0020 /* b5: Packet mode */
188#define DENDE 0x0010 /* b4: Dend enable */
189#define OBUS 0x0004 /* b2: OUTbus mode */
190
191/* CFIFO/DxFIFO Port Select Register */
192#define RCNT 0x8000 /* b15: Read count mode */
193#define REW 0x4000 /* b14: Buffer rewind */
194#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
195#define DREQE 0x1000 /* b12: DREQ output enable */
196#define MBW_8 0x0000 /* 8bit */
197#define MBW_16 0x0400 /* 16bit */
198#define MBW_32 0x0800 /* 32bit */
199#define BIGEND 0x0100 /* b8: Big endian mode */
200#define BYTE_LITTLE 0x0000 /* little dendian */
201#define BYTE_BIG 0x0100 /* big endifan */
202#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
203#define CURPIPE 0x000F /* b2-0: PIPE select */
204
205/* CFIFO/DxFIFO Port Control Register */
206#define BVAL 0x8000 /* b15: Buffer valid flag */
207#define BCLR 0x4000 /* b14: Buffer clear */
208#define FRDY 0x2000 /* b13: FIFO ready */
209#define DTLN 0x0FFF /* b11-0: FIFO received data length */
210
211/* Interrupt Enable Register 0 */
212#define VBSE 0x8000 /* b15: VBUS interrupt */
213#define RSME 0x4000 /* b14: Resume interrupt */
214#define SOFE 0x2000 /* b13: Frame update interrupt */
215#define DVSE 0x1000 /* b12: Device state transition interrupt */
216#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
217#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
218#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
219#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
220
221/* Interrupt Enable Register 1 */
222#define OVRCRE 0x8000 /* b15: Over-current interrupt */
223#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
224#define DTCHE 0x1000 /* b12: Detach sense interrupt */
225#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
226#define EOFERRE 0x0040 /* b6: EOF error interrupt */
227#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
228#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
229
230/* BRDY Interrupt Enable/Status Register */
231#define BRDY9 0x0200 /* b9: PIPE9 */
232#define BRDY8 0x0100 /* b8: PIPE8 */
233#define BRDY7 0x0080 /* b7: PIPE7 */
234#define BRDY6 0x0040 /* b6: PIPE6 */
235#define BRDY5 0x0020 /* b5: PIPE5 */
236#define BRDY4 0x0010 /* b4: PIPE4 */
237#define BRDY3 0x0008 /* b3: PIPE3 */
238#define BRDY2 0x0004 /* b2: PIPE2 */
239#define BRDY1 0x0002 /* b1: PIPE1 */
240#define BRDY0 0x0001 /* b1: PIPE0 */
241
242/* NRDY Interrupt Enable/Status Register */
243#define NRDY9 0x0200 /* b9: PIPE9 */
244#define NRDY8 0x0100 /* b8: PIPE8 */
245#define NRDY7 0x0080 /* b7: PIPE7 */
246#define NRDY6 0x0040 /* b6: PIPE6 */
247#define NRDY5 0x0020 /* b5: PIPE5 */
248#define NRDY4 0x0010 /* b4: PIPE4 */
249#define NRDY3 0x0008 /* b3: PIPE3 */
250#define NRDY2 0x0004 /* b2: PIPE2 */
251#define NRDY1 0x0002 /* b1: PIPE1 */
252#define NRDY0 0x0001 /* b1: PIPE0 */
253
254/* BEMP Interrupt Enable/Status Register */
255#define BEMP9 0x0200 /* b9: PIPE9 */
256#define BEMP8 0x0100 /* b8: PIPE8 */
257#define BEMP7 0x0080 /* b7: PIPE7 */
258#define BEMP6 0x0040 /* b6: PIPE6 */
259#define BEMP5 0x0020 /* b5: PIPE5 */
260#define BEMP4 0x0010 /* b4: PIPE4 */
261#define BEMP3 0x0008 /* b3: PIPE3 */
262#define BEMP2 0x0004 /* b2: PIPE2 */
263#define BEMP1 0x0002 /* b1: PIPE1 */
264#define BEMP0 0x0001 /* b0: PIPE0 */
265
266/* SOF Pin Configuration Register */
267#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
268#define BRDYM 0x0040 /* b6: BRDY clear timing */
269#define INTL 0x0020 /* b5: Interrupt sense select */
270#define EDGESTS 0x0010 /* b4: */
271#define SOFMODE 0x000C /* b3-2: SOF pin select */
272#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
273#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
274#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
275
276/* Interrupt Status Register 0 */
277#define VBINT 0x8000 /* b15: VBUS interrupt */
278#define RESM 0x4000 /* b14: Resume interrupt */
279#define SOFR 0x2000 /* b13: SOF frame update interrupt */
280#define DVST 0x1000 /* b12: Device state transition interrupt */
281#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
282#define BEMP 0x0400 /* b10: Buffer empty interrupt */
283#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
284#define BRDY 0x0100 /* b8: Buffer ready interrupt */
285#define VBSTS 0x0080 /* b7: VBUS input port */
286#define DVSQ 0x0070 /* b6-4: Device state */
287#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
288#define DS_SPD_ADDR 0x0060 /* Suspend Address */
289#define DS_SPD_DFLT 0x0050 /* Suspend Default */
290#define DS_SPD_POWR 0x0040 /* Suspend Powered */
291#define DS_SUSP 0x0040 /* Suspend */
292#define DS_CNFG 0x0030 /* Configured */
293#define DS_ADDS 0x0020 /* Address */
294#define DS_DFLT 0x0010 /* Default */
295#define DS_POWR 0x0000 /* Powered */
296#define DVSQS 0x0030 /* b5-4: Device state */
297#define VALID 0x0008 /* b3: Setup packet detected flag */
298#define CTSQ 0x0007 /* b2-0: Control transfer stage */
299#define CS_SQER 0x0006 /* Sequence error */
300#define CS_WRND 0x0005 /* Control write nodata status stage */
301#define CS_WRSS 0x0004 /* Control write status stage */
302#define CS_WRDS 0x0003 /* Control write data stage */
303#define CS_RDSS 0x0002 /* Control read status stage */
304#define CS_RDDS 0x0001 /* Control read data stage */
305#define CS_IDST 0x0000 /* Idle or setup stage */
306
307/* Interrupt Status Register 1 */
308#define OVRCR 0x8000 /* b15: Over-current interrupt */
309#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
310#define DTCH 0x1000 /* b12: Detach sense interrupt */
311#define ATTCH 0x0800 /* b11: Attach sense interrupt */
312#define EOFERR 0x0040 /* b6: EOF-error interrupt */
313#define SIGN 0x0020 /* b5: Setup ignore interrupt */
314#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
315
316/* Frame Number Register */
317#define OVRN 0x8000 /* b15: Overrun error */
318#define CRCE 0x4000 /* b14: Received data error */
319#define FRNM 0x07FF /* b10-0: Frame number */
320
321/* Micro Frame Number Register */
322#define UFRNM 0x0007 /* b2-0: Micro frame number */
323
324/* Default Control Pipe Maxpacket Size Register */
325/* Pipe Maxpacket Size Register */
326#define DEVSEL 0xF000 /* b15-14: Device address select */
327#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
328
329/* Default Control Pipe Control Register */
330#define BSTS 0x8000 /* b15: Buffer status */
331#define SUREQ 0x4000 /* b14: Send USB request */
332#define CSCLR 0x2000 /* b13: complete-split status clear */
333#define CSSTS 0x1000 /* b12: complete-split status */
334#define SUREQCLR 0x0800 /* b11: stop setup request */
335#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
336#define SQSET 0x0080 /* b7: Sequence toggle bit set */
337#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
338#define PBUSY 0x0020 /* b5: pipe busy */
339#define PINGE 0x0010 /* b4: ping enable */
340#define CCPL 0x0004 /* b2: Enable control transfer complete */
341#define PID 0x0003 /* b1-0: Response PID */
342#define PID_STALL11 0x0003 /* STALL */
343#define PID_STALL 0x0002 /* STALL */
344#define PID_BUF 0x0001 /* BUF */
345#define PID_NAK 0x0000 /* NAK */
346
347/* Pipe Window Select Register */
348#define PIPENM 0x0007 /* b2-0: Pipe select */
349
350/* Pipe Configuration Register */
351#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
352#define R8A66597_ISO 0xC000 /* Isochronous */
353#define R8A66597_INT 0x8000 /* Interrupt */
354#define R8A66597_BULK 0x4000 /* Bulk */
355#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
356#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
357#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
358#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
359#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
360#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
361
362/* Pipe Buffer Configuration Register */
363#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
364#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
365#define PIPE0BUF 256
366#define PIPExBUF 64
367
368/* Pipe Maxpacket Size Register */
369#define MXPS 0x07FF /* b10-0: Maxpacket size */
370
371/* Pipe Cycle Configuration Register */
372#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
373#define IITV 0x0007 /* b2-0: Isochronous interval */
374
375/* Pipex Control Register */
376#define BSTS 0x8000 /* b15: Buffer status */
377#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
378#define CSCLR 0x2000 /* b13: complete-split status clear */
379#define CSSTS 0x1000 /* b12: complete-split status */
380#define ATREPM 0x0400 /* b10: Auto repeat mode */
381#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
382#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
383#define SQSET 0x0080 /* b7: Sequence toggle bit set */
384#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
385#define PBUSY 0x0020 /* b5: pipe busy */
386#define PID 0x0003 /* b1-0: Response PID */
387
388/* PIPExTRE */
389#define TRENB 0x0200 /* b9: Transaction counter enable */
390#define TRCLR 0x0100 /* b8: Transaction counter clear */
391
392/* PIPExTRN */
393#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
394
395/* DEVADDx */
396#define UPPHUB 0x7800
397#define HUBPORT 0x0700
398#define USBSPD 0x00C0
399#define RTPORT 0x0001
400
401#define R8A66597_MAX_NUM_PIPE 10 35#define R8A66597_MAX_NUM_PIPE 10
402#define R8A66597_BUF_BSIZE 8 36#define R8A66597_BUF_BSIZE 8
403#define R8A66597_MAX_DEVICE 10 37#define R8A66597_MAX_DEVICE 10
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 06:47:53 -0400