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authorFelipe Balbi <balbi@ti.com>2011-05-11 05:44:08 -0400
committerFelipe Balbi <balbi@ti.com>2011-05-13 07:34:04 -0400
commit5c8a86e10a7c164f44537fabdc169fd8b4e7a440 (patch)
tree96fe3eb08b9ae01f62e45b725049d3f2aa6b7bba /drivers/usb
parenta0885924326f79e157847010a9aaf49b058b30dc (diff)
usb: musb: drop unneeded musb_debug trickery
We have a generic way of enabling/disabling different debug messages on a driver called DYNAMIC_PRINTK. Anyone interested in enabling just part of the debug messages, please read the documentation under: Documentation/dynamic-debug-howto.txt for information on how to use that great infrastructure. Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/musb/Kconfig8
-rw-r--r--drivers/usb/musb/Makefile2
-rw-r--r--drivers/usb/musb/am35x.c10
-rw-r--r--drivers/usb/musb/blackfin.c11
-rw-r--r--drivers/usb/musb/cppi_dma.c34
-rw-r--r--drivers/usb/musb/da8xx.c14
-rw-r--r--drivers/usb/musb/davinci.c10
-rw-r--r--drivers/usb/musb/musb_core.c96
-rw-r--r--drivers/usb/musb/musb_debug.h12
-rw-r--r--drivers/usb/musb/musb_gadget.c110
-rw-r--r--drivers/usb/musb/musb_gadget_ep0.c22
-rw-r--r--drivers/usb/musb/musb_host.c106
-rw-r--r--drivers/usb/musb/musb_virthub.c22
-rw-r--r--drivers/usb/musb/musbhsdma.c11
-rw-r--r--drivers/usb/musb/omap2430.c20
-rw-r--r--drivers/usb/musb/tusb6010.c48
-rw-r--r--drivers/usb/musb/tusb6010_omap.c32
17 files changed, 267 insertions, 301 deletions
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 74073b363c30..f90123f4ce52 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -176,11 +176,3 @@ config USB_TUSB_OMAP_DMA
176 help 176 help
177 Enable DMA transfers on TUSB 6010 when OMAP DMA is available. 177 Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
178 178
179config USB_MUSB_DEBUG
180 depends on USB_MUSB_HDRC
181 bool "Enable debugging messages"
182 default n
183 help
184 This enables musb debugging. To set the logging level use the debug
185 module parameter. Starting at level 3, per-transfer (urb, usb_request,
186 packet, or dma transfer) tracing may kick in.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 74df5284894f..4e15281b9e02 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -2,8 +2,6 @@
2# for USB OTG silicon based on Mentor Graphics INVENTRA designs 2# for USB OTG silicon based on Mentor Graphics INVENTRA designs
3# 3#
4 4
5ccflags-$(CONFIG_USB_MUSB_DEBUG) := -DDEBUG
6
7obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o 5obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
8 6
9musb_hdrc-y := musb_core.o 7musb_hdrc-y := musb_core.o
diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
index 9e6209f87d3b..23ac28f98d91 100644
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
@@ -151,7 +151,7 @@ static void otg_timer(unsigned long _musb)
151 * status change events (from the transceiver) otherwise. 151 * status change events (from the transceiver) otherwise.
152 */ 152 */
153 devctl = musb_readb(mregs, MUSB_DEVCTL); 153 devctl = musb_readb(mregs, MUSB_DEVCTL);
154 DBG(7, "Poll devctl %02x (%s)\n", devctl, 154 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
155 otg_state_string(musb->xceiv->state)); 155 otg_state_string(musb->xceiv->state));
156 156
157 spin_lock_irqsave(&musb->lock, flags); 157 spin_lock_irqsave(&musb->lock, flags);
@@ -203,7 +203,7 @@ static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
203 /* Never idle if active, or when VBUS timeout is not set as host */ 203 /* Never idle if active, or when VBUS timeout is not set as host */
204 if (musb->is_active || (musb->a_wait_bcon == 0 && 204 if (musb->is_active || (musb->a_wait_bcon == 0 &&
205 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 205 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
206 DBG(4, "%s active, deleting timer\n", 206 dev_dbg(musb->controller, "%s active, deleting timer\n",
207 otg_state_string(musb->xceiv->state)); 207 otg_state_string(musb->xceiv->state));
208 del_timer(&otg_workaround); 208 del_timer(&otg_workaround);
209 last_timer = jiffies; 209 last_timer = jiffies;
@@ -211,12 +211,12 @@ static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
211 } 211 }
212 212
213 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 213 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
214 DBG(4, "Longer idle timer already pending, ignoring...\n"); 214 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
215 return; 215 return;
216 } 216 }
217 last_timer = timeout; 217 last_timer = timeout;
218 218
219 DBG(4, "%s inactive, starting idle timer for %u ms\n", 219 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
220 otg_state_string(musb->xceiv->state), 220 otg_state_string(musb->xceiv->state),
221 jiffies_to_msecs(timeout - jiffies)); 221 jiffies_to_msecs(timeout - jiffies));
222 mod_timer(&otg_workaround, timeout); 222 mod_timer(&otg_workaround, timeout);
@@ -305,7 +305,7 @@ static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
305 } 305 }
306 306
307 /* NOTE: this must complete power-on within 100 ms. */ 307 /* NOTE: this must complete power-on within 100 ms. */
308 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 308 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
309 drvvbus ? "on" : "off", 309 drvvbus ? "on" : "off",
310 otg_state_string(musb->xceiv->state), 310 otg_state_string(musb->xceiv->state),
311 err ? " ERROR" : "", 311 err ? " ERROR" : "",
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index e141d89656e1..95d75c00404b 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -43,7 +43,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
43 43
44 musb_writew(epio, MUSB_TXCOUNT, len); 44 musb_writew(epio, MUSB_TXCOUNT, len);
45 45
46 DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n", 46 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
47 hw_ep->epnum, fifo, len, src, epio); 47 hw_ep->epnum, fifo, len, src, epio);
48 48
49 dump_fifo_data(src, len); 49 dump_fifo_data(src, len);
@@ -154,7 +154,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
154 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4); 154 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
155 } 155 }
156 } 156 }
157 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 157 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
158 'R', hw_ep->epnum, fifo, len, dst); 158 'R', hw_ep->epnum, fifo, len, dst);
159 159
160 dump_fifo_data(dst, len); 160 dump_fifo_data(dst, len);
@@ -279,13 +279,14 @@ static void musb_conn_timer_handler(unsigned long _musb)
279 } 279 }
280 break; 280 break;
281 default: 281 default:
282 DBG(1, "%s state not handled\n", 282 dev_dbg(musb->controller, "%s state not handled\n",
283 otg_state_string(musb->xceiv->state)); 283 otg_state_string(musb->xceiv->state));
284 break; 284 break;
285 } 285 }
286 spin_unlock_irqrestore(&musb->lock, flags); 286 spin_unlock_irqrestore(&musb->lock, flags);
287 287
288 DBG(4, "state is %s\n", otg_state_string(musb->xceiv->state)); 288 dev_dbg(musb->controller, "state is %s\n",
289 otg_state_string(musb->xceiv->state));
289} 290}
290 291
291static void bfin_musb_enable(struct musb *musb) 292static void bfin_musb_enable(struct musb *musb)
@@ -307,7 +308,7 @@ static void bfin_musb_set_vbus(struct musb *musb, int is_on)
307 value = !value; 308 value = !value;
308 gpio_set_value(musb->config->gpio_vrsel, value); 309 gpio_set_value(musb->config->gpio_vrsel, value);
309 310
310 DBG(1, "VBUS %s, devctl %02x " 311 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
311 /* otg %3x conf %08x prcm %08x */ "\n", 312 /* otg %3x conf %08x prcm %08x */ "\n",
312 otg_state_string(musb->xceiv->state), 313 otg_state_string(musb->xceiv->state),
313 musb_readb(musb->mregs, MUSB_DEVCTL)); 314 musb_readb(musb->mregs, MUSB_DEVCTL));
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index ab434fbd8c35..149f3f310a0a 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -236,7 +236,7 @@ static int cppi_controller_stop(struct dma_controller *c)
236 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG, 236 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
237 DAVINCI_DMA_ALL_CHANNELS_ENABLE); 237 DAVINCI_DMA_ALL_CHANNELS_ENABLE);
238 238
239 DBG(1, "Tearing down RX and TX Channels\n"); 239 dev_dbg(musb->controller, "Tearing down RX and TX Channels\n");
240 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 240 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
241 /* FIXME restructure of txdma to use bds like rxdma */ 241 /* FIXME restructure of txdma to use bds like rxdma */
242 controller->tx[i].last_processed = NULL; 242 controller->tx[i].last_processed = NULL;
@@ -301,13 +301,13 @@ cppi_channel_allocate(struct dma_controller *c,
301 */ 301 */
302 if (transmit) { 302 if (transmit) {
303 if (index >= ARRAY_SIZE(controller->tx)) { 303 if (index >= ARRAY_SIZE(controller->tx)) {
304 DBG(1, "no %cX%d CPPI channel\n", 'T', index); 304 dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'T', index);
305 return NULL; 305 return NULL;
306 } 306 }
307 cppi_ch = controller->tx + index; 307 cppi_ch = controller->tx + index;
308 } else { 308 } else {
309 if (index >= ARRAY_SIZE(controller->rx)) { 309 if (index >= ARRAY_SIZE(controller->rx)) {
310 DBG(1, "no %cX%d CPPI channel\n", 'R', index); 310 dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'R', index);
311 return NULL; 311 return NULL;
312 } 312 }
313 cppi_ch = controller->rx + index; 313 cppi_ch = controller->rx + index;
@@ -318,13 +318,13 @@ cppi_channel_allocate(struct dma_controller *c,
318 * with the other DMA engine too 318 * with the other DMA engine too
319 */ 319 */
320 if (cppi_ch->hw_ep) 320 if (cppi_ch->hw_ep)
321 DBG(1, "re-allocating DMA%d %cX channel %p\n", 321 dev_dbg(musb->controller, "re-allocating DMA%d %cX channel %p\n",
322 index, transmit ? 'T' : 'R', cppi_ch); 322 index, transmit ? 'T' : 'R', cppi_ch);
323 cppi_ch->hw_ep = ep; 323 cppi_ch->hw_ep = ep;
324 cppi_ch->channel.status = MUSB_DMA_STATUS_FREE; 324 cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
325 cppi_ch->channel.max_len = 0x7fffffff; 325 cppi_ch->channel.max_len = 0x7fffffff;
326 326
327 DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R'); 327 dev_dbg(musb->controller, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
328 return &cppi_ch->channel; 328 return &cppi_ch->channel;
329} 329}
330 330
@@ -339,7 +339,7 @@ static void cppi_channel_release(struct dma_channel *channel)
339 c = container_of(channel, struct cppi_channel, channel); 339 c = container_of(channel, struct cppi_channel, channel);
340 tibase = c->controller->tibase; 340 tibase = c->controller->tibase;
341 if (!c->hw_ep) 341 if (!c->hw_ep)
342 DBG(1, "releasing idle DMA channel %p\n", c); 342 dev_dbg(musb->controller, "releasing idle DMA channel %p\n", c);
343 else if (!c->transmit) 343 else if (!c->transmit)
344 core_rxirq_enable(tibase, c->index + 1); 344 core_rxirq_enable(tibase, c->index + 1);
345 345
@@ -597,7 +597,7 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
597 length = min(n_bds * maxpacket, length); 597 length = min(n_bds * maxpacket, length);
598 } 598 }
599 599
600 DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n", 600 dev_dbg(musb->controller, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
601 tx->index, 601 tx->index,
602 maxpacket, 602 maxpacket,
603 rndis ? "rndis" : "transparent", 603 rndis ? "rndis" : "transparent",
@@ -654,7 +654,7 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
654 bd->hw_options |= CPPI_ZERO_SET; 654 bd->hw_options |= CPPI_ZERO_SET;
655 } 655 }
656 656
657 DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n", 657 dev_dbg(musb->controller, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
658 bd, bd->hw_next, bd->hw_bufp, 658 bd, bd->hw_next, bd->hw_bufp,
659 bd->hw_off_len, bd->hw_options); 659 bd->hw_off_len, bd->hw_options);
660 660
@@ -819,7 +819,7 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
819 819
820 length = min(n_bds * maxpacket, length); 820 length = min(n_bds * maxpacket, length);
821 821
822 DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) " 822 dev_dbg(musb->controller, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
823 "dma 0x%llx len %u %u/%u\n", 823 "dma 0x%llx len %u %u/%u\n",
824 rx->index, maxpacket, 824 rx->index, maxpacket,
825 onepacket 825 onepacket
@@ -936,7 +936,7 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
936 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 936 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
937 & 0xffff; 937 & 0xffff;
938 if (i < (2 + n_bds)) { 938 if (i < (2 + n_bds)) {
939 DBG(2, "bufcnt%d underrun - %d (for %d)\n", 939 dev_dbg(musb->controller, "bufcnt%d underrun - %d (for %d)\n",
940 rx->index, i, n_bds); 940 rx->index, i, n_bds);
941 musb_writel(tibase, 941 musb_writel(tibase,
942 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 942 DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
@@ -985,7 +985,7 @@ static int cppi_channel_program(struct dma_channel *ch,
985 /* WARN_ON(1); */ 985 /* WARN_ON(1); */
986 break; 986 break;
987 case MUSB_DMA_STATUS_UNKNOWN: 987 case MUSB_DMA_STATUS_UNKNOWN:
988 DBG(1, "%cX DMA%d not allocated!\n", 988 dev_dbg(musb->controller, "%cX DMA%d not allocated!\n",
989 cppi_ch->transmit ? 'T' : 'R', 989 cppi_ch->transmit ? 'T' : 'R',
990 cppi_ch->index); 990 cppi_ch->index);
991 /* FALLTHROUGH */ 991 /* FALLTHROUGH */
@@ -1040,7 +1040,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1040 if (!completed && (bd->hw_options & CPPI_OWN_SET)) 1040 if (!completed && (bd->hw_options & CPPI_OWN_SET))
1041 break; 1041 break;
1042 1042
1043 DBG(5, "C/RXBD %llx: nxt %08x buf %08x " 1043 dev_dbg(musb->controller, "C/RXBD %llx: nxt %08x buf %08x "
1044 "off.len %08x opt.len %08x (%d)\n", 1044 "off.len %08x opt.len %08x (%d)\n",
1045 (unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp, 1045 (unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
1046 bd->hw_off_len, bd->hw_options, 1046 bd->hw_off_len, bd->hw_options,
@@ -1062,7 +1062,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1062 * CPPI ignores those BDs even though OWN is still set. 1062 * CPPI ignores those BDs even though OWN is still set.
1063 */ 1063 */
1064 completed = true; 1064 completed = true;
1065 DBG(3, "rx short %d/%d (%d)\n", 1065 dev_dbg(musb->controller, "rx short %d/%d (%d)\n",
1066 len, bd->buflen, 1066 len, bd->buflen,
1067 rx->channel.actual_len); 1067 rx->channel.actual_len);
1068 } 1068 }
@@ -1112,7 +1112,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
1112 musb_ep_select(cppi->mregs, rx->index + 1); 1112 musb_ep_select(cppi->mregs, rx->index + 1);
1113 csr = musb_readw(regs, MUSB_RXCSR); 1113 csr = musb_readw(regs, MUSB_RXCSR);
1114 if (csr & MUSB_RXCSR_DMAENAB) { 1114 if (csr & MUSB_RXCSR_DMAENAB) {
1115 DBG(4, "list%d %p/%p, last %llx%s, csr %04x\n", 1115 dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
1116 rx->index, 1116 rx->index,
1117 rx->head, rx->tail, 1117 rx->head, rx->tail,
1118 rx->last_processed 1118 rx->last_processed
@@ -1175,7 +1175,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1175 return IRQ_NONE; 1175 return IRQ_NONE;
1176 } 1176 }
1177 1177
1178 DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx); 1178 dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
1179 1179
1180 /* process TX channels */ 1180 /* process TX channels */
1181 for (index = 0; tx; tx = tx >> 1, index++) { 1181 for (index = 0; tx; tx = tx >> 1, index++) {
@@ -1203,7 +1203,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1203 * that needs to be acknowledged. 1203 * that needs to be acknowledged.
1204 */ 1204 */
1205 if (NULL == bd) { 1205 if (NULL == bd) {
1206 DBG(1, "null BD\n"); 1206 dev_dbg(musb->controller, "null BD\n");
1207 musb_writel(&tx_ram->tx_complete, 0, 0); 1207 musb_writel(&tx_ram->tx_complete, 0, 0);
1208 continue; 1208 continue;
1209 } 1209 }
@@ -1218,7 +1218,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
1218 if (bd->hw_options & CPPI_OWN_SET) 1218 if (bd->hw_options & CPPI_OWN_SET)
1219 break; 1219 break;
1220 1220
1221 DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n", 1221 dev_dbg(musb->controller, "C/TXBD %p n %x b %x off %x opt %x\n",
1222 bd, bd->hw_next, bd->hw_bufp, 1222 bd, bd->hw_next, bd->hw_bufp,
1223 bd->hw_off_len, bd->hw_options); 1223 bd->hw_off_len, bd->hw_options);
1224 1224
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index 0d8984993a38..662ed34980bd 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -199,7 +199,7 @@ static void otg_timer(unsigned long _musb)
199 * status change events (from the transceiver) otherwise. 199 * status change events (from the transceiver) otherwise.
200 */ 200 */
201 devctl = musb_readb(mregs, MUSB_DEVCTL); 201 devctl = musb_readb(mregs, MUSB_DEVCTL);
202 DBG(7, "Poll devctl %02x (%s)\n", devctl, 202 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
203 otg_state_string(musb->xceiv->state)); 203 otg_state_string(musb->xceiv->state));
204 204
205 spin_lock_irqsave(&musb->lock, flags); 205 spin_lock_irqsave(&musb->lock, flags);
@@ -274,7 +274,7 @@ static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
274 /* Never idle if active, or when VBUS timeout is not set as host */ 274 /* Never idle if active, or when VBUS timeout is not set as host */
275 if (musb->is_active || (musb->a_wait_bcon == 0 && 275 if (musb->is_active || (musb->a_wait_bcon == 0 &&
276 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 276 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
277 DBG(4, "%s active, deleting timer\n", 277 dev_dbg(musb->controller, "%s active, deleting timer\n",
278 otg_state_string(musb->xceiv->state)); 278 otg_state_string(musb->xceiv->state));
279 del_timer(&otg_workaround); 279 del_timer(&otg_workaround);
280 last_timer = jiffies; 280 last_timer = jiffies;
@@ -282,12 +282,12 @@ static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
282 } 282 }
283 283
284 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 284 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
285 DBG(4, "Longer idle timer already pending, ignoring...\n"); 285 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
286 return; 286 return;
287 } 287 }
288 last_timer = timeout; 288 last_timer = timeout;
289 289
290 DBG(4, "%s inactive, starting idle timer for %u ms\n", 290 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
291 otg_state_string(musb->xceiv->state), 291 otg_state_string(musb->xceiv->state),
292 jiffies_to_msecs(timeout - jiffies)); 292 jiffies_to_msecs(timeout - jiffies));
293 mod_timer(&otg_workaround, timeout); 293 mod_timer(&otg_workaround, timeout);
@@ -314,7 +314,7 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
314 goto eoi; 314 goto eoi;
315 315
316 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); 316 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
317 DBG(4, "USB IRQ %08x\n", status); 317 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
318 318
319 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT; 319 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
320 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT; 320 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
@@ -366,7 +366,7 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
366 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 366 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
367 } 367 }
368 368
369 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 369 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
370 drvvbus ? "on" : "off", 370 drvvbus ? "on" : "off",
371 otg_state_string(musb->xceiv->state), 371 otg_state_string(musb->xceiv->state),
372 err ? " ERROR" : "", 372 err ? " ERROR" : "",
@@ -413,7 +413,7 @@ static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
413 break; 413 break;
414#endif 414#endif
415 default: 415 default:
416 DBG(2, "Trying to set unsupported mode %u\n", musb_mode); 416 dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
417 } 417 }
418 418
419 __raw_writel(cfgchip2, CFGCHIP2); 419 __raw_writel(cfgchip2, CFGCHIP2);
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 3661b81a9571..2a2adf6492cd 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -220,7 +220,7 @@ static void otg_timer(unsigned long _musb)
220 * status change events (from the transceiver) otherwise. 220 * status change events (from the transceiver) otherwise.
221 */ 221 */
222 devctl = musb_readb(mregs, MUSB_DEVCTL); 222 devctl = musb_readb(mregs, MUSB_DEVCTL);
223 DBG(7, "poll devctl %02x (%s)\n", devctl, 223 dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
224 otg_state_string(musb->xceiv->state)); 224 otg_state_string(musb->xceiv->state));
225 225
226 spin_lock_irqsave(&musb->lock, flags); 226 spin_lock_irqsave(&musb->lock, flags);
@@ -298,7 +298,7 @@ static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
298 /* ack and handle non-CPPI interrupts */ 298 /* ack and handle non-CPPI interrupts */
299 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); 299 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
300 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); 300 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
301 DBG(4, "IRQ %08x\n", tmp); 301 dev_dbg(musb->controller, "IRQ %08x\n", tmp);
302 302
303 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) 303 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
304 >> DAVINCI_USB_RXINT_SHIFT; 304 >> DAVINCI_USB_RXINT_SHIFT;
@@ -355,7 +355,7 @@ static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
355 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. 355 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
356 */ 356 */
357 davinci_musb_source_power(musb, drvvbus, 0); 357 davinci_musb_source_power(musb, drvvbus, 0);
358 DBG(2, "VBUS %s (%s)%s, devctl %02x\n", 358 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
359 drvvbus ? "on" : "off", 359 drvvbus ? "on" : "off",
360 otg_state_string(musb->xceiv->state), 360 otg_state_string(musb->xceiv->state),
361 err ? " ERROR" : "", 361 err ? " ERROR" : "",
@@ -485,7 +485,7 @@ static int davinci_musb_exit(struct musb *musb)
485 break; 485 break;
486 if ((devctl & MUSB_DEVCTL_VBUS) != warn) { 486 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
487 warn = devctl & MUSB_DEVCTL_VBUS; 487 warn = devctl & MUSB_DEVCTL_VBUS;
488 DBG(1, "VBUS %d\n", 488 dev_dbg(musb->controller, "VBUS %d\n",
489 warn >> MUSB_DEVCTL_VBUS_SHIFT); 489 warn >> MUSB_DEVCTL_VBUS_SHIFT);
490 } 490 }
491 msleep(1000); 491 msleep(1000);
@@ -494,7 +494,7 @@ static int davinci_musb_exit(struct musb *musb)
494 494
495 /* in OTG mode, another host might be connected */ 495 /* in OTG mode, another host might be connected */
496 if (devctl & MUSB_DEVCTL_VBUS) 496 if (devctl & MUSB_DEVCTL_VBUS)
497 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl); 497 dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
498 } 498 }
499 499
500 phy_off(); 500 phy_off();
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 9a280872c2b4..6e3988cb6e8a 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -104,10 +104,6 @@
104#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 104#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
105 105
106 106
107unsigned musb_debug;
108module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
109MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
110
111#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 107#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
112#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 108#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113 109
@@ -157,10 +153,8 @@ static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 153 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) { 154 & MUSB_ULPI_REG_CMPLT)) {
159 i++; 155 i++;
160 if (i == 10000) { 156 if (i == 10000)
161 DBG(3, "ULPI read timed out\n");
162 return -ETIMEDOUT; 157 return -ETIMEDOUT;
163 }
164 158
165 } 159 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 160 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
@@ -190,10 +184,8 @@ static int musb_ulpi_write(struct otg_transceiver *otg,
190 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 184 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
191 & MUSB_ULPI_REG_CMPLT)) { 185 & MUSB_ULPI_REG_CMPLT)) {
192 i++; 186 i++;
193 if (i == 10000) { 187 if (i == 10000)
194 DBG(3, "ULPI write timed out\n");
195 return -ETIMEDOUT; 188 return -ETIMEDOUT;
196 }
197 } 189 }
198 190
199 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 191 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
@@ -221,11 +213,12 @@ static struct otg_io_access_ops musb_ulpi_access = {
221 */ 213 */
222void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 214void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
223{ 215{
216 struct musb *musb = hw_ep->musb;
224 void __iomem *fifo = hw_ep->fifo; 217 void __iomem *fifo = hw_ep->fifo;
225 218
226 prefetch((u8 *)src); 219 prefetch((u8 *)src);
227 220
228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 221 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'T', hw_ep->epnum, fifo, len, src); 222 'T', hw_ep->epnum, fifo, len, src);
230 223
231 /* we can't assume unaligned reads work */ 224 /* we can't assume unaligned reads work */
@@ -262,9 +255,10 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
262 */ 255 */
263void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 256void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
264{ 257{
258 struct musb *musb = hw_ep->musb;
265 void __iomem *fifo = hw_ep->fifo; 259 void __iomem *fifo = hw_ep->fifo;
266 260
267 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 261 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
268 'R', hw_ep->epnum, fifo, len, dst); 262 'R', hw_ep->epnum, fifo, len, dst);
269 263
270 /* we can't assume unaligned writes work */ 264 /* we can't assume unaligned writes work */
@@ -346,20 +340,20 @@ void musb_otg_timer_func(unsigned long data)
346 spin_lock_irqsave(&musb->lock, flags); 340 spin_lock_irqsave(&musb->lock, flags);
347 switch (musb->xceiv->state) { 341 switch (musb->xceiv->state) {
348 case OTG_STATE_B_WAIT_ACON: 342 case OTG_STATE_B_WAIT_ACON:
349 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 343 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
350 musb_g_disconnect(musb); 344 musb_g_disconnect(musb);
351 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 345 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
352 musb->is_active = 0; 346 musb->is_active = 0;
353 break; 347 break;
354 case OTG_STATE_A_SUSPEND: 348 case OTG_STATE_A_SUSPEND:
355 case OTG_STATE_A_WAIT_BCON: 349 case OTG_STATE_A_WAIT_BCON:
356 DBG(1, "HNP: %s timeout\n", 350 dev_dbg(musb->controller, "HNP: %s timeout\n",
357 otg_state_string(musb->xceiv->state)); 351 otg_state_string(musb->xceiv->state));
358 musb_platform_set_vbus(musb, 0); 352 musb_platform_set_vbus(musb, 0);
359 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 353 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
360 break; 354 break;
361 default: 355 default:
362 DBG(1, "HNP: Unhandled mode %s\n", 356 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
363 otg_state_string(musb->xceiv->state)); 357 otg_state_string(musb->xceiv->state));
364 } 358 }
365 musb->ignore_disconnect = 0; 359 musb->ignore_disconnect = 0;
@@ -375,16 +369,16 @@ void musb_hnp_stop(struct musb *musb)
375 void __iomem *mbase = musb->mregs; 369 void __iomem *mbase = musb->mregs;
376 u8 reg; 370 u8 reg;
377 371
378 DBG(1, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 372 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
379 373
380 switch (musb->xceiv->state) { 374 switch (musb->xceiv->state) {
381 case OTG_STATE_A_PERIPHERAL: 375 case OTG_STATE_A_PERIPHERAL:
382 musb_g_disconnect(musb); 376 musb_g_disconnect(musb);
383 DBG(1, "HNP: back to %s\n", 377 dev_dbg(musb->controller, "HNP: back to %s\n",
384 otg_state_string(musb->xceiv->state)); 378 otg_state_string(musb->xceiv->state));
385 break; 379 break;
386 case OTG_STATE_B_HOST: 380 case OTG_STATE_B_HOST:
387 DBG(1, "HNP: Disabling HR\n"); 381 dev_dbg(musb->controller, "HNP: Disabling HR\n");
388 hcd->self.is_b_host = 0; 382 hcd->self.is_b_host = 0;
389 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 383 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
390 MUSB_DEV_MODE(musb); 384 MUSB_DEV_MODE(musb);
@@ -394,7 +388,7 @@ void musb_hnp_stop(struct musb *musb)
394 /* REVISIT: Start SESSION_REQUEST here? */ 388 /* REVISIT: Start SESSION_REQUEST here? */
395 break; 389 break;
396 default: 390 default:
397 DBG(1, "HNP: Stopping in unknown state %s\n", 391 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
398 otg_state_string(musb->xceiv->state)); 392 otg_state_string(musb->xceiv->state));
399 } 393 }
400 394
@@ -425,7 +419,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
425{ 419{
426 irqreturn_t handled = IRQ_NONE; 420 irqreturn_t handled = IRQ_NONE;
427 421
428 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 422 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
429 int_usb); 423 int_usb);
430 424
431 /* in host mode, the peripheral may issue remote wakeup. 425 /* in host mode, the peripheral may issue remote wakeup.
@@ -434,7 +428,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
434 */ 428 */
435 if (int_usb & MUSB_INTR_RESUME) { 429 if (int_usb & MUSB_INTR_RESUME) {
436 handled = IRQ_HANDLED; 430 handled = IRQ_HANDLED;
437 DBG(3, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 431 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
438 432
439 if (devctl & MUSB_DEVCTL_HM) { 433 if (devctl & MUSB_DEVCTL_HM) {
440#ifdef CONFIG_USB_MUSB_HDRC_HCD 434#ifdef CONFIG_USB_MUSB_HDRC_HCD
@@ -449,7 +443,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
449 if (power & MUSB_POWER_SUSPENDM) { 443 if (power & MUSB_POWER_SUSPENDM) {
450 /* spurious */ 444 /* spurious */
451 musb->int_usb &= ~MUSB_INTR_SUSPEND; 445 musb->int_usb &= ~MUSB_INTR_SUSPEND;
452 DBG(2, "Spurious SUSPENDM\n"); 446 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
453 break; 447 break;
454 } 448 }
455 449
@@ -521,11 +515,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
521 515
522 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 516 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
523 && (devctl & MUSB_DEVCTL_BDEVICE)) { 517 && (devctl & MUSB_DEVCTL_BDEVICE)) {
524 DBG(3, "SessReq while on B state\n"); 518 dev_dbg(musb->controller, "SessReq while on B state\n");
525 return IRQ_HANDLED; 519 return IRQ_HANDLED;
526 } 520 }
527 521
528 DBG(1, "SESSION_REQUEST (%s)\n", 522 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
529 otg_state_string(musb->xceiv->state)); 523 otg_state_string(musb->xceiv->state));
530 524
531 /* IRQ arrives from ID pin sense or (later, if VBUS power 525 /* IRQ arrives from ID pin sense or (later, if VBUS power
@@ -590,7 +584,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
590 break; 584 break;
591 } 585 }
592 586
593 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 587 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
594 otg_state_string(musb->xceiv->state), 588 otg_state_string(musb->xceiv->state),
595 devctl, 589 devctl,
596 ({ char *s; 590 ({ char *s;
@@ -616,7 +610,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
616 610
617#endif 611#endif
618 if (int_usb & MUSB_INTR_SUSPEND) { 612 if (int_usb & MUSB_INTR_SUSPEND) {
619 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 613 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
620 otg_state_string(musb->xceiv->state), devctl, power); 614 otg_state_string(musb->xceiv->state), devctl, power);
621 handled = IRQ_HANDLED; 615 handled = IRQ_HANDLED;
622 616
@@ -649,7 +643,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
649 if (musb->is_active) { 643 if (musb->is_active) {
650#ifdef CONFIG_USB_MUSB_OTG 644#ifdef CONFIG_USB_MUSB_OTG
651 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 645 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
652 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 646 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
653 mod_timer(&musb->otg_timer, jiffies 647 mod_timer(&musb->otg_timer, jiffies
654 + msecs_to_jiffies( 648 + msecs_to_jiffies(
655 OTG_TIME_B_ASE0_BRST)); 649 OTG_TIME_B_ASE0_BRST));
@@ -668,7 +662,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
668 break; 662 break;
669 case OTG_STATE_B_HOST: 663 case OTG_STATE_B_HOST:
670 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 664 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
671 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 665 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
672 break; 666 break;
673 default: 667 default:
674 /* "should not happen" */ 668 /* "should not happen" */
@@ -711,14 +705,14 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
711 switch (musb->xceiv->state) { 705 switch (musb->xceiv->state) {
712 case OTG_STATE_B_PERIPHERAL: 706 case OTG_STATE_B_PERIPHERAL:
713 if (int_usb & MUSB_INTR_SUSPEND) { 707 if (int_usb & MUSB_INTR_SUSPEND) {
714 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 708 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
715 int_usb &= ~MUSB_INTR_SUSPEND; 709 int_usb &= ~MUSB_INTR_SUSPEND;
716 goto b_host; 710 goto b_host;
717 } else 711 } else
718 DBG(1, "CONNECT as b_peripheral???\n"); 712 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
719 break; 713 break;
720 case OTG_STATE_B_WAIT_ACON: 714 case OTG_STATE_B_WAIT_ACON:
721 DBG(1, "HNP: CONNECT, now b_host\n"); 715 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
722b_host: 716b_host:
723 musb->xceiv->state = OTG_STATE_B_HOST; 717 musb->xceiv->state = OTG_STATE_B_HOST;
724 hcd->self.is_b_host = 1; 718 hcd->self.is_b_host = 1;
@@ -741,13 +735,13 @@ b_host:
741 else 735 else
742 usb_hcd_resume_root_hub(hcd); 736 usb_hcd_resume_root_hub(hcd);
743 737
744 DBG(1, "CONNECT (%s) devctl %02x\n", 738 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
745 otg_state_string(musb->xceiv->state), devctl); 739 otg_state_string(musb->xceiv->state), devctl);
746 } 740 }
747#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 741#endif /* CONFIG_USB_MUSB_HDRC_HCD */
748 742
749 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 743 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
750 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 744 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
751 otg_state_string(musb->xceiv->state), 745 otg_state_string(musb->xceiv->state),
752 MUSB_MODE(musb), devctl); 746 MUSB_MODE(musb), devctl);
753 handled = IRQ_HANDLED; 747 handled = IRQ_HANDLED;
@@ -810,13 +804,13 @@ b_host:
810 * stop the session. 804 * stop the session.
811 */ 805 */
812 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 806 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
813 DBG(1, "BABBLE devctl: %02x\n", devctl); 807 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
814 else { 808 else {
815 ERR("Stopping host session -- babble\n"); 809 ERR("Stopping host session -- babble\n");
816 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 810 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
817 } 811 }
818 } else if (is_peripheral_capable()) { 812 } else if (is_peripheral_capable()) {
819 DBG(1, "BUS RESET as %s\n", 813 dev_dbg(musb->controller, "BUS RESET as %s\n",
820 otg_state_string(musb->xceiv->state)); 814 otg_state_string(musb->xceiv->state));
821 switch (musb->xceiv->state) { 815 switch (musb->xceiv->state) {
822#ifdef CONFIG_USB_OTG 816#ifdef CONFIG_USB_OTG
@@ -830,7 +824,7 @@ b_host:
830 /* FALLTHROUGH */ 824 /* FALLTHROUGH */
831 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 825 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
832 /* never use invalid T(a_wait_bcon) */ 826 /* never use invalid T(a_wait_bcon) */
833 DBG(1, "HNP: in %s, %d msec timeout\n", 827 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
834 otg_state_string(musb->xceiv->state), 828 otg_state_string(musb->xceiv->state),
835 TA_WAIT_BCON(musb)); 829 TA_WAIT_BCON(musb));
836 mod_timer(&musb->otg_timer, jiffies 830 mod_timer(&musb->otg_timer, jiffies
@@ -842,7 +836,7 @@ b_host:
842 musb_g_reset(musb); 836 musb_g_reset(musb);
843 break; 837 break;
844 case OTG_STATE_B_WAIT_ACON: 838 case OTG_STATE_B_WAIT_ACON:
845 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 839 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
846 otg_state_string(musb->xceiv->state)); 840 otg_state_string(musb->xceiv->state));
847 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 841 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
848 musb_g_reset(musb); 842 musb_g_reset(musb);
@@ -855,7 +849,7 @@ b_host:
855 musb_g_reset(musb); 849 musb_g_reset(musb);
856 break; 850 break;
857 default: 851 default:
858 DBG(1, "Unhandled BUS RESET as %s\n", 852 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
859 otg_state_string(musb->xceiv->state)); 853 otg_state_string(musb->xceiv->state));
860 } 854 }
861 } 855 }
@@ -879,7 +873,7 @@ b_host:
879 u8 epnum; 873 u8 epnum;
880 u16 frame; 874 u16 frame;
881 875
882 DBG(6, "START_OF_FRAME\n"); 876 dev_dbg(musb->controller, "START_OF_FRAME\n");
883 handled = IRQ_HANDLED; 877 handled = IRQ_HANDLED;
884 878
885 /* start any periodic Tx transfers waiting for current frame */ 879 /* start any periodic Tx transfers waiting for current frame */
@@ -921,7 +915,7 @@ void musb_start(struct musb *musb)
921 void __iomem *regs = musb->mregs; 915 void __iomem *regs = musb->mregs;
922 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 916 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
923 917
924 DBG(2, "<== devctl %02x\n", devctl); 918 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
925 919
926 /* Set INT enable registers, enable interrupts */ 920 /* Set INT enable registers, enable interrupts */
927 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 921 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
@@ -998,7 +992,7 @@ void musb_stop(struct musb *musb)
998 /* stop IRQs, timers, ... */ 992 /* stop IRQs, timers, ... */
999 musb_platform_disable(musb); 993 musb_platform_disable(musb);
1000 musb_generic_disable(musb); 994 musb_generic_disable(musb);
1001 DBG(3, "HDRC disabled\n"); 995 dev_dbg(musb->controller, "HDRC disabled\n");
1002 996
1003 /* FIXME 997 /* FIXME
1004 * - mark host and/or peripheral drivers unusable/inactive 998 * - mark host and/or peripheral drivers unusable/inactive
@@ -1344,7 +1338,7 @@ static int __init ep_config_from_hw(struct musb *musb)
1344 void *mbase = musb->mregs; 1338 void *mbase = musb->mregs;
1345 int ret = 0; 1339 int ret = 0;
1346 1340
1347 DBG(2, "<== static silicon ep config\n"); 1341 dev_dbg(musb->controller, "<== static silicon ep config\n");
1348 1342
1349 /* FIXME pick up ep0 maxpacket size */ 1343 /* FIXME pick up ep0 maxpacket size */
1350 1344
@@ -1491,7 +1485,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1491#endif 1485#endif
1492 1486
1493 if (hw_ep->max_packet_sz_tx) { 1487 if (hw_ep->max_packet_sz_tx) {
1494 DBG(1, 1488 dev_dbg(musb->controller,
1495 "%s: hw_ep %d%s, %smax %d\n", 1489 "%s: hw_ep %d%s, %smax %d\n",
1496 musb_driver_name, i, 1490 musb_driver_name, i,
1497 hw_ep->is_shared_fifo ? "shared" : "tx", 1491 hw_ep->is_shared_fifo ? "shared" : "tx",
@@ -1500,7 +1494,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1500 hw_ep->max_packet_sz_tx); 1494 hw_ep->max_packet_sz_tx);
1501 } 1495 }
1502 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1496 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1503 DBG(1, 1497 dev_dbg(musb->controller,
1504 "%s: hw_ep %d%s, %smax %d\n", 1498 "%s: hw_ep %d%s, %smax %d\n",
1505 musb_driver_name, i, 1499 musb_driver_name, i,
1506 "rx", 1500 "rx",
@@ -1509,7 +1503,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
1509 hw_ep->max_packet_sz_rx); 1503 hw_ep->max_packet_sz_rx);
1510 } 1504 }
1511 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1505 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1512 DBG(1, "hw_ep %d not configured\n", i); 1506 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1513 } 1507 }
1514 1508
1515 return 0; 1509 return 0;
@@ -1562,14 +1556,14 @@ irqreturn_t musb_interrupt(struct musb *musb)
1562 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1556 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1563 power = musb_readb(musb->mregs, MUSB_POWER); 1557 power = musb_readb(musb->mregs, MUSB_POWER);
1564 1558
1565 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1559 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1566 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1560 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1567 musb->int_usb, musb->int_tx, musb->int_rx); 1561 musb->int_usb, musb->int_tx, musb->int_rx);
1568 1562
1569#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1563#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1570 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1564 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1571 if (!musb->gadget_driver) { 1565 if (!musb->gadget_driver) {
1572 DBG(5, "No gadget driver loaded\n"); 1566 dev_dbg(musb->controller, "No gadget driver loaded\n");
1573 return IRQ_HANDLED; 1567 return IRQ_HANDLED;
1574 } 1568 }
1575#endif 1569#endif
@@ -2060,7 +2054,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2060 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2054 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2061 2055
2062 hcd->self.uses_pio_for_control = 1; 2056 hcd->self.uses_pio_for_control = 1;
2063 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2057 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2064 "HOST", status, 2058 "HOST", status,
2065 musb_readb(musb->mregs, MUSB_DEVCTL), 2059 musb_readb(musb->mregs, MUSB_DEVCTL),
2066 (musb_readb(musb->mregs, MUSB_DEVCTL) 2060 (musb_readb(musb->mregs, MUSB_DEVCTL)
@@ -2074,7 +2068,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2074 2068
2075 status = musb_gadget_setup(musb); 2069 status = musb_gadget_setup(musb);
2076 2070
2077 DBG(1, "%s mode, status %d, dev%02x\n", 2071 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2078 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2072 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2079 status, 2073 status,
2080 musb_readb(musb->mregs, MUSB_DEVCTL)); 2074 musb_readb(musb->mregs, MUSB_DEVCTL));
@@ -2456,8 +2450,8 @@ static int __init musb_init(void)
2456#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2450#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2457 "host" 2451 "host"
2458#endif 2452#endif
2459 ", debug=%d\n", 2453 ,
2460 musb_driver_name, musb_debug); 2454 musb_driver_name);
2461 return platform_driver_probe(&musb_driver, musb_probe); 2455 return platform_driver_probe(&musb_driver, musb_probe);
2462} 2456}
2463 2457
diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
index f958a49a0124..742eada5002e 100644
--- a/drivers/usb/musb/musb_debug.h
+++ b/drivers/usb/musb/musb_debug.h
@@ -42,18 +42,6 @@
42#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args) 42#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
43#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args) 43#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
44 44
45#define DBG(level, format, args...) do { \
46 if (_dbg_level(level)) \
47 pr_debug("%s %d: " format, __func__, __LINE__, ## args); \
48 } while (0)
49
50extern unsigned musb_debug;
51
52static inline int _dbg_level(unsigned l)
53{
54 return musb_debug >= l;
55}
56
57#ifdef CONFIG_DEBUG_FS 45#ifdef CONFIG_DEBUG_FS
58extern int musb_init_debugfs(struct musb *musb); 46extern int musb_init_debugfs(struct musb *musb);
59extern void musb_exit_debugfs(struct musb *musb); 47extern void musb_exit_debugfs(struct musb *musb);
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index cfbee4dcfc13..d34ff408c815 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -147,7 +147,8 @@ static inline void unmap_dma_buffer(struct musb_request *request,
147 return; 147 return;
148 148
149 if (request->request.dma == DMA_ADDR_INVALID) { 149 if (request->request.dma == DMA_ADDR_INVALID) {
150 DBG(20, "not unmapping a never mapped buffer\n"); 150 dev_vdbg(musb->controller,
151 "not unmapping a never mapped buffer\n");
151 return; 152 return;
152 } 153 }
153 if (request->map_state == MUSB_MAPPED) { 154 if (request->map_state == MUSB_MAPPED) {
@@ -198,11 +199,11 @@ __acquires(ep->musb->lock)
198 spin_unlock(&musb->lock); 199 spin_unlock(&musb->lock);
199 unmap_dma_buffer(req, musb); 200 unmap_dma_buffer(req, musb);
200 if (request->status == 0) 201 if (request->status == 0)
201 DBG(5, "%s done request %p, %d/%d\n", 202 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
202 ep->end_point.name, request, 203 ep->end_point.name, request,
203 req->request.actual, req->request.length); 204 req->request.actual, req->request.length);
204 else 205 else
205 DBG(2, "%s request %p, %d/%d fault %d\n", 206 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
206 ep->end_point.name, request, 207 ep->end_point.name, request,
207 req->request.actual, req->request.length, 208 req->request.actual, req->request.length,
208 request->status); 209 request->status);
@@ -219,6 +220,7 @@ __acquires(ep->musb->lock)
219 */ 220 */
220static void nuke(struct musb_ep *ep, const int status) 221static void nuke(struct musb_ep *ep, const int status)
221{ 222{
223 struct musb *musb = ep->musb;
222 struct musb_request *req = NULL; 224 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; 225 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
224 226
@@ -246,7 +248,8 @@ static void nuke(struct musb_ep *ep, const int status)
246 } 248 }
247 249
248 value = c->channel_abort(ep->dma); 250 value = c->channel_abort(ep->dma);
249 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); 251 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
252 ep->name, value);
250 c->channel_release(ep->dma); 253 c->channel_release(ep->dma);
251 ep->dma = NULL; 254 ep->dma = NULL;
252 } 255 }
@@ -329,7 +332,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
329 332
330 /* we shouldn't get here while DMA is active ... but we do ... */ 333 /* we shouldn't get here while DMA is active ... but we do ... */
331 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 334 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
332 DBG(4, "dma pending...\n"); 335 dev_dbg(musb->controller, "dma pending...\n");
333 return; 336 return;
334 } 337 }
335 338
@@ -341,18 +344,18 @@ static void txstate(struct musb *musb, struct musb_request *req)
341 (int)(request->length - request->actual)); 344 (int)(request->length - request->actual));
342 345
343 if (csr & MUSB_TXCSR_TXPKTRDY) { 346 if (csr & MUSB_TXCSR_TXPKTRDY) {
344 DBG(5, "%s old packet still ready , txcsr %03x\n", 347 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
345 musb_ep->end_point.name, csr); 348 musb_ep->end_point.name, csr);
346 return; 349 return;
347 } 350 }
348 351
349 if (csr & MUSB_TXCSR_P_SENDSTALL) { 352 if (csr & MUSB_TXCSR_P_SENDSTALL) {
350 DBG(5, "%s stalling, txcsr %03x\n", 353 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
351 musb_ep->end_point.name, csr); 354 musb_ep->end_point.name, csr);
352 return; 355 return;
353 } 356 }
354 357
355 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", 358 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
356 epnum, musb_ep->packet_sz, fifo_count, 359 epnum, musb_ep->packet_sz, fifo_count,
357 csr); 360 csr);
358 361
@@ -469,7 +472,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
469 } 472 }
470 473
471 /* host may already have the data when this message shows... */ 474 /* host may already have the data when this message shows... */
472 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", 475 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
473 musb_ep->end_point.name, use_dma ? "dma" : "pio", 476 musb_ep->end_point.name, use_dma ? "dma" : "pio",
474 request->actual, request->length, 477 request->actual, request->length,
475 musb_readw(epio, MUSB_TXCSR), 478 musb_readw(epio, MUSB_TXCSR),
@@ -496,7 +499,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
496 request = &req->request; 499 request = &req->request;
497 500
498 csr = musb_readw(epio, MUSB_TXCSR); 501 csr = musb_readw(epio, MUSB_TXCSR);
499 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); 502 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
500 503
501 dma = is_dma_capable() ? musb_ep->dma : NULL; 504 dma = is_dma_capable() ? musb_ep->dma : NULL;
502 505
@@ -516,7 +519,8 @@ void musb_g_tx(struct musb *musb, u8 epnum)
516 csr |= MUSB_TXCSR_P_WZC_BITS; 519 csr |= MUSB_TXCSR_P_WZC_BITS;
517 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 520 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
518 musb_writew(epio, MUSB_TXCSR, csr); 521 musb_writew(epio, MUSB_TXCSR, csr);
519 DBG(20, "underrun on ep%d, req %p\n", epnum, request); 522 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
523 epnum, request);
520 } 524 }
521 525
522 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 526 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
@@ -524,7 +528,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
524 * SHOULD NOT HAPPEN... has with CPPI though, after 528 * SHOULD NOT HAPPEN... has with CPPI though, after
525 * changing SENDSTALL (and other cases); harmless? 529 * changing SENDSTALL (and other cases); harmless?
526 */ 530 */
527 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); 531 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
528 return; 532 return;
529 } 533 }
530 534
@@ -540,7 +544,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
540 /* Ensure writebuffer is empty. */ 544 /* Ensure writebuffer is empty. */
541 csr = musb_readw(epio, MUSB_TXCSR); 545 csr = musb_readw(epio, MUSB_TXCSR);
542 request->actual += musb_ep->dma->actual_len; 546 request->actual += musb_ep->dma->actual_len;
543 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n", 547 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
544 epnum, csr, musb_ep->dma->actual_len, request); 548 epnum, csr, musb_ep->dma->actual_len, request);
545 } 549 }
546 550
@@ -564,7 +568,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
564 if (csr & MUSB_TXCSR_TXPKTRDY) 568 if (csr & MUSB_TXCSR_TXPKTRDY)
565 return; 569 return;
566 570
567 DBG(4, "sending zero pkt\n"); 571 dev_dbg(musb->controller, "sending zero pkt\n");
568 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE 572 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
569 | MUSB_TXCSR_TXPKTRDY); 573 | MUSB_TXCSR_TXPKTRDY);
570 request->zero = 0; 574 request->zero = 0;
@@ -574,7 +578,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
574 musb_g_giveback(musb_ep, request, 0); 578 musb_g_giveback(musb_ep, request, 0);
575 req = musb_ep->desc ? next_request(musb_ep) : NULL; 579 req = musb_ep->desc ? next_request(musb_ep) : NULL;
576 if (!req) { 580 if (!req) {
577 DBG(4, "%s idle now\n", 581 dev_dbg(musb->controller, "%s idle now\n",
578 musb_ep->end_point.name); 582 musb_ep->end_point.name);
579 return; 583 return;
580 } 584 }
@@ -640,12 +644,12 @@ static void rxstate(struct musb *musb, struct musb_request *req)
640 644
641 /* We shouldn't get here while DMA is active, but we do... */ 645 /* We shouldn't get here while DMA is active, but we do... */
642 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 646 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
643 DBG(4, "DMA pending...\n"); 647 dev_dbg(musb->controller, "DMA pending...\n");
644 return; 648 return;
645 } 649 }
646 650
647 if (csr & MUSB_RXCSR_P_SENDSTALL) { 651 if (csr & MUSB_RXCSR_P_SENDSTALL) {
648 DBG(5, "%s stalling, RXCSR %04x\n", 652 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
649 musb_ep->end_point.name, csr); 653 musb_ep->end_point.name, csr);
650 return; 654 return;
651 } 655 }
@@ -757,7 +761,7 @@ static void rxstate(struct musb *musb, struct musb_request *req)
757#endif /* Mentor's DMA */ 761#endif /* Mentor's DMA */
758 762
759 fifo_count = request->length - request->actual; 763 fifo_count = request->length - request->actual;
760 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", 764 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
761 musb_ep->end_point.name, 765 musb_ep->end_point.name,
762 len, fifo_count, 766 len, fifo_count,
763 musb_ep->packet_sz); 767 musb_ep->packet_sz);
@@ -846,7 +850,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
846 csr = musb_readw(epio, MUSB_RXCSR); 850 csr = musb_readw(epio, MUSB_RXCSR);
847 dma = is_dma_capable() ? musb_ep->dma : NULL; 851 dma = is_dma_capable() ? musb_ep->dma : NULL;
848 852
849 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, 853 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
850 csr, dma ? " (dma)" : "", request); 854 csr, dma ? " (dma)" : "", request);
851 855
852 if (csr & MUSB_RXCSR_P_SENTSTALL) { 856 if (csr & MUSB_RXCSR_P_SENTSTALL) {
@@ -861,19 +865,18 @@ void musb_g_rx(struct musb *musb, u8 epnum)
861 csr &= ~MUSB_RXCSR_P_OVERRUN; 865 csr &= ~MUSB_RXCSR_P_OVERRUN;
862 musb_writew(epio, MUSB_RXCSR, csr); 866 musb_writew(epio, MUSB_RXCSR, csr);
863 867
864 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); 868 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
865 if (request->status == -EINPROGRESS) 869 if (request->status == -EINPROGRESS)
866 request->status = -EOVERFLOW; 870 request->status = -EOVERFLOW;
867 } 871 }
868 if (csr & MUSB_RXCSR_INCOMPRX) { 872 if (csr & MUSB_RXCSR_INCOMPRX) {
869 /* REVISIT not necessarily an error */ 873 /* REVISIT not necessarily an error */
870 DBG(4, "%s, incomprx\n", musb_ep->end_point.name); 874 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
871 } 875 }
872 876
873 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 877 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
874 /* "should not happen"; likely RXPKTRDY pending for DMA */ 878 /* "should not happen"; likely RXPKTRDY pending for DMA */
875 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, 879 dev_dbg(musb->controller, "%s busy, csr %04x\n",
876 "%s busy, csr %04x\n",
877 musb_ep->end_point.name, csr); 880 musb_ep->end_point.name, csr);
878 return; 881 return;
879 } 882 }
@@ -887,7 +890,7 @@ void musb_g_rx(struct musb *musb, u8 epnum)
887 890
888 request->actual += musb_ep->dma->actual_len; 891 request->actual += musb_ep->dma->actual_len;
889 892
890 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", 893 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
891 epnum, csr, 894 epnum, csr,
892 musb_readw(epio, MUSB_RXCSR), 895 musb_readw(epio, MUSB_RXCSR),
893 musb_ep->dma->actual_len, request); 896 musb_ep->dma->actual_len, request);
@@ -978,7 +981,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
978 ok = musb->hb_iso_rx; 981 ok = musb->hb_iso_rx;
979 982
980 if (!ok) { 983 if (!ok) {
981 DBG(4, "no support for high bandwidth ISO\n"); 984 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
982 goto fail; 985 goto fail;
983 } 986 }
984 musb_ep->hb_mult = (tmp >> 11) & 3; 987 musb_ep->hb_mult = (tmp >> 11) & 3;
@@ -1002,7 +1005,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
1002 goto fail; 1005 goto fail;
1003 1006
1004 if (tmp > hw_ep->max_packet_sz_tx) { 1007 if (tmp > hw_ep->max_packet_sz_tx) {
1005 DBG(4, "packet size beyond hardware FIFO size\n"); 1008 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1006 goto fail; 1009 goto fail;
1007 } 1010 }
1008 1011
@@ -1042,7 +1045,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
1042 goto fail; 1045 goto fail;
1043 1046
1044 if (tmp > hw_ep->max_packet_sz_rx) { 1047 if (tmp > hw_ep->max_packet_sz_rx) {
1045 DBG(4, "packet size beyond hardware FIFO size\n"); 1048 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1046 goto fail; 1049 goto fail;
1047 } 1050 }
1048 1051
@@ -1155,7 +1158,7 @@ static int musb_gadget_disable(struct usb_ep *ep)
1155 1158
1156 spin_unlock_irqrestore(&(musb->lock), flags); 1159 spin_unlock_irqrestore(&(musb->lock), flags);
1157 1160
1158 DBG(2, "%s\n", musb_ep->end_point.name); 1161 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1159 1162
1160 return status; 1163 return status;
1161} 1164}
@@ -1167,11 +1170,12 @@ static int musb_gadget_disable(struct usb_ep *ep)
1167struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 1170struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1168{ 1171{
1169 struct musb_ep *musb_ep = to_musb_ep(ep); 1172 struct musb_ep *musb_ep = to_musb_ep(ep);
1173 struct musb *musb = musb_ep->musb;
1170 struct musb_request *request = NULL; 1174 struct musb_request *request = NULL;
1171 1175
1172 request = kzalloc(sizeof *request, gfp_flags); 1176 request = kzalloc(sizeof *request, gfp_flags);
1173 if (!request) { 1177 if (!request) {
1174 DBG(4, "not enough memory\n"); 1178 dev_dbg(musb->controller, "not enough memory\n");
1175 return NULL; 1179 return NULL;
1176 } 1180 }
1177 1181
@@ -1205,7 +1209,7 @@ struct free_record {
1205 */ 1209 */
1206void musb_ep_restart(struct musb *musb, struct musb_request *req) 1210void musb_ep_restart(struct musb *musb, struct musb_request *req)
1207{ 1211{
1208 DBG(3, "<== %s request %p len %u on hw_ep%d\n", 1212 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1209 req->tx ? "TX/IN" : "RX/OUT", 1213 req->tx ? "TX/IN" : "RX/OUT",
1210 &req->request, req->request.length, req->epnum); 1214 &req->request, req->request.length, req->epnum);
1211 1215
@@ -1239,7 +1243,7 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1239 if (request->ep != musb_ep) 1243 if (request->ep != musb_ep)
1240 return -EINVAL; 1244 return -EINVAL;
1241 1245
1242 DBG(4, "<== to %s request=%p\n", ep->name, req); 1246 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1243 1247
1244 /* request is mine now... */ 1248 /* request is mine now... */
1245 request->request.actual = 0; 1249 request->request.actual = 0;
@@ -1253,7 +1257,7 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1253 1257
1254 /* don't queue if the ep is down */ 1258 /* don't queue if the ep is down */
1255 if (!musb_ep->desc) { 1259 if (!musb_ep->desc) {
1256 DBG(4, "req %p queued to %s while ep %s\n", 1260 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1257 req, ep->name, "disabled"); 1261 req, ep->name, "disabled");
1258 status = -ESHUTDOWN; 1262 status = -ESHUTDOWN;
1259 goto cleanup; 1263 goto cleanup;
@@ -1290,7 +1294,7 @@ static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1290 break; 1294 break;
1291 } 1295 }
1292 if (r != req) { 1296 if (r != req) {
1293 DBG(3, "request %p not queued to %s\n", request, ep->name); 1297 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1294 status = -EINVAL; 1298 status = -EINVAL;
1295 goto done; 1299 goto done;
1296 } 1300 }
@@ -1356,7 +1360,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1356 request = next_request(musb_ep); 1360 request = next_request(musb_ep);
1357 if (value) { 1361 if (value) {
1358 if (request) { 1362 if (request) {
1359 DBG(3, "request in progress, cannot halt %s\n", 1363 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1360 ep->name); 1364 ep->name);
1361 status = -EAGAIN; 1365 status = -EAGAIN;
1362 goto done; 1366 goto done;
@@ -1365,7 +1369,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1365 if (musb_ep->is_in) { 1369 if (musb_ep->is_in) {
1366 csr = musb_readw(epio, MUSB_TXCSR); 1370 csr = musb_readw(epio, MUSB_TXCSR);
1367 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1371 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1368 DBG(3, "FIFO busy, cannot halt %s\n", ep->name); 1372 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1369 status = -EAGAIN; 1373 status = -EAGAIN;
1370 goto done; 1374 goto done;
1371 } 1375 }
@@ -1374,7 +1378,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1374 musb_ep->wedged = 0; 1378 musb_ep->wedged = 0;
1375 1379
1376 /* set/clear the stall and toggle bits */ 1380 /* set/clear the stall and toggle bits */
1377 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); 1381 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1378 if (musb_ep->is_in) { 1382 if (musb_ep->is_in) {
1379 csr = musb_readw(epio, MUSB_TXCSR); 1383 csr = musb_readw(epio, MUSB_TXCSR);
1380 csr |= MUSB_TXCSR_P_WZC_BITS 1384 csr |= MUSB_TXCSR_P_WZC_BITS
@@ -1401,7 +1405,7 @@ static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1401 1405
1402 /* maybe start the first request in the queue */ 1406 /* maybe start the first request in the queue */
1403 if (!musb_ep->busy && !value && request) { 1407 if (!musb_ep->busy && !value && request) {
1404 DBG(3, "restarting the request\n"); 1408 dev_dbg(musb->controller, "restarting the request\n");
1405 musb_ep_restart(musb, request); 1409 musb_ep_restart(musb, request);
1406 } 1410 }
1407 1411
@@ -1532,7 +1536,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1532 case OTG_STATE_B_IDLE: 1536 case OTG_STATE_B_IDLE:
1533 /* Start SRP ... OTG not required. */ 1537 /* Start SRP ... OTG not required. */
1534 devctl = musb_readb(mregs, MUSB_DEVCTL); 1538 devctl = musb_readb(mregs, MUSB_DEVCTL);
1535 DBG(2, "Sending SRP: devctl: %02x\n", devctl); 1539 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1536 devctl |= MUSB_DEVCTL_SESSION; 1540 devctl |= MUSB_DEVCTL_SESSION;
1537 musb_writeb(mregs, MUSB_DEVCTL, devctl); 1541 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1538 devctl = musb_readb(mregs, MUSB_DEVCTL); 1542 devctl = musb_readb(mregs, MUSB_DEVCTL);
@@ -1556,7 +1560,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1556 status = 0; 1560 status = 0;
1557 goto done; 1561 goto done;
1558 default: 1562 default:
1559 DBG(2, "Unhandled wake: %s\n", 1563 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1560 otg_state_string(musb->xceiv->state)); 1564 otg_state_string(musb->xceiv->state));
1561 goto done; 1565 goto done;
1562 } 1566 }
@@ -1566,7 +1570,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
1566 power = musb_readb(mregs, MUSB_POWER); 1570 power = musb_readb(mregs, MUSB_POWER);
1567 power |= MUSB_POWER_RESUME; 1571 power |= MUSB_POWER_RESUME;
1568 musb_writeb(mregs, MUSB_POWER, power); 1572 musb_writeb(mregs, MUSB_POWER, power);
1569 DBG(2, "issue wakeup\n"); 1573 dev_dbg(musb->controller, "issue wakeup\n");
1570 1574
1571 /* FIXME do this next chunk in a timer callback, no udelay */ 1575 /* FIXME do this next chunk in a timer callback, no udelay */
1572 mdelay(2); 1576 mdelay(2);
@@ -1600,7 +1604,7 @@ static void musb_pullup(struct musb *musb, int is_on)
1600 1604
1601 /* FIXME if on, HdrcStart; if off, HdrcStop */ 1605 /* FIXME if on, HdrcStart; if off, HdrcStop */
1602 1606
1603 DBG(3, "gadget %s D+ pullup %s\n", 1607 dev_dbg(musb->controller, "gadget %s D+ pullup %s\n",
1604 musb->gadget_driver->function, is_on ? "on" : "off"); 1608 musb->gadget_driver->function, is_on ? "on" : "off");
1605 musb_writeb(musb->mregs, MUSB_POWER, power); 1609 musb_writeb(musb->mregs, MUSB_POWER, power);
1606} 1610}
@@ -1608,7 +1612,7 @@ static void musb_pullup(struct musb *musb, int is_on)
1608#if 0 1612#if 0
1609static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) 1613static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1610{ 1614{
1611 DBG(2, "<= %s =>\n", __func__); 1615 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1612 1616
1613 /* 1617 /*
1614 * FIXME iff driver's softconnect flag is set (as it is during probe, 1618 * FIXME iff driver's softconnect flag is set (as it is during probe,
@@ -1817,17 +1821,17 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1817 1821
1818 /* driver must be initialized to support peripheral mode */ 1822 /* driver must be initialized to support peripheral mode */
1819 if (!musb) { 1823 if (!musb) {
1820 DBG(1, "no dev??\n"); 1824 dev_dbg(musb->controller, "no dev??\n");
1821 retval = -ENODEV; 1825 retval = -ENODEV;
1822 goto err0; 1826 goto err0;
1823 } 1827 }
1824 1828
1825 pm_runtime_get_sync(musb->controller); 1829 pm_runtime_get_sync(musb->controller);
1826 1830
1827 DBG(3, "registering driver %s\n", driver->function); 1831 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1828 1832
1829 if (musb->gadget_driver) { 1833 if (musb->gadget_driver) {
1830 DBG(1, "%s is already bound to %s\n", 1834 dev_dbg(musb->controller, "%s is already bound to %s\n",
1831 musb_driver_name, 1835 musb_driver_name,
1832 musb->gadget_driver->driver.name); 1836 musb->gadget_driver->driver.name);
1833 retval = -EBUSY; 1837 retval = -EBUSY;
@@ -1843,7 +1847,7 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1843 1847
1844 retval = bind(&musb->g); 1848 retval = bind(&musb->g);
1845 if (retval) { 1849 if (retval) {
1846 DBG(3, "bind to driver %s failed --> %d\n", 1850 dev_dbg(musb->controller, "bind to driver %s failed --> %d\n",
1847 driver->driver.name, retval); 1851 driver->driver.name, retval);
1848 goto err1; 1852 goto err1;
1849 } 1853 }
@@ -1871,7 +1875,7 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1871 if (is_otg_enabled(musb)) { 1875 if (is_otg_enabled(musb)) {
1872 struct usb_hcd *hcd = musb_to_hcd(musb); 1876 struct usb_hcd *hcd = musb_to_hcd(musb);
1873 1877
1874 DBG(3, "OTG startup...\n"); 1878 dev_dbg(musb->controller, "OTG startup...\n");
1875 1879
1876 /* REVISIT: funcall to other code, which also 1880 /* REVISIT: funcall to other code, which also
1877 * handles power budgeting ... this way also 1881 * handles power budgeting ... this way also
@@ -1879,7 +1883,7 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1879 */ 1883 */
1880 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); 1884 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1881 if (retval < 0) { 1885 if (retval < 0) {
1882 DBG(1, "add_hcd failed, %d\n", retval); 1886 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1883 goto err2; 1887 goto err2;
1884 } 1888 }
1885 1889
@@ -1986,7 +1990,7 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1986 stop_activity(musb, driver); 1990 stop_activity(musb, driver);
1987 otg_set_peripheral(musb->xceiv, NULL); 1991 otg_set_peripheral(musb->xceiv, NULL);
1988 1992
1989 DBG(3, "unregistering driver %s\n", driver->function); 1993 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
1990 1994
1991 spin_unlock_irqrestore(&musb->lock, flags); 1995 spin_unlock_irqrestore(&musb->lock, flags);
1992 driver->unbind(&musb->g); 1996 driver->unbind(&musb->g);
@@ -2048,7 +2052,7 @@ void musb_g_suspend(struct musb *musb)
2048 u8 devctl; 2052 u8 devctl;
2049 2053
2050 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2054 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2051 DBG(3, "devctl %02x\n", devctl); 2055 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2052 2056
2053 switch (musb->xceiv->state) { 2057 switch (musb->xceiv->state) {
2054 case OTG_STATE_B_IDLE: 2058 case OTG_STATE_B_IDLE:
@@ -2084,7 +2088,7 @@ void musb_g_disconnect(struct musb *musb)
2084 void __iomem *mregs = musb->mregs; 2088 void __iomem *mregs = musb->mregs;
2085 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 2089 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2086 2090
2087 DBG(3, "devctl %02x\n", devctl); 2091 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2088 2092
2089 /* clear HR */ 2093 /* clear HR */
2090 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); 2094 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
@@ -2102,7 +2106,7 @@ void musb_g_disconnect(struct musb *musb)
2102 switch (musb->xceiv->state) { 2106 switch (musb->xceiv->state) {
2103 default: 2107 default:
2104#ifdef CONFIG_USB_MUSB_OTG 2108#ifdef CONFIG_USB_MUSB_OTG
2105 DBG(2, "Unhandled disconnect %s, setting a_idle\n", 2109 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2106 otg_state_string(musb->xceiv->state)); 2110 otg_state_string(musb->xceiv->state));
2107 musb->xceiv->state = OTG_STATE_A_IDLE; 2111 musb->xceiv->state = OTG_STATE_A_IDLE;
2108 MUSB_HST_MODE(musb); 2112 MUSB_HST_MODE(musb);
@@ -2133,7 +2137,7 @@ __acquires(musb->lock)
2133 u8 devctl = musb_readb(mbase, MUSB_DEVCTL); 2137 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2134 u8 power; 2138 u8 power;
2135 2139
2136 DBG(3, "<== %s addr=%x driver '%s'\n", 2140 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2137 (devctl & MUSB_DEVCTL_BDEVICE) 2141 (devctl & MUSB_DEVCTL_BDEVICE)
2138 ? "B-Device" : "A-Device", 2142 ? "B-Device" : "A-Device",
2139 musb_readb(mbase, MUSB_FADDR), 2143 musb_readb(mbase, MUSB_FADDR),
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 75a542e42fdf..b2faff235507 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -209,7 +209,7 @@ static inline void musb_try_b_hnp_enable(struct musb *musb)
209 void __iomem *mbase = musb->mregs; 209 void __iomem *mbase = musb->mregs;
210 u8 devctl; 210 u8 devctl;
211 211
212 DBG(1, "HNP: Setting HR\n"); 212 dev_dbg(musb->controller, "HNP: Setting HR\n");
213 devctl = musb_readb(mbase, MUSB_DEVCTL); 213 devctl = musb_readb(mbase, MUSB_DEVCTL);
214 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR); 214 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
215} 215}
@@ -306,7 +306,7 @@ __acquires(musb->lock)
306 /* Maybe start the first request in the queue */ 306 /* Maybe start the first request in the queue */
307 request = next_request(musb_ep); 307 request = next_request(musb_ep);
308 if (!musb_ep->busy && request) { 308 if (!musb_ep->busy && request) {
309 DBG(3, "restarting the request\n"); 309 dev_dbg(musb->controller, "restarting the request\n");
310 musb_ep_restart(musb, request); 310 musb_ep_restart(musb, request);
311 } 311 }
312 312
@@ -553,7 +553,7 @@ static void ep0_txstate(struct musb *musb)
553 553
554 if (!req) { 554 if (!req) {
555 /* WARN_ON(1); */ 555 /* WARN_ON(1); */
556 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0)); 556 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
557 return; 557 return;
558 } 558 }
559 559
@@ -610,7 +610,7 @@ musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
610 /* NOTE: earlier 2.6 versions changed setup packets to host 610 /* NOTE: earlier 2.6 versions changed setup packets to host
611 * order, but now USB packets always stay in USB byte order. 611 * order, but now USB packets always stay in USB byte order.
612 */ 612 */
613 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n", 613 dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
614 req->bRequestType, 614 req->bRequestType,
615 req->bRequest, 615 req->bRequest,
616 le16_to_cpu(req->wValue), 616 le16_to_cpu(req->wValue),
@@ -678,7 +678,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
678 csr = musb_readw(regs, MUSB_CSR0); 678 csr = musb_readw(regs, MUSB_CSR0);
679 len = musb_readb(regs, MUSB_COUNT0); 679 len = musb_readb(regs, MUSB_COUNT0);
680 680
681 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n", 681 dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
682 csr, len, 682 csr, len,
683 musb_readb(mbase, MUSB_FADDR), 683 musb_readb(mbase, MUSB_FADDR),
684 decode_ep0stage(musb->ep0_state)); 684 decode_ep0stage(musb->ep0_state));
@@ -749,7 +749,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
749 749
750 /* enter test mode if needed (exit by reset) */ 750 /* enter test mode if needed (exit by reset) */
751 else if (musb->test_mode) { 751 else if (musb->test_mode) {
752 DBG(1, "entering TESTMODE\n"); 752 dev_dbg(musb->controller, "entering TESTMODE\n");
753 753
754 if (MUSB_TEST_PACKET == musb->test_mode_nr) 754 if (MUSB_TEST_PACKET == musb->test_mode_nr)
755 musb_load_testpacket(musb); 755 musb_load_testpacket(musb);
@@ -861,7 +861,7 @@ setup:
861 break; 861 break;
862 } 862 }
863 863
864 DBG(3, "handled %d, csr %04x, ep0stage %s\n", 864 dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
865 handled, csr, 865 handled, csr,
866 decode_ep0stage(musb->ep0_state)); 866 decode_ep0stage(musb->ep0_state));
867 867
@@ -878,7 +878,7 @@ setup:
878 if (handled < 0) { 878 if (handled < 0) {
879 musb_ep_select(mbase, 0); 879 musb_ep_select(mbase, 0);
880stall: 880stall:
881 DBG(3, "stall (%d)\n", handled); 881 dev_dbg(musb->controller, "stall (%d)\n", handled);
882 musb->ackpend |= MUSB_CSR0_P_SENDSTALL; 882 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
883 musb->ep0_state = MUSB_EP0_STAGE_IDLE; 883 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
884finish: 884finish:
@@ -958,7 +958,7 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
958 status = 0; 958 status = 0;
959 break; 959 break;
960 default: 960 default:
961 DBG(1, "ep0 request queued in state %d\n", 961 dev_dbg(musb->controller, "ep0 request queued in state %d\n",
962 musb->ep0_state); 962 musb->ep0_state);
963 status = -EINVAL; 963 status = -EINVAL;
964 goto cleanup; 964 goto cleanup;
@@ -967,7 +967,7 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
967 /* add request to the list */ 967 /* add request to the list */
968 list_add_tail(&req->list, &ep->req_list); 968 list_add_tail(&req->list, &ep->req_list);
969 969
970 DBG(3, "queue to %s (%s), length=%d\n", 970 dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
971 ep->name, ep->is_in ? "IN/TX" : "OUT/RX", 971 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
972 req->request.length); 972 req->request.length);
973 973
@@ -1060,7 +1060,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
1060 musb->ackpend = 0; 1060 musb->ackpend = 0;
1061 break; 1061 break;
1062 default: 1062 default:
1063 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state); 1063 dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
1064 status = -EINVAL; 1064 status = -EINVAL;
1065 } 1065 }
1066 1066
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 07b106c7de82..75aa01e0036d 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -106,6 +106,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
106 */ 106 */
107static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 107static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
108{ 108{
109 struct musb *musb = ep->musb;
109 void __iomem *epio = ep->regs; 110 void __iomem *epio = ep->regs;
110 u16 csr; 111 u16 csr;
111 u16 lastcsr = 0; 112 u16 lastcsr = 0;
@@ -114,7 +115,7 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
114 csr = musb_readw(epio, MUSB_TXCSR); 115 csr = musb_readw(epio, MUSB_TXCSR);
115 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 116 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
116 if (csr != lastcsr) 117 if (csr != lastcsr)
117 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 118 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
118 lastcsr = csr; 119 lastcsr = csr;
119 csr |= MUSB_TXCSR_FLUSHFIFO; 120 csr |= MUSB_TXCSR_FLUSHFIFO;
120 musb_writew(epio, MUSB_TXCSR, csr); 121 musb_writew(epio, MUSB_TXCSR, csr);
@@ -240,7 +241,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
240 len = urb->transfer_buffer_length - urb->actual_length; 241 len = urb->transfer_buffer_length - urb->actual_length;
241 } 242 }
242 243
243 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 244 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
244 qh, urb, address, qh->epnum, 245 qh, urb, address, qh->epnum,
245 is_in ? "in" : "out", 246 is_in ? "in" : "out",
246 ({char *s; switch (qh->type) { 247 ({char *s; switch (qh->type) {
@@ -263,7 +264,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
263 switch (qh->type) { 264 switch (qh->type) {
264 case USB_ENDPOINT_XFER_ISOC: 265 case USB_ENDPOINT_XFER_ISOC:
265 case USB_ENDPOINT_XFER_INT: 266 case USB_ENDPOINT_XFER_INT:
266 DBG(3, "check whether there's still time for periodic Tx\n"); 267 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
267 frame = musb_readw(mbase, MUSB_FRAME); 268 frame = musb_readw(mbase, MUSB_FRAME);
268 /* FIXME this doesn't implement that scheduling policy ... 269 /* FIXME this doesn't implement that scheduling policy ...
269 * or handle framecounter wrapping 270 * or handle framecounter wrapping
@@ -278,7 +279,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
278 } else { 279 } else {
279 qh->frame = urb->start_frame; 280 qh->frame = urb->start_frame;
280 /* enable SOF interrupt so we can count down */ 281 /* enable SOF interrupt so we can count down */
281 DBG(1, "SOF for %d\n", epnum); 282 dev_dbg(musb->controller, "SOF for %d\n", epnum);
282#if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 283#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
283 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 284 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
284#endif 285#endif
@@ -286,7 +287,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
286 break; 287 break;
287 default: 288 default:
288start: 289start:
289 DBG(4, "Start TX%d %s\n", epnum, 290 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
290 hw_ep->tx_channel ? "dma" : "pio"); 291 hw_ep->tx_channel ? "dma" : "pio");
291 292
292 if (!hw_ep->tx_channel) 293 if (!hw_ep->tx_channel)
@@ -301,21 +302,7 @@ static void musb_giveback(struct musb *musb, struct urb *urb, int status)
301__releases(musb->lock) 302__releases(musb->lock)
302__acquires(musb->lock) 303__acquires(musb->lock)
303{ 304{
304 DBG(({ int level; switch (status) { 305 dev_dbg(musb->controller,
305 case 0:
306 level = 4;
307 break;
308 /* common/boring faults */
309 case -EREMOTEIO:
310 case -ESHUTDOWN:
311 case -ECONNRESET:
312 case -EPIPE:
313 level = 3;
314 break;
315 default:
316 level = 2;
317 break;
318 }; level; }),
319 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 306 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
320 urb, urb->complete, status, 307 urb, urb->complete, status,
321 usb_pipedevice(urb->pipe), 308 usb_pipedevice(urb->pipe),
@@ -426,7 +413,7 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
426 } 413 }
427 414
428 if (qh != NULL && qh->is_ready) { 415 if (qh != NULL && qh->is_ready) {
429 DBG(4, "... next ep%d %cX urb %p\n", 416 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
430 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 417 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
431 musb_start_urb(musb, is_in, qh); 418 musb_start_urb(musb, is_in, qh);
432 } 419 }
@@ -471,7 +458,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
471 458
472 /* musb_ep_select(mbase, epnum); */ 459 /* musb_ep_select(mbase, epnum); */
473 rx_count = musb_readw(epio, MUSB_RXCOUNT); 460 rx_count = musb_readw(epio, MUSB_RXCOUNT);
474 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 461 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
475 urb->transfer_buffer, qh->offset, 462 urb->transfer_buffer, qh->offset,
476 urb->transfer_buffer_length); 463 urb->transfer_buffer_length);
477 464
@@ -493,7 +480,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
493 status = -EOVERFLOW; 480 status = -EOVERFLOW;
494 urb->error_count++; 481 urb->error_count++;
495 } 482 }
496 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 483 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
497 do_flush = 1; 484 do_flush = 1;
498 } else 485 } else
499 length = rx_count; 486 length = rx_count;
@@ -511,7 +498,7 @@ musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
511 if (rx_count > length) { 498 if (rx_count > length) {
512 if (urb->status == -EINPROGRESS) 499 if (urb->status == -EINPROGRESS)
513 urb->status = -EOVERFLOW; 500 urb->status = -EOVERFLOW;
514 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 501 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
515 do_flush = 1; 502 do_flush = 1;
516 } else 503 } else
517 length = rx_count; 504 length = rx_count;
@@ -697,7 +684,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
697 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 684 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
698 u16 packet_sz = qh->maxpacket; 685 u16 packet_sz = qh->maxpacket;
699 686
700 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " 687 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
701 "h_addr%02x h_port%02x bytes %d\n", 688 "h_addr%02x h_port%02x bytes %d\n",
702 is_out ? "-->" : "<--", 689 is_out ? "-->" : "<--",
703 epnum, urb, urb->dev->speed, 690 epnum, urb, urb->dev->speed,
@@ -880,7 +867,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
880 } 867 }
881 868
882 csr |= MUSB_RXCSR_H_REQPKT; 869 csr |= MUSB_RXCSR_H_REQPKT;
883 DBG(7, "RXCSR%d := %04x\n", epnum, csr); 870 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
884 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 871 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
885 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 872 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
886 } 873 }
@@ -923,15 +910,15 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
923 request = (struct usb_ctrlrequest *) urb->setup_packet; 910 request = (struct usb_ctrlrequest *) urb->setup_packet;
924 911
925 if (!request->wLength) { 912 if (!request->wLength) {
926 DBG(4, "start no-DATA\n"); 913 dev_dbg(musb->controller, "start no-DATA\n");
927 break; 914 break;
928 } else if (request->bRequestType & USB_DIR_IN) { 915 } else if (request->bRequestType & USB_DIR_IN) {
929 DBG(4, "start IN-DATA\n"); 916 dev_dbg(musb->controller, "start IN-DATA\n");
930 musb->ep0_stage = MUSB_EP0_IN; 917 musb->ep0_stage = MUSB_EP0_IN;
931 more = true; 918 more = true;
932 break; 919 break;
933 } else { 920 } else {
934 DBG(4, "start OUT-DATA\n"); 921 dev_dbg(musb->controller, "start OUT-DATA\n");
935 musb->ep0_stage = MUSB_EP0_OUT; 922 musb->ep0_stage = MUSB_EP0_OUT;
936 more = true; 923 more = true;
937 } 924 }
@@ -943,7 +930,7 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
943 if (fifo_count) { 930 if (fifo_count) {
944 fifo_dest = (u8 *) (urb->transfer_buffer 931 fifo_dest = (u8 *) (urb->transfer_buffer
945 + urb->actual_length); 932 + urb->actual_length);
946 DBG(3, "Sending %d byte%s to ep0 fifo %p\n", 933 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
947 fifo_count, 934 fifo_count,
948 (fifo_count == 1) ? "" : "s", 935 (fifo_count == 1) ? "" : "s",
949 fifo_dest); 936 fifo_dest);
@@ -988,7 +975,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
988 ? musb_readb(epio, MUSB_COUNT0) 975 ? musb_readb(epio, MUSB_COUNT0)
989 : 0; 976 : 0;
990 977
991 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 978 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
992 csr, qh, len, urb, musb->ep0_stage); 979 csr, qh, len, urb, musb->ep0_stage);
993 980
994 /* if we just did status stage, we are done */ 981 /* if we just did status stage, we are done */
@@ -999,15 +986,15 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
999 986
1000 /* prepare status */ 987 /* prepare status */
1001 if (csr & MUSB_CSR0_H_RXSTALL) { 988 if (csr & MUSB_CSR0_H_RXSTALL) {
1002 DBG(6, "STALLING ENDPOINT\n"); 989 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1003 status = -EPIPE; 990 status = -EPIPE;
1004 991
1005 } else if (csr & MUSB_CSR0_H_ERROR) { 992 } else if (csr & MUSB_CSR0_H_ERROR) {
1006 DBG(2, "no response, csr0 %04x\n", csr); 993 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1007 status = -EPROTO; 994 status = -EPROTO;
1008 995
1009 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 996 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1010 DBG(2, "control NAK timeout\n"); 997 dev_dbg(musb->controller, "control NAK timeout\n");
1011 998
1012 /* NOTE: this code path would be a good place to PAUSE a 999 /* NOTE: this code path would be a good place to PAUSE a
1013 * control transfer, if another one is queued, so that 1000 * control transfer, if another one is queued, so that
@@ -1022,7 +1009,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
1022 } 1009 }
1023 1010
1024 if (status) { 1011 if (status) {
1025 DBG(6, "aborting\n"); 1012 dev_dbg(musb->controller, "aborting\n");
1026 retval = IRQ_HANDLED; 1013 retval = IRQ_HANDLED;
1027 if (urb) 1014 if (urb)
1028 urb->status = status; 1015 urb->status = status;
@@ -1072,7 +1059,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
1072 /* flag status stage */ 1059 /* flag status stage */
1073 musb->ep0_stage = MUSB_EP0_STATUS; 1060 musb->ep0_stage = MUSB_EP0_STATUS;
1074 1061
1075 DBG(5, "ep0 STATUS, csr %04x\n", csr); 1062 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1076 1063
1077 } 1064 }
1078 musb_writew(epio, MUSB_CSR0, csr); 1065 musb_writew(epio, MUSB_CSR0, csr);
@@ -1126,31 +1113,31 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1126 1113
1127 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1114 /* with CPPI, DMA sometimes triggers "extra" irqs */
1128 if (!urb) { 1115 if (!urb) {
1129 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1116 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1130 return; 1117 return;
1131 } 1118 }
1132 1119
1133 pipe = urb->pipe; 1120 pipe = urb->pipe;
1134 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1121 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1135 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1122 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1136 dma ? ", dma" : ""); 1123 dma ? ", dma" : "");
1137 1124
1138 /* check for errors */ 1125 /* check for errors */
1139 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1126 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1140 /* dma was disabled, fifo flushed */ 1127 /* dma was disabled, fifo flushed */
1141 DBG(3, "TX end %d stall\n", epnum); 1128 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1142 1129
1143 /* stall; record URB status */ 1130 /* stall; record URB status */
1144 status = -EPIPE; 1131 status = -EPIPE;
1145 1132
1146 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1133 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1147 /* (NON-ISO) dma was disabled, fifo flushed */ 1134 /* (NON-ISO) dma was disabled, fifo flushed */
1148 DBG(3, "TX 3strikes on ep=%d\n", epnum); 1135 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1149 1136
1150 status = -ETIMEDOUT; 1137 status = -ETIMEDOUT;
1151 1138
1152 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1139 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1153 DBG(6, "TX end=%d device not responding\n", epnum); 1140 dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
1154 1141
1155 /* NOTE: this code path would be a good place to PAUSE a 1142 /* NOTE: this code path would be a good place to PAUSE a
1156 * transfer, if there's some other (nonperiodic) tx urb 1143 * transfer, if there's some other (nonperiodic) tx urb
@@ -1195,7 +1182,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1195 1182
1196 /* second cppi case */ 1183 /* second cppi case */
1197 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1184 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1198 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1185 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1199 return; 1186 return;
1200 } 1187 }
1201 1188
@@ -1254,7 +1241,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1254 * FIFO mode too... 1241 * FIFO mode too...
1255 */ 1242 */
1256 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1243 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1257 DBG(2, "DMA complete but packet still in FIFO, " 1244 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1258 "CSR %04x\n", tx_csr); 1245 "CSR %04x\n", tx_csr);
1259 return; 1246 return;
1260 } 1247 }
@@ -1321,7 +1308,7 @@ void musb_host_tx(struct musb *musb, u8 epnum)
1321 return; 1308 return;
1322 } 1309 }
1323 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1310 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1324 DBG(1, "not complete, but DMA enabled?\n"); 1311 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1325 return; 1312 return;
1326 } 1313 }
1327 1314
@@ -1462,7 +1449,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1462 * usbtest #11 (unlinks) triggers it regularly, sometimes 1449 * usbtest #11 (unlinks) triggers it regularly, sometimes
1463 * with fifo full. (Only with DMA??) 1450 * with fifo full. (Only with DMA??)
1464 */ 1451 */
1465 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1452 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1466 musb_readw(epio, MUSB_RXCOUNT)); 1453 musb_readw(epio, MUSB_RXCOUNT));
1467 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1454 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1468 return; 1455 return;
@@ -1470,20 +1457,20 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1470 1457
1471 pipe = urb->pipe; 1458 pipe = urb->pipe;
1472 1459
1473 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1460 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1474 epnum, rx_csr, urb->actual_length, 1461 epnum, rx_csr, urb->actual_length,
1475 dma ? dma->actual_len : 0); 1462 dma ? dma->actual_len : 0);
1476 1463
1477 /* check for errors, concurrent stall & unlink is not really 1464 /* check for errors, concurrent stall & unlink is not really
1478 * handled yet! */ 1465 * handled yet! */
1479 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1466 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1480 DBG(3, "RX end %d STALL\n", epnum); 1467 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1481 1468
1482 /* stall; record URB status */ 1469 /* stall; record URB status */
1483 status = -EPIPE; 1470 status = -EPIPE;
1484 1471
1485 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1472 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1486 DBG(3, "end %d RX proto error\n", epnum); 1473 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1487 1474
1488 status = -EPROTO; 1475 status = -EPROTO;
1489 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1476 musb_writeb(epio, MUSB_RXINTERVAL, 0);
@@ -1491,7 +1478,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1491 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1478 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1492 1479
1493 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1480 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1494 DBG(6, "RX end %d NAK timeout\n", epnum); 1481 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1495 1482
1496 /* NOTE: NAKing is *NOT* an error, so we want to 1483 /* NOTE: NAKing is *NOT* an error, so we want to
1497 * continue. Except ... if there's a request for 1484 * continue. Except ... if there's a request for
@@ -1514,12 +1501,12 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1514 1501
1515 goto finish; 1502 goto finish;
1516 } else { 1503 } else {
1517 DBG(4, "RX end %d ISO data error\n", epnum); 1504 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1518 /* packet error reported later */ 1505 /* packet error reported later */
1519 iso_err = true; 1506 iso_err = true;
1520 } 1507 }
1521 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1508 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1522 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n", 1509 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1523 epnum); 1510 epnum);
1524 status = -EPROTO; 1511 status = -EPROTO;
1525 } 1512 }
@@ -1565,7 +1552,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1565 done = true; 1552 done = true;
1566 } 1553 }
1567 1554
1568 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1555 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1569 xfer_len, dma ? ", dma" : ""); 1556 xfer_len, dma ? ", dma" : "");
1570 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1557 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1571 1558
@@ -1615,7 +1602,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1615 MUSB_RXCSR_H_WZC_BITS | val); 1602 MUSB_RXCSR_H_WZC_BITS | val);
1616 } 1603 }
1617 1604
1618 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1605 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1619 done ? "off" : "reset", 1606 done ? "off" : "reset",
1620 musb_readw(epio, MUSB_RXCSR), 1607 musb_readw(epio, MUSB_RXCSR),
1621 musb_readw(epio, MUSB_RXCOUNT)); 1608 musb_readw(epio, MUSB_RXCOUNT));
@@ -1648,7 +1635,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1648 1635
1649 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1636 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1650 1637
1651 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n", 1638 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
1652 epnum, rx_count, 1639 epnum, rx_count,
1653 urb->transfer_dma 1640 urb->transfer_dma
1654 + urb->actual_length, 1641 + urb->actual_length,
@@ -1672,7 +1659,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1672 d_status = -EOVERFLOW; 1659 d_status = -EOVERFLOW;
1673 urb->error_count++; 1660 urb->error_count++;
1674 } 1661 }
1675 DBG(2, "** OVERFLOW %d into %d\n",\ 1662 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1676 rx_count, d->length); 1663 rx_count, d->length);
1677 1664
1678 length = d->length; 1665 length = d->length;
@@ -1760,7 +1747,7 @@ void musb_host_rx(struct musb *musb, u8 epnum)
1760 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); 1747 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1761 done = musb_host_packet_rx(musb, urb, 1748 done = musb_host_packet_rx(musb, urb,
1762 epnum, iso_err); 1749 epnum, iso_err);
1763 DBG(6, "read %spacket\n", done ? "last " : ""); 1750 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1764 } 1751 }
1765 } 1752 }
1766 1753
@@ -1881,7 +1868,7 @@ static int musb_schedule(
1881 idle = 1; 1868 idle = 1;
1882 qh->mux = 0; 1869 qh->mux = 0;
1883 hw_ep = musb->endpoints + best_end; 1870 hw_ep = musb->endpoints + best_end;
1884 DBG(4, "qh %p periodic slot %d\n", qh, best_end); 1871 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
1885success: 1872success:
1886 if (head) { 1873 if (head) {
1887 idle = list_empty(head); 1874 idle = list_empty(head);
@@ -2087,6 +2074,7 @@ done:
2087static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2074static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2088{ 2075{
2089 struct musb_hw_ep *ep = qh->hw_ep; 2076 struct musb_hw_ep *ep = qh->hw_ep;
2077 struct musb *musb = ep->musb;
2090 void __iomem *epio = ep->regs; 2078 void __iomem *epio = ep->regs;
2091 unsigned hw_end = ep->epnum; 2079 unsigned hw_end = ep->epnum;
2092 void __iomem *regs = ep->musb->mregs; 2080 void __iomem *regs = ep->musb->mregs;
@@ -2102,7 +2090,7 @@ static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2102 dma = is_in ? ep->rx_channel : ep->tx_channel; 2090 dma = is_in ? ep->rx_channel : ep->tx_channel;
2103 if (dma) { 2091 if (dma) {
2104 status = ep->musb->dma_controller->channel_abort(dma); 2092 status = ep->musb->dma_controller->channel_abort(dma);
2105 DBG(status ? 1 : 3, 2093 dev_dbg(musb->controller,
2106 "abort %cX%d DMA for urb %p --> %d\n", 2094 "abort %cX%d DMA for urb %p --> %d\n",
2107 is_in ? 'R' : 'T', ep->epnum, 2095 is_in ? 'R' : 'T', ep->epnum,
2108 urb, status); 2096 urb, status);
@@ -2149,7 +2137,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2149 int is_in = usb_pipein(urb->pipe); 2137 int is_in = usb_pipein(urb->pipe);
2150 int ret; 2138 int ret;
2151 2139
2152 DBG(4, "urb=%p, dev%d ep%d%s\n", urb, 2140 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2153 usb_pipedevice(urb->pipe), 2141 usb_pipedevice(urb->pipe),
2154 usb_pipeendpoint(urb->pipe), 2142 usb_pipeendpoint(urb->pipe),
2155 is_in ? "in" : "out"); 2143 is_in ? "in" : "out");
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index bb1247d5fd04..2d80a5758838 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -74,7 +74,7 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
74 break; 74 break;
75 } 75 }
76 76
77 DBG(3, "Root port suspended, power %02x\n", power); 77 dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
78 78
79 musb->port1_status |= USB_PORT_STAT_SUSPEND; 79 musb->port1_status |= USB_PORT_STAT_SUSPEND;
80 switch (musb->xceiv->state) { 80 switch (musb->xceiv->state) {
@@ -97,7 +97,7 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
97 break; 97 break;
98#endif 98#endif
99 default: 99 default:
100 DBG(1, "bogus rh suspend? %s\n", 100 dev_dbg(musb->controller, "bogus rh suspend? %s\n",
101 otg_state_string(musb->xceiv->state)); 101 otg_state_string(musb->xceiv->state));
102 } 102 }
103 } else if (power & MUSB_POWER_SUSPENDM) { 103 } else if (power & MUSB_POWER_SUSPENDM) {
@@ -105,7 +105,7 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
105 power |= MUSB_POWER_RESUME; 105 power |= MUSB_POWER_RESUME;
106 musb_writeb(mbase, MUSB_POWER, power); 106 musb_writeb(mbase, MUSB_POWER, power);
107 107
108 DBG(3, "Root port resuming, power %02x\n", power); 108 dev_dbg(musb->controller, "Root port resuming, power %02x\n", power);
109 109
110 /* later, GetPortStatus will stop RESUME signaling */ 110 /* later, GetPortStatus will stop RESUME signaling */
111 musb->port1_status |= MUSB_PORT_STAT_RESUME; 111 musb->port1_status |= MUSB_PORT_STAT_RESUME;
@@ -120,7 +120,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
120 120
121#ifdef CONFIG_USB_MUSB_OTG 121#ifdef CONFIG_USB_MUSB_OTG
122 if (musb->xceiv->state == OTG_STATE_B_IDLE) { 122 if (musb->xceiv->state == OTG_STATE_B_IDLE) {
123 DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n"); 123 dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
124 musb->port1_status &= ~USB_PORT_STAT_RESET; 124 musb->port1_status &= ~USB_PORT_STAT_RESET;
125 return; 125 return;
126 } 126 }
@@ -159,7 +159,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
159 musb->port1_status &= ~USB_PORT_STAT_ENABLE; 159 musb->port1_status &= ~USB_PORT_STAT_ENABLE;
160 musb->rh_timer = jiffies + msecs_to_jiffies(50); 160 musb->rh_timer = jiffies + msecs_to_jiffies(50);
161 } else { 161 } else {
162 DBG(4, "root port reset stopped\n"); 162 dev_dbg(musb->controller, "root port reset stopped\n");
163 musb_writeb(mbase, MUSB_POWER, 163 musb_writeb(mbase, MUSB_POWER,
164 power & ~MUSB_POWER_RESET); 164 power & ~MUSB_POWER_RESET);
165 165
@@ -167,7 +167,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
167 167
168 power = musb_readb(mbase, MUSB_POWER); 168 power = musb_readb(mbase, MUSB_POWER);
169 if (power & MUSB_POWER_HSMODE) { 169 if (power & MUSB_POWER_HSMODE) {
170 DBG(4, "high-speed device connected\n"); 170 dev_dbg(musb->controller, "high-speed device connected\n");
171 musb->port1_status |= USB_PORT_STAT_HIGH_SPEED; 171 musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
172 } 172 }
173 173
@@ -208,7 +208,7 @@ void musb_root_disconnect(struct musb *musb)
208 musb->xceiv->state = OTG_STATE_B_IDLE; 208 musb->xceiv->state = OTG_STATE_B_IDLE;
209 break; 209 break;
210 default: 210 default:
211 DBG(1, "host disconnect (%s)\n", 211 dev_dbg(musb->controller, "host disconnect (%s)\n",
212 otg_state_string(musb->xceiv->state)); 212 otg_state_string(musb->xceiv->state));
213 } 213 }
214} 214}
@@ -288,7 +288,7 @@ int musb_hub_control(
288 default: 288 default:
289 goto error; 289 goto error;
290 } 290 }
291 DBG(5, "clear feature %d\n", wValue); 291 dev_dbg(musb->controller, "clear feature %d\n", wValue);
292 musb->port1_status &= ~(1 << wValue); 292 musb->port1_status &= ~(1 << wValue);
293 break; 293 break;
294 case GetHubDescriptor: 294 case GetHubDescriptor:
@@ -330,7 +330,7 @@ int musb_hub_control(
330 330
331 power = musb_readb(musb->mregs, MUSB_POWER); 331 power = musb_readb(musb->mregs, MUSB_POWER);
332 power &= ~MUSB_POWER_RESUME; 332 power &= ~MUSB_POWER_RESUME;
333 DBG(4, "root port resume stopped, power %02x\n", 333 dev_dbg(musb->controller, "root port resume stopped, power %02x\n",
334 power); 334 power);
335 musb_writeb(musb->mregs, MUSB_POWER, power); 335 musb_writeb(musb->mregs, MUSB_POWER, power);
336 336
@@ -353,7 +353,7 @@ int musb_hub_control(
353 (__le32 *) buf); 353 (__le32 *) buf);
354 354
355 /* port change status is more interesting */ 355 /* port change status is more interesting */
356 DBG(get_unaligned((u16 *)(buf+2)) ? 2 : 5, "port status %08x\n", 356 dev_dbg(musb->controller, "port status %08x\n",
357 musb->port1_status); 357 musb->port1_status);
358 break; 358 break;
359 case SetPortFeature: 359 case SetPortFeature:
@@ -424,7 +424,7 @@ int musb_hub_control(
424 default: 424 default:
425 goto error; 425 goto error;
426 } 426 }
427 DBG(5, "set feature %d\n", wValue); 427 dev_dbg(musb->controller, "set feature %d\n", wValue);
428 musb->port1_status |= 1 << wValue; 428 musb->port1_status |= 1 << wValue;
429 break; 429 break;
430 430
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index d281792db05c..f70c5a577736 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -122,11 +122,12 @@ static void configure_channel(struct dma_channel *channel,
122{ 122{
123 struct musb_dma_channel *musb_channel = channel->private_data; 123 struct musb_dma_channel *musb_channel = channel->private_data;
124 struct musb_dma_controller *controller = musb_channel->controller; 124 struct musb_dma_controller *controller = musb_channel->controller;
125 struct musb *musb = controller->private_data;
125 void __iomem *mbase = controller->base; 126 void __iomem *mbase = controller->base;
126 u8 bchannel = musb_channel->idx; 127 u8 bchannel = musb_channel->idx;
127 u16 csr = 0; 128 u16 csr = 0;
128 129
129 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 130 dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
130 channel, packet_sz, dma_addr, len, mode); 131 channel, packet_sz, dma_addr, len, mode);
131 132
132 if (mode) { 133 if (mode) {
@@ -161,7 +162,7 @@ static int dma_channel_program(struct dma_channel *channel,
161 struct musb_dma_controller *controller = musb_channel->controller; 162 struct musb_dma_controller *controller = musb_channel->controller;
162 struct musb *musb = controller->private_data; 163 struct musb *musb = controller->private_data;
163 164
164 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 165 dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
165 musb_channel->epnum, 166 musb_channel->epnum,
166 musb_channel->transmit ? "Tx" : "Rx", 167 musb_channel->transmit ? "Tx" : "Rx",
167 packet_sz, dma_addr, len, mode); 168 packet_sz, dma_addr, len, mode);
@@ -274,7 +275,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
274#endif 275#endif
275 276
276 if (!int_hsdma) { 277 if (!int_hsdma) {
277 DBG(2, "spurious DMA irq\n"); 278 dev_dbg(musb->controller, "spurious DMA irq\n");
278 279
279 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 280 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
280 musb_channel = (struct musb_dma_channel *) 281 musb_channel = (struct musb_dma_channel *)
@@ -288,7 +289,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
288 } 289 }
289 } 290 }
290 291
291 DBG(2, "int_hsdma = 0x%x\n", int_hsdma); 292 dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
292 293
293 if (!int_hsdma) 294 if (!int_hsdma)
294 goto done; 295 goto done;
@@ -315,7 +316,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
315 channel->actual_len = addr 316 channel->actual_len = addr
316 - musb_channel->start_addr; 317 - musb_channel->start_addr;
317 318
318 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", 319 dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
319 channel, musb_channel->start_addr, 320 channel, musb_channel->start_addr,
320 addr, channel->actual_len, 321 addr, channel->actual_len,
321 musb_channel->len, 322 musb_channel->len,
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index b996fec84c29..c5d4c44d0ffa 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -76,7 +76,7 @@ static void musb_do_idle(unsigned long _musb)
76 if (musb->port1_status & MUSB_PORT_STAT_RESUME) { 76 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
77 power = musb_readb(musb->mregs, MUSB_POWER); 77 power = musb_readb(musb->mregs, MUSB_POWER);
78 power &= ~MUSB_POWER_RESUME; 78 power &= ~MUSB_POWER_RESUME;
79 DBG(1, "root port resume stopped, power %02x\n", power); 79 dev_dbg(musb->controller, "root port resume stopped, power %02x\n", power);
80 musb_writeb(musb->mregs, MUSB_POWER, power); 80 musb_writeb(musb->mregs, MUSB_POWER, power);
81 musb->is_active = 1; 81 musb->is_active = 1;
82 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND 82 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
@@ -114,7 +114,7 @@ static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
114 /* Never idle if active, or when VBUS timeout is not set as host */ 114 /* Never idle if active, or when VBUS timeout is not set as host */
115 if (musb->is_active || ((musb->a_wait_bcon == 0) 115 if (musb->is_active || ((musb->a_wait_bcon == 0)
116 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 116 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
117 DBG(4, "%s active, deleting timer\n", 117 dev_dbg(musb->controller, "%s active, deleting timer\n",
118 otg_state_string(musb->xceiv->state)); 118 otg_state_string(musb->xceiv->state));
119 del_timer(&musb_idle_timer); 119 del_timer(&musb_idle_timer);
120 last_timer = jiffies; 120 last_timer = jiffies;
@@ -125,13 +125,13 @@ static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
125 if (!timer_pending(&musb_idle_timer)) 125 if (!timer_pending(&musb_idle_timer))
126 last_timer = timeout; 126 last_timer = timeout;
127 else { 127 else {
128 DBG(4, "Longer idle timer already pending, ignoring\n"); 128 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
129 return; 129 return;
130 } 130 }
131 } 131 }
132 last_timer = timeout; 132 last_timer = timeout;
133 133
134 DBG(4, "%s inactive, for idle timer for %lu ms\n", 134 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
135 otg_state_string(musb->xceiv->state), 135 otg_state_string(musb->xceiv->state),
136 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 136 (unsigned long)jiffies_to_msecs(timeout - jiffies));
137 mod_timer(&musb_idle_timer, timeout); 137 mod_timer(&musb_idle_timer, timeout);
@@ -194,7 +194,7 @@ static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
194 } 194 }
195 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 195 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
196 196
197 DBG(1, "VBUS %s, devctl %02x " 197 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
198 /* otg %3x conf %08x prcm %08x */ "\n", 198 /* otg %3x conf %08x prcm %08x */ "\n",
199 otg_state_string(musb->xceiv->state), 199 otg_state_string(musb->xceiv->state),
200 musb_readb(musb->mregs, MUSB_DEVCTL)); 200 musb_readb(musb->mregs, MUSB_DEVCTL));
@@ -240,7 +240,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
240 240
241 switch (event) { 241 switch (event) {
242 case USB_EVENT_ID: 242 case USB_EVENT_ID:
243 DBG(4, "ID GND\n"); 243 dev_dbg(musb->controller, "ID GND\n");
244 244
245 if (is_otg_enabled(musb)) { 245 if (is_otg_enabled(musb)) {
246#ifdef CONFIG_USB_GADGET_MUSB_HDRC 246#ifdef CONFIG_USB_GADGET_MUSB_HDRC
@@ -258,7 +258,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
258 break; 258 break;
259 259
260 case USB_EVENT_VBUS: 260 case USB_EVENT_VBUS:
261 DBG(4, "VBUS Connect\n"); 261 dev_dbg(musb->controller, "VBUS Connect\n");
262 262
263#ifdef CONFIG_USB_GADGET_MUSB_HDRC 263#ifdef CONFIG_USB_GADGET_MUSB_HDRC
264 if (musb->gadget_driver) 264 if (musb->gadget_driver)
@@ -268,7 +268,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
268 break; 268 break;
269 269
270 case USB_EVENT_NONE: 270 case USB_EVENT_NONE:
271 DBG(4, "VBUS Disconnect\n"); 271 dev_dbg(musb->controller, "VBUS Disconnect\n");
272 272
273#ifdef CONFIG_USB_GADGET_MUSB_HDRC 273#ifdef CONFIG_USB_GADGET_MUSB_HDRC
274 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 274 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
@@ -286,7 +286,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
286 otg_shutdown(musb->xceiv); 286 otg_shutdown(musb->xceiv);
287 break; 287 break;
288 default: 288 default:
289 DBG(4, "ID float\n"); 289 dev_dbg(musb->controller, "ID float\n");
290 return NOTIFY_DONE; 290 return NOTIFY_DONE;
291 } 291 }
292 292
@@ -340,7 +340,7 @@ static int omap2430_musb_init(struct musb *musb)
340 status = otg_register_notifier(musb->xceiv, &musb->nb); 340 status = otg_register_notifier(musb->xceiv, &musb->nb);
341 341
342 if (status) 342 if (status)
343 DBG(1, "notification register failed\n"); 343 dev_dbg(musb->controller, "notification register failed\n");
344 344
345 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 345 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
346 346
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 221feaaded72..2f683a67ebb4 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -106,7 +106,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
@@ -115,7 +115,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0; 121 phy_otg_ctrl = 0;
@@ -178,7 +178,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
178 178
179 prefetch(buf); 179 prefetch(buf);
180 180
181 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 181 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
182 'T', epnum, fifo, len, buf); 182 'T', epnum, fifo, len, buf);
183 183
184 if (epnum) 184 if (epnum)
@@ -225,7 +225,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
225 void __iomem *fifo = hw_ep->fifo; 225 void __iomem *fifo = hw_ep->fifo;
226 u8 epnum = hw_ep->epnum; 226 u8 epnum = hw_ep->epnum;
227 227
228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 228 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'R', epnum, fifo, len, buf); 229 'R', epnum, fifo, len, buf);
230 230
231 if (epnum) 231 if (epnum)
@@ -304,7 +304,7 @@ static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
304 } 304 }
305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
306 306
307 DBG(2, "draw max %d mA VBUS\n", mA); 307 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
308 return 0; 308 return 0;
309} 309}
310 310
@@ -374,7 +374,7 @@ static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376 376
377 DBG(6, "idle, wake on %02x\n", wakeup_enables); 377 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
378} 378}
379 379
380/* 380/*
@@ -421,7 +421,7 @@ static void musb_do_idle(unsigned long _musb)
421 if ((musb->a_wait_bcon != 0) 421 if ((musb->a_wait_bcon != 0)
422 && (musb->idle_timeout == 0 422 && (musb->idle_timeout == 0
423 || time_after(jiffies, musb->idle_timeout))) { 423 || time_after(jiffies, musb->idle_timeout))) {
424 DBG(4, "Nothing connected %s, turning off VBUS\n", 424 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
425 otg_state_string(musb->xceiv->state)); 425 otg_state_string(musb->xceiv->state));
426 } 426 }
427 /* FALLTHROUGH */ 427 /* FALLTHROUGH */
@@ -481,7 +481,7 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
481 /* Never idle if active, or when VBUS timeout is not set as host */ 481 /* Never idle if active, or when VBUS timeout is not set as host */
482 if (musb->is_active || ((musb->a_wait_bcon == 0) 482 if (musb->is_active || ((musb->a_wait_bcon == 0)
483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
484 DBG(4, "%s active, deleting timer\n", 484 dev_dbg(musb->controller, "%s active, deleting timer\n",
485 otg_state_string(musb->xceiv->state)); 485 otg_state_string(musb->xceiv->state));
486 del_timer(&musb_idle_timer); 486 del_timer(&musb_idle_timer);
487 last_timer = jiffies; 487 last_timer = jiffies;
@@ -492,13 +492,13 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
492 if (!timer_pending(&musb_idle_timer)) 492 if (!timer_pending(&musb_idle_timer))
493 last_timer = timeout; 493 last_timer = timeout;
494 else { 494 else {
495 DBG(4, "Longer idle timer already pending, ignoring\n"); 495 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
496 return; 496 return;
497 } 497 }
498 } 498 }
499 last_timer = timeout; 499 last_timer = timeout;
500 500
501 DBG(4, "%s inactive, for idle timer for %lu ms\n", 501 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
502 otg_state_string(musb->xceiv->state), 502 otg_state_string(musb->xceiv->state),
503 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 503 (unsigned long)jiffies_to_msecs(timeout - jiffies));
504 mod_timer(&musb_idle_timer, timeout); 504 mod_timer(&musb_idle_timer, timeout);
@@ -573,7 +573,7 @@ static void tusb_musb_set_vbus(struct musb *musb, int is_on)
573 musb_writel(tbase, TUSB_DEV_CONF, conf); 573 musb_writel(tbase, TUSB_DEV_CONF, conf);
574 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 574 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
575 575
576 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 576 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
577 otg_state_string(musb->xceiv->state), 577 otg_state_string(musb->xceiv->state),
578 musb_readb(musb->mregs, MUSB_DEVCTL), 578 musb_readb(musb->mregs, MUSB_DEVCTL),
579 musb_readl(tbase, TUSB_DEV_OTG_STAT), 579 musb_readl(tbase, TUSB_DEV_OTG_STAT),
@@ -634,7 +634,7 @@ static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
634#endif 634#endif
635 635
636 default: 636 default:
637 DBG(2, "Trying to set mode %i\n", musb_mode); 637 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
638 return -EINVAL; 638 return -EINVAL;
639 } 639 }
640 640
@@ -667,7 +667,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
667 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 667 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
668 else 668 else
669 default_a = is_host_enabled(musb); 669 default_a = is_host_enabled(musb);
670 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 670 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
671 musb->xceiv->default_a = default_a; 671 musb->xceiv->default_a = default_a;
672 tusb_musb_set_vbus(musb, default_a); 672 tusb_musb_set_vbus(musb, default_a);
673 673
@@ -694,7 +694,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
694#endif 694#endif
695 695
696 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 696 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
697 DBG(1, "Forcing disconnect (no interrupt)\n"); 697 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
698 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 698 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
699 /* INTR_DISCONNECT can hide... */ 699 /* INTR_DISCONNECT can hide... */
700 musb->xceiv->state = OTG_STATE_B_IDLE; 700 musb->xceiv->state = OTG_STATE_B_IDLE;
@@ -702,18 +702,18 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
702 } 702 }
703 musb->is_active = 0; 703 musb->is_active = 0;
704 } 704 }
705 DBG(2, "vbus change, %s, otg %03x\n", 705 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
706 otg_state_string(musb->xceiv->state), otg_stat); 706 otg_state_string(musb->xceiv->state), otg_stat);
707 idle_timeout = jiffies + (1 * HZ); 707 idle_timeout = jiffies + (1 * HZ);
708 schedule_work(&musb->irq_work); 708 schedule_work(&musb->irq_work);
709 709
710 } else /* A-dev state machine */ { 710 } else /* A-dev state machine */ {
711 DBG(2, "vbus change, %s, otg %03x\n", 711 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
712 otg_state_string(musb->xceiv->state), otg_stat); 712 otg_state_string(musb->xceiv->state), otg_stat);
713 713
714 switch (musb->xceiv->state) { 714 switch (musb->xceiv->state) {
715 case OTG_STATE_A_IDLE: 715 case OTG_STATE_A_IDLE:
716 DBG(2, "Got SRP, turning on VBUS\n"); 716 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
717 musb_platform_set_vbus(musb, 1); 717 musb_platform_set_vbus(musb, 1);
718 718
719 /* CONNECT can wake if a_wait_bcon is set */ 719 /* CONNECT can wake if a_wait_bcon is set */
@@ -757,7 +757,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
757 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 757 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
758 u8 devctl; 758 u8 devctl;
759 759
760 DBG(4, "%s timer, %03x\n", 760 dev_dbg(musb->controller, "%s timer, %03x\n",
761 otg_state_string(musb->xceiv->state), otg_stat); 761 otg_state_string(musb->xceiv->state), otg_stat);
762 762
763 switch (musb->xceiv->state) { 763 switch (musb->xceiv->state) {
@@ -769,7 +769,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
769 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 769 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
770 if ((devctl & MUSB_DEVCTL_VBUS) 770 if ((devctl & MUSB_DEVCTL_VBUS)
771 != MUSB_DEVCTL_VBUS) { 771 != MUSB_DEVCTL_VBUS) {
772 DBG(2, "devctl %02x\n", devctl); 772 dev_dbg(musb->controller, "devctl %02x\n", devctl);
773 break; 773 break;
774 } 774 }
775 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 775 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
@@ -814,7 +814,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
814 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 814 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
815 815
816 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 816 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
817 DBG(3, "TUSB IRQ %08x\n", int_src); 817 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
818 818
819 musb->int_usb = (u8) int_src; 819 musb->int_usb = (u8) int_src;
820 820
@@ -835,7 +835,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
835 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 835 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
836 if (reg == i) 836 if (reg == i)
837 break; 837 break;
838 DBG(6, "TUSB NOR not ready\n"); 838 dev_dbg(musb->controller, "TUSB NOR not ready\n");
839 } 839 }
840 840
841 /* work around issue 13 (2nd half) */ 841 /* work around issue 13 (2nd half) */
@@ -847,7 +847,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
847 musb->is_active = 1; 847 musb->is_active = 1;
848 schedule_work(&musb->irq_work); 848 schedule_work(&musb->irq_work);
849 } 849 }
850 DBG(3, "wake %sactive %02x\n", 850 dev_dbg(musb->controller, "wake %sactive %02x\n",
851 musb->is_active ? "" : "in", reg); 851 musb->is_active ? "" : "in", reg);
852 852
853 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 853 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
@@ -869,7 +869,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
869 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 869 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
870 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 870 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
871 871
872 DBG(3, "DMA IRQ %08x\n", dma_src); 872 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
873 real_dma_src = ~real_dma_src & dma_src; 873 real_dma_src = ~real_dma_src & dma_src;
874 if (tusb_dma_omap() && real_dma_src) { 874 if (tusb_dma_omap() && real_dma_src) {
875 int tx_source = (real_dma_src & 0xffff); 875 int tx_source = (real_dma_src & 0xffff);
@@ -877,7 +877,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
877 877
878 for (i = 1; i <= 15; i++) { 878 for (i = 1; i <= 15; i++) {
879 if (tx_source & (1 << i)) { 879 if (tx_source & (1 << i)) {
880 DBG(3, "completing ep%i %s\n", i, "tx"); 880 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
881 musb_dma_completion(musb, i, 1); 881 musb_dma_completion(musb, i, 1);
882 } 882 }
883 } 883 }
diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
index 99cb541e4ef0..c784e6c03aac 100644
--- a/drivers/usb/musb/tusb6010_omap.c
+++ b/drivers/usb/musb/tusb6010_omap.c
@@ -65,7 +65,7 @@ static int tusb_omap_dma_start(struct dma_controller *c)
65 65
66 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 66 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
67 67
68 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 68 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
69 69
70 return 0; 70 return 0;
71} 71}
@@ -76,7 +76,7 @@ static int tusb_omap_dma_stop(struct dma_controller *c)
76 76
77 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 77 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
78 78
79 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 79 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
80 80
81 return 0; 81 return 0;
82} 82}
@@ -89,7 +89,7 @@ static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
89 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 89 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
90 90
91 if (reg != 0) { 91 if (reg != 0) {
92 DBG(3, "ep%i dmareq0 is busy for ep%i\n", 92 dev_dbg(musb->controller, "ep%i dmareq0 is busy for ep%i\n",
93 chdat->epnum, reg & 0xf); 93 chdat->epnum, reg & 0xf);
94 return -EAGAIN; 94 return -EAGAIN;
95 } 95 }
@@ -143,7 +143,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
143 if (ch_status != OMAP_DMA_BLOCK_IRQ) 143 if (ch_status != OMAP_DMA_BLOCK_IRQ)
144 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 144 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
145 145
146 DBG(3, "ep%i %s dma callback ch: %i status: %x\n", 146 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
147 chdat->epnum, chdat->tx ? "tx" : "rx", 147 chdat->epnum, chdat->tx ? "tx" : "rx",
148 ch, ch_status); 148 ch, ch_status);
149 149
@@ -156,7 +156,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
156 156
157 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 157 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
158 if (unlikely(remaining > chdat->transfer_len)) { 158 if (unlikely(remaining > chdat->transfer_len)) {
159 DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 159 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
160 chdat->tx ? "tx" : "rx", chdat->ch, 160 chdat->tx ? "tx" : "rx", chdat->ch,
161 remaining); 161 remaining);
162 remaining = 0; 162 remaining = 0;
@@ -165,13 +165,13 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
165 channel->actual_len = chdat->transfer_len - remaining; 165 channel->actual_len = chdat->transfer_len - remaining;
166 pio = chdat->len - channel->actual_len; 166 pio = chdat->len - channel->actual_len;
167 167
168 DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 168 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
169 169
170 /* Transfer remaining 1 - 31 bytes */ 170 /* Transfer remaining 1 - 31 bytes */
171 if (pio > 0 && pio < 32) { 171 if (pio > 0 && pio < 32) {
172 u8 *buf; 172 u8 *buf;
173 173
174 DBG(3, "Using PIO for remaining %lu bytes\n", pio); 174 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
175 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 175 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
176 if (chdat->tx) { 176 if (chdat->tx) {
177 dma_unmap_single(dev, chdat->dma_addr, 177 dma_unmap_single(dev, chdat->dma_addr,
@@ -209,7 +209,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
209 u16 csr; 209 u16 csr;
210 210
211 if (chdat->tx) { 211 if (chdat->tx) {
212 DBG(3, "terminating short tx packet\n"); 212 dev_dbg(musb->controller, "terminating short tx packet\n");
213 musb_ep_select(mbase, chdat->epnum); 213 musb_ep_select(mbase, chdat->epnum);
214 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 214 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
215 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 215 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
@@ -264,7 +264,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
264 264
265 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 265 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
266 if (dma_remaining) { 266 if (dma_remaining) {
267 DBG(2, "Busy %s dma ch%i, not using: %08x\n", 267 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
268 chdat->tx ? "tx" : "rx", chdat->ch, 268 chdat->tx ? "tx" : "rx", chdat->ch,
269 dma_remaining); 269 dma_remaining);
270 return false; 270 return false;
@@ -283,7 +283,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
283 sync_dev = chdat->sync_dev; 283 sync_dev = chdat->sync_dev;
284 } else { 284 } else {
285 if (tusb_omap_use_shared_dmareq(chdat) != 0) { 285 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
286 DBG(3, "could not get dma for ep%i\n", chdat->epnum); 286 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
287 return false; 287 return false;
288 } 288 }
289 if (tusb_dma->ch < 0) { 289 if (tusb_dma->ch < 0) {
@@ -326,7 +326,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
326 326
327 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 327 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
328 328
329 DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n", 329 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
330 chdat->epnum, chdat->tx ? "tx" : "rx", 330 chdat->epnum, chdat->tx ? "tx" : "rx",
331 ch, dma_addr, chdat->transfer_len, len, 331 ch, dma_addr, chdat->transfer_len, len,
332 chdat->transfer_packet_sz, packet_sz); 332 chdat->transfer_packet_sz, packet_sz);
@@ -370,7 +370,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
370 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 370 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
371 } 371 }
372 372
373 DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 373 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
374 chdat->epnum, chdat->tx ? "tx" : "rx", 374 chdat->epnum, chdat->tx ? "tx" : "rx",
375 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 375 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
376 ((dma_addr & 0x3) == 0) ? "sync" : "async", 376 ((dma_addr & 0x3) == 0) ? "sync" : "async",
@@ -525,7 +525,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
525 525
526 /* REVISIT: Why does dmareq5 not work? */ 526 /* REVISIT: Why does dmareq5 not work? */
527 if (hw_ep->epnum == 0) { 527 if (hw_ep->epnum == 0) {
528 DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 528 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
529 return NULL; 529 return NULL;
530 } 530 }
531 531
@@ -585,7 +585,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
585 chdat->ch = -1; 585 chdat->ch = -1;
586 } 586 }
587 587
588 DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 588 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
589 chdat->epnum, 589 chdat->epnum,
590 chdat->tx ? "tx" : "rx", 590 chdat->tx ? "tx" : "rx",
591 chdat->ch >= 0 ? "dedicated" : "shared", 591 chdat->ch >= 0 ? "dedicated" : "shared",
@@ -598,7 +598,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
598free_dmareq: 598free_dmareq:
599 tusb_omap_dma_free_dmareq(chdat); 599 tusb_omap_dma_free_dmareq(chdat);
600 600
601 DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum); 601 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
602 channel->status = MUSB_DMA_STATUS_UNKNOWN; 602 channel->status = MUSB_DMA_STATUS_UNKNOWN;
603 603
604 return NULL; 604 return NULL;
@@ -611,7 +611,7 @@ static void tusb_omap_dma_release(struct dma_channel *channel)
611 void __iomem *tbase = musb->ctrl_base; 611 void __iomem *tbase = musb->ctrl_base;
612 u32 reg; 612 u32 reg;
613 613
614 DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch); 614 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
615 615
616 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 616 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
617 if (chdat->tx) 617 if (chdat->tx)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 09:31:16 -0500