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authorGreg Kroah-Hartman <gregkh@suse.de>2010-05-17 13:33:41 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-05-20 16:21:47 -0400
commita320471147fe61ed9260295958f07cc23ec360c8 (patch)
tree7a324996de1f0e897f8efbad1a2ba55ed347e943 /drivers/usb/serial/io_ti.h
parent3bb36aa266f11f762e345cc85499a15d8df7ec51 (diff)
USB: io_edgeport: checkpatch cleanups
Minor whitespace cleanups to make checkpatch happy. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/serial/io_ti.h')
-rw-r--r--drivers/usb/serial/io_ti.h92
1 files changed, 49 insertions, 43 deletions
diff --git a/drivers/usb/serial/io_ti.h b/drivers/usb/serial/io_ti.h
index cab84f2256b9..1bd67b24f916 100644
--- a/drivers/usb/serial/io_ti.h
+++ b/drivers/usb/serial/io_ti.h
@@ -1,4 +1,4 @@
1/***************************************************************************** 1/*****************************************************************************
2 * 2 *
3 * Copyright (C) 1997-2002 Inside Out Networks, Inc. 3 * Copyright (C) 1997-2002 Inside Out Networks, Inc.
4 * 4 *
@@ -22,10 +22,10 @@
22#define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */ 22#define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */
23#define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */ 23#define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */
24 24
25// UART Defines 25/* UART Defines */
26#define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */ 26#define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */
27#define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */ 27#define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */
28#define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */ 28#define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */
29 29
30/* Bits per character */ 30/* Bits per character */
31#define UMP_UART_CHAR5BITS 0x00 31#define UMP_UART_CHAR5BITS 0x00
@@ -54,7 +54,7 @@
54#define UMP_UART_LSR_RX_MASK 0x10 54#define UMP_UART_LSR_RX_MASK 0x10
55#define UMP_UART_LSR_TX_MASK 0x20 55#define UMP_UART_LSR_TX_MASK 0x20
56 56
57#define UMP_UART_LSR_DATA_MASK ( LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK ) 57#define UMP_UART_LSR_DATA_MASK (LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)
58 58
59/* Port Settings Constants) */ 59/* Port Settings Constants) */
60#define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001 60#define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001
@@ -79,50 +79,57 @@
79#define UMP_PORT_DIR_OUT 0x01 79#define UMP_PORT_DIR_OUT 0x01
80#define UMP_PORT_DIR_IN 0x02 80#define UMP_PORT_DIR_IN 0x02
81 81
82// Address of Port 0 82/* Address of Port 0 */
83#define UMPM_UART1_PORT 0x03 83#define UMPM_UART1_PORT 0x03
84 84
85// Commands 85/* Commands */
86#define UMPC_SET_CONFIG 0x05 86#define UMPC_SET_CONFIG 0x05
87#define UMPC_OPEN_PORT 0x06 87#define UMPC_OPEN_PORT 0x06
88#define UMPC_CLOSE_PORT 0x07 88#define UMPC_CLOSE_PORT 0x07
89#define UMPC_START_PORT 0x08 89#define UMPC_START_PORT 0x08
90#define UMPC_STOP_PORT 0x09 90#define UMPC_STOP_PORT 0x09
91#define UMPC_TEST_PORT 0x0A 91#define UMPC_TEST_PORT 0x0A
92#define UMPC_PURGE_PORT 0x0B 92#define UMPC_PURGE_PORT 0x0B
93 93
94#define UMPC_COMPLETE_READ 0x80 // Force the Firmware to complete the current Read 94/* Force the Firmware to complete the current Read */
95#define UMPC_HARDWARE_RESET 0x81 // Force UMP back into BOOT Mode 95#define UMPC_COMPLETE_READ 0x80
96#define UMPC_COPY_DNLD_TO_I2C 0x82 // Copy current download image to type 0xf2 record in 16k I2C 96/* Force UMP back into BOOT Mode */
97 // firmware will change 0xff record to type 2 record when complete 97#define UMPC_HARDWARE_RESET 0x81
98/*
99 * Copy current download image to type 0xf2 record in 16k I2C
100 * firmware will change 0xff record to type 2 record when complete
101 */
102#define UMPC_COPY_DNLD_TO_I2C 0x82
98 103
99 // Special function register commands 104/*
100 // wIndex is register address 105 * Special function register commands
101 // wValue is MSB/LSB mask/data 106 * wIndex is register address
102#define UMPC_WRITE_SFR 0x83 // Write SFR Register 107 * wValue is MSB/LSB mask/data
108 */
109#define UMPC_WRITE_SFR 0x83 /* Write SFR Register */
103 110
104 // wIndex is register address 111/* wIndex is register address */
105#define UMPC_READ_SFR 0x84 // Read SRF Register 112#define UMPC_READ_SFR 0x84 /* Read SRF Register */
106 113
107 // Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) 114/* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
108#define UMPC_SET_CLR_DTR 0x85 115#define UMPC_SET_CLR_DTR 0x85
109 116
110 // Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) 117/* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
111#define UMPC_SET_CLR_RTS 0x86 118#define UMPC_SET_CLR_RTS 0x86
112 119
113 // Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) 120/* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
114#define UMPC_SET_CLR_LOOPBACK 0x87 121#define UMPC_SET_CLR_LOOPBACK 0x87
115 122
116 // Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) 123/* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
117#define UMPC_SET_CLR_BREAK 0x88 124#define UMPC_SET_CLR_BREAK 0x88
118 125
119 // Read MSR wIndex ModuleID (port) 126/* Read MSR wIndex ModuleID (port) */
120#define UMPC_READ_MSR 0x89 127#define UMPC_READ_MSR 0x89
121 128
122 /* Toolkit commands */ 129/* Toolkit commands */
123 /* Read-write group */ 130/* Read-write group */
124#define UMPC_MEMORY_READ 0x92 131#define UMPC_MEMORY_READ 0x92
125#define UMPC_MEMORY_WRITE 0x93 132#define UMPC_MEMORY_WRITE 0x93
126 133
127/* 134/*
128 * UMP DMA Definitions 135 * UMP DMA Definitions
@@ -130,8 +137,7 @@
130#define UMPD_OEDB1_ADDRESS 0xFF08 137#define UMPD_OEDB1_ADDRESS 0xFF08
131#define UMPD_OEDB2_ADDRESS 0xFF10 138#define UMPD_OEDB2_ADDRESS 0xFF10
132 139
133struct out_endpoint_desc_block 140struct out_endpoint_desc_block {
134{
135 __u8 Configuration; 141 __u8 Configuration;
136 __u8 XBufAddr; 142 __u8 XBufAddr;
137 __u8 XByteCount; 143 __u8 XByteCount;
@@ -147,8 +153,8 @@ struct out_endpoint_desc_block
147 * TYPE DEFINITIONS 153 * TYPE DEFINITIONS
148 * Structures for Firmware commands 154 * Structures for Firmware commands
149 */ 155 */
150struct ump_uart_config /* UART settings */ 156/* UART settings */
151{ 157struct ump_uart_config {
152 __u16 wBaudRate; /* Baud rate */ 158 __u16 wBaudRate; /* Baud rate */
153 __u16 wFlags; /* Bitmap mask of flags */ 159 __u16 wFlags; /* Bitmap mask of flags */
154 __u8 bDataBits; /* 5..8 - data bits per character */ 160 __u8 bDataBits; /* 5..8 - data bits per character */
@@ -165,8 +171,8 @@ struct ump_uart_config /* UART settings */
165 * TYPE DEFINITIONS 171 * TYPE DEFINITIONS
166 * Structures for USB interrupts 172 * Structures for USB interrupts
167 */ 173 */
168struct ump_interrupt /* Interrupt packet structure */ 174/* Interrupt packet structure */
169{ 175struct ump_interrupt {
170 __u8 bICode; /* Interrupt code (interrupt num) */ 176 __u8 bICode; /* Interrupt code (interrupt num) */
171 __u8 bIInfo; /* Interrupt information */ 177 __u8 bIInfo; /* Interrupt information */
172} __attribute__((packed)); 178} __attribute__((packed));