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authorFelipe Balbi <balbi@ti.com>2013-03-07 04:01:15 -0500
committerFelipe Balbi <balbi@ti.com>2013-03-18 05:18:04 -0400
commita0e631235a04f8a815a1ecec93ef418f7d1e6086 (patch)
tree448db1daeeab6801efdedf77e25823ee27a403c8 /drivers/usb/phy
parent110ff6d04162a8a3b288019eaf84dee0800270e0 (diff)
usb: phy: move all PHY drivers to drivers/usb/phy/
that's a much more reasonable location for those drivers. It helps us saving drivers/usb/otg/ for when we actually start adding generic OTG code. Also completely delete drivers/usb/otg/ as there's nothing left there. Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/phy')
-rw-r--r--drivers/usb/phy/Kconfig168
-rw-r--r--drivers/usb/phy/Makefile24
-rw-r--r--drivers/usb/phy/ab8500-usb.c596
-rw-r--r--drivers/usb/phy/fsl_otg.c1173
-rw-r--r--drivers/usb/phy/fsl_otg.h406
-rw-r--r--drivers/usb/phy/gpio_vbus.c416
-rw-r--r--drivers/usb/phy/isp1301_omap.c1656
-rw-r--r--drivers/usb/phy/msm_otg.c1762
-rw-r--r--drivers/usb/phy/mv_otg.c923
-rw-r--r--drivers/usb/phy/mv_otg.h165
-rw-r--r--drivers/usb/phy/mxs-phy.c220
-rw-r--r--drivers/usb/phy/nop-usb-xceiv.c294
-rw-r--r--drivers/usb/phy/otg_fsm.c348
-rw-r--r--drivers/usb/phy/otg_fsm.h154
-rw-r--r--drivers/usb/phy/twl4030-usb.c728
-rw-r--r--drivers/usb/phy/twl6030-usb.c446
-rw-r--r--drivers/usb/phy/ulpi.c283
-rw-r--r--drivers/usb/phy/ulpi_viewport.c80
18 files changed, 9821 insertions, 21 deletions
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 65217a590068..32ce740a9dd5 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -4,6 +4,73 @@
4comment "USB Physical Layer drivers" 4comment "USB Physical Layer drivers"
5 depends on USB || USB_GADGET 5 depends on USB || USB_GADGET
6 6
7config USB_OTG_UTILS
8 bool
9 help
10 Select this to make sure the build includes objects from
11 the OTG infrastructure directory.
12
13if USB || USB_GADGET
14
15#
16# USB Transceiver Drivers
17#
18config AB8500_USB
19 tristate "AB8500 USB Transceiver Driver"
20 depends on AB8500_CORE
21 select USB_OTG_UTILS
22 help
23 Enable this to support the USB OTG transceiver in AB8500 chip.
24 This transceiver supports high and full speed devices plus,
25 in host mode, low speed.
26
27config FSL_USB2_OTG
28 bool "Freescale USB OTG Transceiver Driver"
29 depends on USB_EHCI_FSL && USB_FSL_USB2 && USB_SUSPEND
30 select USB_OTG
31 select USB_OTG_UTILS
32 help
33 Enable this to support Freescale USB OTG transceiver.
34
35config ISP1301_OMAP
36 tristate "Philips ISP1301 with OMAP OTG"
37 depends on I2C && ARCH_OMAP_OTG
38 select USB_OTG_UTILS
39 help
40 If you say yes here you get support for the Philips ISP1301
41 USB-On-The-Go transceiver working with the OMAP OTG controller.
42 The ISP1301 is a full speed USB transceiver which is used in
43 products including H2, H3, and H4 development boards for Texas
44 Instruments OMAP processors.
45
46 This driver can also be built as a module. If so, the module
47 will be called isp1301_omap.
48
49config MV_U3D_PHY
50 bool "Marvell USB 3.0 PHY controller Driver"
51 depends on USB_MV_U3D
52 select USB_OTG_UTILS
53 help
54 Enable this to support Marvell USB 3.0 phy controller for Marvell
55 SoC.
56
57config NOP_USB_XCEIV
58 tristate "NOP USB Transceiver Driver"
59 select USB_OTG_UTILS
60 help
61 This driver is to be used by all the usb transceiver which are either
62 built-in with usb ip or which are autonomous and doesn't require any
63 phy programming such as ISP1x04 etc.
64
65config OMAP_CONTROL_USB
66 tristate "OMAP CONTROL USB Driver"
67 help
68 Enable this to add support for the USB part present in the control
69 module. This driver has API to power on the USB2 PHY and to write to
70 the mailbox. The mailbox is present only in omap4 and the register to
71 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
72 additional register to power on USB3 PHY.
73
7config OMAP_USB2 74config OMAP_USB2
8 tristate "OMAP USB2 PHY Driver" 75 tristate "OMAP USB2 PHY Driver"
9 depends on ARCH_OMAP2PLUS 76 depends on ARCH_OMAP2PLUS
@@ -25,14 +92,45 @@ config OMAP_USB3
25 This driver interacts with the "OMAP Control USB Driver" to power 92 This driver interacts with the "OMAP Control USB Driver" to power
26 on/off the PHY. 93 on/off the PHY.
27 94
28config OMAP_CONTROL_USB 95config SAMSUNG_USBPHY
29 tristate "OMAP CONTROL USB Driver" 96 bool "Samsung USB PHY controller Driver"
97 depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
98 select USB_OTG_UTILS
30 help 99 help
31 Enable this to add support for the USB part present in the control 100 Enable this to support Samsung USB phy controller for samsung
32 module. This driver has API to power on the USB2 PHY and to write to 101 SoCs.
33 the mailbox. The mailbox is present only in omap4 and the register to 102
34 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an 103config TWL4030_USB
35 additional register to power on USB3 PHY. 104 tristate "TWL4030 USB Transceiver Driver"
105 depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
106 select USB_OTG_UTILS
107 help
108 Enable this to support the USB OTG transceiver on TWL4030
109 family chips (including the TWL5030 and TPS659x0 devices).
110 This transceiver supports high and full speed devices plus,
111 in host mode, low speed.
112
113config TWL6030_USB
114 tristate "TWL6030 USB Transceiver Driver"
115 depends on TWL4030_CORE && OMAP_USB2 && USB_MUSB_OMAP2PLUS
116 select USB_OTG_UTILS
117 help
118 Enable this to support the USB OTG transceiver on TWL6030
119 family chips. This TWL6030 transceiver has the VBUS and ID GND
120 and OTG SRP events capabilities. For all other transceiver functionality
121 UTMI PHY is embedded in OMAP4430. The internal PHY configurations APIs
122 are hooked to this driver through platform_data structure.
123 The definition of internal PHY APIs are in the mach-omap2 layer.
124
125config USB_GPIO_VBUS
126 tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
127 depends on GENERIC_GPIO
128 select USB_OTG_UTILS
129 help
130 Provides simple GPIO VBUS sensing for controllers with an
131 internal transceiver via the usb_phy interface, and
132 optionally control of a D+ pullup GPIO as well as a VBUS
133 current limit regulator.
36 134
37config USB_ISP1301 135config USB_ISP1301
38 tristate "NXP ISP1301 USB transceiver support" 136 tristate "NXP ISP1301 USB transceiver support"
@@ -46,13 +144,40 @@ config USB_ISP1301
46 To compile this driver as a module, choose M here: the 144 To compile this driver as a module, choose M here: the
47 module will be called isp1301. 145 module will be called isp1301.
48 146
49config MV_U3D_PHY 147config USB_MSM_OTG
50 bool "Marvell USB 3.0 PHY controller Driver" 148 tristate "OTG support for Qualcomm on-chip USB controller"
51 depends on USB_MV_U3D 149 depends on (USB || USB_GADGET) && ARCH_MSM
52 select USB_OTG_UTILS 150 select USB_OTG_UTILS
53 help 151 help
54 Enable this to support Marvell USB 3.0 phy controller for Marvell 152 Enable this to support the USB OTG transceiver on MSM chips. It
55 SoC. 153 handles PHY initialization, clock management, and workarounds
154 required after resetting the hardware and power management.
155 This driver is required even for peripheral only or host only
156 mode configurations.
157 This driver is not supported on boards like trout which
158 has an external PHY.
159
160config USB_MV_OTG
161 tristate "Marvell USB OTG support"
162 depends on USB_EHCI_MV && USB_MV_UDC && USB_SUSPEND
163 select USB_OTG
164 select USB_OTG_UTILS
165 help
166 Say Y here if you want to build Marvell USB OTG transciever
167 driver in kernel (including PXA and MMP series). This driver
168 implements role switch between EHCI host driver and gadget driver.
169
170 To compile this driver as a module, choose M here.
171
172config USB_MXS_PHY
173 tristate "Freescale MXS USB PHY support"
174 depends on ARCH_MXC || ARCH_MXS
175 select STMP_DEVICE
176 select USB_OTG_UTILS
177 help
178 Enable this to support the Freescale MXS USB PHY.
179
180 MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
56 181
57config USB_RCAR_PHY 182config USB_RCAR_PHY
58 tristate "Renesas R-Car USB phy support" 183 tristate "Renesas R-Car USB phy support"
@@ -66,10 +191,19 @@ config USB_RCAR_PHY
66 To compile this driver as a module, choose M here: the 191 To compile this driver as a module, choose M here: the
67 module will be called rcar-phy. 192 module will be called rcar-phy.
68 193
69config SAMSUNG_USBPHY 194config USB_ULPI
70 bool "Samsung USB PHY controller Driver" 195 bool "Generic ULPI Transceiver Driver"
71 depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS 196 depends on ARM
72 select USB_OTG_UTILS 197 select USB_OTG_UTILS
73 help 198 help
74 Enable this to support Samsung USB phy controller for samsung 199 Enable this to support ULPI connected USB OTG transceivers which
75 SoCs. 200 are likely found on embedded boards.
201
202config USB_ULPI_VIEWPORT
203 bool
204 depends on USB_ULPI
205 help
206 Provides read/write operations to the ULPI phy register set for
207 controllers with a viewport register (e.g. Chipidea/ARC controllers).
208
209endif # USB || OTG
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 9fa6327d4c52..34488ceef491 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,11 +5,27 @@
5ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG 5ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
6 6
7obj-$(CONFIG_USB_OTG_UTILS) += phy.o 7obj-$(CONFIG_USB_OTG_UTILS) += phy.o
8
9# transceiver drivers, keep the list sorted
10
11obj-$(CONFIG_AB8500_USB) += ab8500-usb.o
12fsl_usb2_otg-objs := fsl_otg.o otg_fsm.o
13obj-$(CONFIG_FSL_USB2_OTG) += fsl_usb2_otg.o
14obj-$(CONFIG_ISP1301_OMAP) += isp1301_omap.o
15obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o
16obj-$(CONFIG_NOP_USB_XCEIV) += nop-usb-xceiv.o
17obj-$(CONFIG_OMAP_CONTROL_USB) += omap-control-usb.o
8obj-$(CONFIG_OMAP_USB2) += omap-usb2.o 18obj-$(CONFIG_OMAP_USB2) += omap-usb2.o
9obj-$(CONFIG_OMAP_USB3) += omap-usb3.o 19obj-$(CONFIG_OMAP_USB3) += omap-usb3.o
10obj-$(CONFIG_OMAP_CONTROL_USB) += omap-control-usb.o 20obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o
21obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o
22obj-$(CONFIG_TWL6030_USB) += twl6030-usb.o
23obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o
24obj-$(CONFIG_USB_GPIO_VBUS) += gpio_vbus.o
11obj-$(CONFIG_USB_ISP1301) += isp1301.o 25obj-$(CONFIG_USB_ISP1301) += isp1301.o
12obj-$(CONFIG_MV_U3D_PHY) += mv_u3d_phy.o 26obj-$(CONFIG_USB_MSM_OTG) += msm_otg.o
13obj-$(CONFIG_USB_EHCI_TEGRA) += tegra_usb_phy.o 27obj-$(CONFIG_USB_MV_OTG) += mv_otg.o
28obj-$(CONFIG_USB_MXS_PHY) += mxs-phy.o
14obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o 29obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
15obj-$(CONFIG_SAMSUNG_USBPHY) += samsung-usbphy.o 30obj-$(CONFIG_USB_ULPI) += ulpi.o
31obj-$(CONFIG_USB_ULPI_VIEWPORT) += ulpi_viewport.o
diff --git a/drivers/usb/phy/ab8500-usb.c b/drivers/usb/phy/ab8500-usb.c
new file mode 100644
index 000000000000..2d86f26a0183
--- /dev/null
+++ b/drivers/usb/phy/ab8500-usb.c
@@ -0,0 +1,596 @@
1/*
2 * drivers/usb/otg/ab8500_usb.c
3 *
4 * USB transceiver driver for AB8500 chip
5 *
6 * Copyright (C) 2010 ST-Ericsson AB
7 * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/usb/otg.h>
28#include <linux/slab.h>
29#include <linux/notifier.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/mfd/abx500.h>
33#include <linux/mfd/abx500/ab8500.h>
34
35#define AB8500_MAIN_WD_CTRL_REG 0x01
36#define AB8500_USB_LINE_STAT_REG 0x80
37#define AB8500_USB_PHY_CTRL_REG 0x8A
38
39#define AB8500_BIT_OTG_STAT_ID (1 << 0)
40#define AB8500_BIT_PHY_CTRL_HOST_EN (1 << 0)
41#define AB8500_BIT_PHY_CTRL_DEVICE_EN (1 << 1)
42#define AB8500_BIT_WD_CTRL_ENABLE (1 << 0)
43#define AB8500_BIT_WD_CTRL_KICK (1 << 1)
44
45#define AB8500_V1x_LINK_STAT_WAIT (HZ/10)
46#define AB8500_WD_KICK_DELAY_US 100 /* usec */
47#define AB8500_WD_V11_DISABLE_DELAY_US 100 /* usec */
48#define AB8500_WD_V10_DISABLE_DELAY_MS 100 /* ms */
49
50/* Usb line status register */
51enum ab8500_usb_link_status {
52 USB_LINK_NOT_CONFIGURED = 0,
53 USB_LINK_STD_HOST_NC,
54 USB_LINK_STD_HOST_C_NS,
55 USB_LINK_STD_HOST_C_S,
56 USB_LINK_HOST_CHG_NM,
57 USB_LINK_HOST_CHG_HS,
58 USB_LINK_HOST_CHG_HS_CHIRP,
59 USB_LINK_DEDICATED_CHG,
60 USB_LINK_ACA_RID_A,
61 USB_LINK_ACA_RID_B,
62 USB_LINK_ACA_RID_C_NM,
63 USB_LINK_ACA_RID_C_HS,
64 USB_LINK_ACA_RID_C_HS_CHIRP,
65 USB_LINK_HM_IDGND,
66 USB_LINK_RESERVED,
67 USB_LINK_NOT_VALID_LINK
68};
69
70struct ab8500_usb {
71 struct usb_phy phy;
72 struct device *dev;
73 int irq_num_id_rise;
74 int irq_num_id_fall;
75 int irq_num_vbus_rise;
76 int irq_num_vbus_fall;
77 int irq_num_link_status;
78 unsigned vbus_draw;
79 struct delayed_work dwork;
80 struct work_struct phy_dis_work;
81 unsigned long link_status_wait;
82 int rev;
83};
84
85static inline struct ab8500_usb *phy_to_ab(struct usb_phy *x)
86{
87 return container_of(x, struct ab8500_usb, phy);
88}
89
90static void ab8500_usb_wd_workaround(struct ab8500_usb *ab)
91{
92 abx500_set_register_interruptible(ab->dev,
93 AB8500_SYS_CTRL2_BLOCK,
94 AB8500_MAIN_WD_CTRL_REG,
95 AB8500_BIT_WD_CTRL_ENABLE);
96
97 udelay(AB8500_WD_KICK_DELAY_US);
98
99 abx500_set_register_interruptible(ab->dev,
100 AB8500_SYS_CTRL2_BLOCK,
101 AB8500_MAIN_WD_CTRL_REG,
102 (AB8500_BIT_WD_CTRL_ENABLE
103 | AB8500_BIT_WD_CTRL_KICK));
104
105 if (ab->rev > 0x10) /* v1.1 v2.0 */
106 udelay(AB8500_WD_V11_DISABLE_DELAY_US);
107 else /* v1.0 */
108 msleep(AB8500_WD_V10_DISABLE_DELAY_MS);
109
110 abx500_set_register_interruptible(ab->dev,
111 AB8500_SYS_CTRL2_BLOCK,
112 AB8500_MAIN_WD_CTRL_REG,
113 0);
114}
115
116static void ab8500_usb_phy_ctrl(struct ab8500_usb *ab, bool sel_host,
117 bool enable)
118{
119 u8 ctrl_reg;
120 abx500_get_register_interruptible(ab->dev,
121 AB8500_USB,
122 AB8500_USB_PHY_CTRL_REG,
123 &ctrl_reg);
124 if (sel_host) {
125 if (enable)
126 ctrl_reg |= AB8500_BIT_PHY_CTRL_HOST_EN;
127 else
128 ctrl_reg &= ~AB8500_BIT_PHY_CTRL_HOST_EN;
129 } else {
130 if (enable)
131 ctrl_reg |= AB8500_BIT_PHY_CTRL_DEVICE_EN;
132 else
133 ctrl_reg &= ~AB8500_BIT_PHY_CTRL_DEVICE_EN;
134 }
135
136 abx500_set_register_interruptible(ab->dev,
137 AB8500_USB,
138 AB8500_USB_PHY_CTRL_REG,
139 ctrl_reg);
140
141 /* Needed to enable the phy.*/
142 if (enable)
143 ab8500_usb_wd_workaround(ab);
144}
145
146#define ab8500_usb_host_phy_en(ab) ab8500_usb_phy_ctrl(ab, true, true)
147#define ab8500_usb_host_phy_dis(ab) ab8500_usb_phy_ctrl(ab, true, false)
148#define ab8500_usb_peri_phy_en(ab) ab8500_usb_phy_ctrl(ab, false, true)
149#define ab8500_usb_peri_phy_dis(ab) ab8500_usb_phy_ctrl(ab, false, false)
150
151static int ab8500_usb_link_status_update(struct ab8500_usb *ab)
152{
153 u8 reg;
154 enum ab8500_usb_link_status lsts;
155 void *v = NULL;
156 enum usb_phy_events event;
157
158 abx500_get_register_interruptible(ab->dev,
159 AB8500_USB,
160 AB8500_USB_LINE_STAT_REG,
161 &reg);
162
163 lsts = (reg >> 3) & 0x0F;
164
165 switch (lsts) {
166 case USB_LINK_NOT_CONFIGURED:
167 case USB_LINK_RESERVED:
168 case USB_LINK_NOT_VALID_LINK:
169 /* TODO: Disable regulators. */
170 ab8500_usb_host_phy_dis(ab);
171 ab8500_usb_peri_phy_dis(ab);
172 ab->phy.state = OTG_STATE_B_IDLE;
173 ab->phy.otg->default_a = false;
174 ab->vbus_draw = 0;
175 event = USB_EVENT_NONE;
176 break;
177
178 case USB_LINK_STD_HOST_NC:
179 case USB_LINK_STD_HOST_C_NS:
180 case USB_LINK_STD_HOST_C_S:
181 case USB_LINK_HOST_CHG_NM:
182 case USB_LINK_HOST_CHG_HS:
183 case USB_LINK_HOST_CHG_HS_CHIRP:
184 if (ab->phy.otg->gadget) {
185 /* TODO: Enable regulators. */
186 ab8500_usb_peri_phy_en(ab);
187 v = ab->phy.otg->gadget;
188 }
189 event = USB_EVENT_VBUS;
190 break;
191
192 case USB_LINK_HM_IDGND:
193 if (ab->phy.otg->host) {
194 /* TODO: Enable regulators. */
195 ab8500_usb_host_phy_en(ab);
196 v = ab->phy.otg->host;
197 }
198 ab->phy.state = OTG_STATE_A_IDLE;
199 ab->phy.otg->default_a = true;
200 event = USB_EVENT_ID;
201 break;
202
203 case USB_LINK_ACA_RID_A:
204 case USB_LINK_ACA_RID_B:
205 /* TODO */
206 case USB_LINK_ACA_RID_C_NM:
207 case USB_LINK_ACA_RID_C_HS:
208 case USB_LINK_ACA_RID_C_HS_CHIRP:
209 case USB_LINK_DEDICATED_CHG:
210 /* TODO: vbus_draw */
211 event = USB_EVENT_CHARGER;
212 break;
213 }
214
215 atomic_notifier_call_chain(&ab->phy.notifier, event, v);
216
217 return 0;
218}
219
220static void ab8500_usb_delayed_work(struct work_struct *work)
221{
222 struct ab8500_usb *ab = container_of(work, struct ab8500_usb,
223 dwork.work);
224
225 ab8500_usb_link_status_update(ab);
226}
227
228static irqreturn_t ab8500_usb_v1x_common_irq(int irq, void *data)
229{
230 struct ab8500_usb *ab = (struct ab8500_usb *) data;
231
232 /* Wait for link status to become stable. */
233 schedule_delayed_work(&ab->dwork, ab->link_status_wait);
234
235 return IRQ_HANDLED;
236}
237
238static irqreturn_t ab8500_usb_v1x_vbus_fall_irq(int irq, void *data)
239{
240 struct ab8500_usb *ab = (struct ab8500_usb *) data;
241
242 /* Link status will not be updated till phy is disabled. */
243 ab8500_usb_peri_phy_dis(ab);
244
245 /* Wait for link status to become stable. */
246 schedule_delayed_work(&ab->dwork, ab->link_status_wait);
247
248 return IRQ_HANDLED;
249}
250
251static irqreturn_t ab8500_usb_v20_irq(int irq, void *data)
252{
253 struct ab8500_usb *ab = (struct ab8500_usb *) data;
254
255 ab8500_usb_link_status_update(ab);
256
257 return IRQ_HANDLED;
258}
259
260static void ab8500_usb_phy_disable_work(struct work_struct *work)
261{
262 struct ab8500_usb *ab = container_of(work, struct ab8500_usb,
263 phy_dis_work);
264
265 if (!ab->phy.otg->host)
266 ab8500_usb_host_phy_dis(ab);
267
268 if (!ab->phy.otg->gadget)
269 ab8500_usb_peri_phy_dis(ab);
270}
271
272static int ab8500_usb_set_power(struct usb_phy *phy, unsigned mA)
273{
274 struct ab8500_usb *ab;
275
276 if (!phy)
277 return -ENODEV;
278
279 ab = phy_to_ab(phy);
280
281 ab->vbus_draw = mA;
282
283 if (mA)
284 atomic_notifier_call_chain(&ab->phy.notifier,
285 USB_EVENT_ENUMERATED, ab->phy.otg->gadget);
286 return 0;
287}
288
289/* TODO: Implement some way for charging or other drivers to read
290 * ab->vbus_draw.
291 */
292
293static int ab8500_usb_set_suspend(struct usb_phy *x, int suspend)
294{
295 /* TODO */
296 return 0;
297}
298
299static int ab8500_usb_set_peripheral(struct usb_otg *otg,
300 struct usb_gadget *gadget)
301{
302 struct ab8500_usb *ab;
303
304 if (!otg)
305 return -ENODEV;
306
307 ab = phy_to_ab(otg->phy);
308
309 /* Some drivers call this function in atomic context.
310 * Do not update ab8500 registers directly till this
311 * is fixed.
312 */
313
314 if (!gadget) {
315 /* TODO: Disable regulators. */
316 otg->gadget = NULL;
317 schedule_work(&ab->phy_dis_work);
318 } else {
319 otg->gadget = gadget;
320 otg->phy->state = OTG_STATE_B_IDLE;
321
322 /* Phy will not be enabled if cable is already
323 * plugged-in. Schedule to enable phy.
324 * Use same delay to avoid any race condition.
325 */
326 schedule_delayed_work(&ab->dwork, ab->link_status_wait);
327 }
328
329 return 0;
330}
331
332static int ab8500_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
333{
334 struct ab8500_usb *ab;
335
336 if (!otg)
337 return -ENODEV;
338
339 ab = phy_to_ab(otg->phy);
340
341 /* Some drivers call this function in atomic context.
342 * Do not update ab8500 registers directly till this
343 * is fixed.
344 */
345
346 if (!host) {
347 /* TODO: Disable regulators. */
348 otg->host = NULL;
349 schedule_work(&ab->phy_dis_work);
350 } else {
351 otg->host = host;
352 /* Phy will not be enabled if cable is already
353 * plugged-in. Schedule to enable phy.
354 * Use same delay to avoid any race condition.
355 */
356 schedule_delayed_work(&ab->dwork, ab->link_status_wait);
357 }
358
359 return 0;
360}
361
362static void ab8500_usb_irq_free(struct ab8500_usb *ab)
363{
364 if (ab->rev < 0x20) {
365 free_irq(ab->irq_num_id_rise, ab);
366 free_irq(ab->irq_num_id_fall, ab);
367 free_irq(ab->irq_num_vbus_rise, ab);
368 free_irq(ab->irq_num_vbus_fall, ab);
369 } else {
370 free_irq(ab->irq_num_link_status, ab);
371 }
372}
373
374static int ab8500_usb_v1x_res_setup(struct platform_device *pdev,
375 struct ab8500_usb *ab)
376{
377 int err;
378
379 ab->irq_num_id_rise = platform_get_irq_byname(pdev, "ID_WAKEUP_R");
380 if (ab->irq_num_id_rise < 0) {
381 dev_err(&pdev->dev, "ID rise irq not found\n");
382 return ab->irq_num_id_rise;
383 }
384 err = request_threaded_irq(ab->irq_num_id_rise, NULL,
385 ab8500_usb_v1x_common_irq,
386 IRQF_NO_SUSPEND | IRQF_SHARED,
387 "usb-id-rise", ab);
388 if (err < 0) {
389 dev_err(ab->dev, "request_irq failed for ID rise irq\n");
390 goto fail0;
391 }
392
393 ab->irq_num_id_fall = platform_get_irq_byname(pdev, "ID_WAKEUP_F");
394 if (ab->irq_num_id_fall < 0) {
395 dev_err(&pdev->dev, "ID fall irq not found\n");
396 return ab->irq_num_id_fall;
397 }
398 err = request_threaded_irq(ab->irq_num_id_fall, NULL,
399 ab8500_usb_v1x_common_irq,
400 IRQF_NO_SUSPEND | IRQF_SHARED,
401 "usb-id-fall", ab);
402 if (err < 0) {
403 dev_err(ab->dev, "request_irq failed for ID fall irq\n");
404 goto fail1;
405 }
406
407 ab->irq_num_vbus_rise = platform_get_irq_byname(pdev, "VBUS_DET_R");
408 if (ab->irq_num_vbus_rise < 0) {
409 dev_err(&pdev->dev, "VBUS rise irq not found\n");
410 return ab->irq_num_vbus_rise;
411 }
412 err = request_threaded_irq(ab->irq_num_vbus_rise, NULL,
413 ab8500_usb_v1x_common_irq,
414 IRQF_NO_SUSPEND | IRQF_SHARED,
415 "usb-vbus-rise", ab);
416 if (err < 0) {
417 dev_err(ab->dev, "request_irq failed for Vbus rise irq\n");
418 goto fail2;
419 }
420
421 ab->irq_num_vbus_fall = platform_get_irq_byname(pdev, "VBUS_DET_F");
422 if (ab->irq_num_vbus_fall < 0) {
423 dev_err(&pdev->dev, "VBUS fall irq not found\n");
424 return ab->irq_num_vbus_fall;
425 }
426 err = request_threaded_irq(ab->irq_num_vbus_fall, NULL,
427 ab8500_usb_v1x_vbus_fall_irq,
428 IRQF_NO_SUSPEND | IRQF_SHARED,
429 "usb-vbus-fall", ab);
430 if (err < 0) {
431 dev_err(ab->dev, "request_irq failed for Vbus fall irq\n");
432 goto fail3;
433 }
434
435 return 0;
436fail3:
437 free_irq(ab->irq_num_vbus_rise, ab);
438fail2:
439 free_irq(ab->irq_num_id_fall, ab);
440fail1:
441 free_irq(ab->irq_num_id_rise, ab);
442fail0:
443 return err;
444}
445
446static int ab8500_usb_v2_res_setup(struct platform_device *pdev,
447 struct ab8500_usb *ab)
448{
449 int err;
450
451 ab->irq_num_link_status = platform_get_irq_byname(pdev,
452 "USB_LINK_STATUS");
453 if (ab->irq_num_link_status < 0) {
454 dev_err(&pdev->dev, "Link status irq not found\n");
455 return ab->irq_num_link_status;
456 }
457
458 err = request_threaded_irq(ab->irq_num_link_status, NULL,
459 ab8500_usb_v20_irq,
460 IRQF_NO_SUSPEND | IRQF_SHARED,
461 "usb-link-status", ab);
462 if (err < 0) {
463 dev_err(ab->dev,
464 "request_irq failed for link status irq\n");
465 return err;
466 }
467
468 return 0;
469}
470
471static int ab8500_usb_probe(struct platform_device *pdev)
472{
473 struct ab8500_usb *ab;
474 struct usb_otg *otg;
475 int err;
476 int rev;
477
478 rev = abx500_get_chip_id(&pdev->dev);
479 if (rev < 0) {
480 dev_err(&pdev->dev, "Chip id read failed\n");
481 return rev;
482 } else if (rev < 0x10) {
483 dev_err(&pdev->dev, "Unsupported AB8500 chip\n");
484 return -ENODEV;
485 }
486
487 ab = kzalloc(sizeof *ab, GFP_KERNEL);
488 if (!ab)
489 return -ENOMEM;
490
491 otg = kzalloc(sizeof *otg, GFP_KERNEL);
492 if (!otg) {
493 kfree(ab);
494 return -ENOMEM;
495 }
496
497 ab->dev = &pdev->dev;
498 ab->rev = rev;
499 ab->phy.dev = ab->dev;
500 ab->phy.otg = otg;
501 ab->phy.label = "ab8500";
502 ab->phy.set_suspend = ab8500_usb_set_suspend;
503 ab->phy.set_power = ab8500_usb_set_power;
504 ab->phy.state = OTG_STATE_UNDEFINED;
505
506 otg->phy = &ab->phy;
507 otg->set_host = ab8500_usb_set_host;
508 otg->set_peripheral = ab8500_usb_set_peripheral;
509
510 platform_set_drvdata(pdev, ab);
511
512 ATOMIC_INIT_NOTIFIER_HEAD(&ab->phy.notifier);
513
514 /* v1: Wait for link status to become stable.
515 * all: Updates form set_host and set_peripheral as they are atomic.
516 */
517 INIT_DELAYED_WORK(&ab->dwork, ab8500_usb_delayed_work);
518
519 /* all: Disable phy when called from set_host and set_peripheral */
520 INIT_WORK(&ab->phy_dis_work, ab8500_usb_phy_disable_work);
521
522 if (ab->rev < 0x20) {
523 err = ab8500_usb_v1x_res_setup(pdev, ab);
524 ab->link_status_wait = AB8500_V1x_LINK_STAT_WAIT;
525 } else {
526 err = ab8500_usb_v2_res_setup(pdev, ab);
527 }
528
529 if (err < 0)
530 goto fail0;
531
532 err = usb_add_phy(&ab->phy, USB_PHY_TYPE_USB2);
533 if (err) {
534 dev_err(&pdev->dev, "Can't register transceiver\n");
535 goto fail1;
536 }
537
538 dev_info(&pdev->dev, "AB8500 usb driver initialized\n");
539
540 return 0;
541fail1:
542 ab8500_usb_irq_free(ab);
543fail0:
544 kfree(otg);
545 kfree(ab);
546 return err;
547}
548
549static int ab8500_usb_remove(struct platform_device *pdev)
550{
551 struct ab8500_usb *ab = platform_get_drvdata(pdev);
552
553 ab8500_usb_irq_free(ab);
554
555 cancel_delayed_work_sync(&ab->dwork);
556
557 cancel_work_sync(&ab->phy_dis_work);
558
559 usb_remove_phy(&ab->phy);
560
561 ab8500_usb_host_phy_dis(ab);
562 ab8500_usb_peri_phy_dis(ab);
563
564 platform_set_drvdata(pdev, NULL);
565
566 kfree(ab->phy.otg);
567 kfree(ab);
568
569 return 0;
570}
571
572static struct platform_driver ab8500_usb_driver = {
573 .probe = ab8500_usb_probe,
574 .remove = ab8500_usb_remove,
575 .driver = {
576 .name = "ab8500-usb",
577 .owner = THIS_MODULE,
578 },
579};
580
581static int __init ab8500_usb_init(void)
582{
583 return platform_driver_register(&ab8500_usb_driver);
584}
585subsys_initcall(ab8500_usb_init);
586
587static void __exit ab8500_usb_exit(void)
588{
589 platform_driver_unregister(&ab8500_usb_driver);
590}
591module_exit(ab8500_usb_exit);
592
593MODULE_ALIAS("platform:ab8500_usb");
594MODULE_AUTHOR("ST-Ericsson AB");
595MODULE_DESCRIPTION("AB8500 usb transceiver driver");
596MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/fsl_otg.c b/drivers/usb/phy/fsl_otg.c
new file mode 100644
index 000000000000..72a2a00c2487
--- /dev/null
+++ b/drivers/usb/phy/fsl_otg.c
@@ -0,0 +1,1173 @@
1/*
2 * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
3 *
4 * Author: Li Yang <LeoLi@freescale.com>
5 * Jerry Huang <Chang-Ming.Huang@freescale.com>
6 *
7 * Initialization based on code from Shlomi Gridish.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28#include <linux/proc_fs.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/timer.h>
34#include <linux/usb.h>
35#include <linux/device.h>
36#include <linux/usb/ch9.h>
37#include <linux/usb/gadget.h>
38#include <linux/workqueue.h>
39#include <linux/time.h>
40#include <linux/fsl_devices.h>
41#include <linux/platform_device.h>
42#include <linux/uaccess.h>
43
44#include <asm/unaligned.h>
45
46#include "fsl_otg.h"
47
48#define DRIVER_VERSION "Rev. 1.55"
49#define DRIVER_AUTHOR "Jerry Huang/Li Yang"
50#define DRIVER_DESC "Freescale USB OTG Transceiver Driver"
51#define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
52
53static const char driver_name[] = "fsl-usb2-otg";
54
55const pm_message_t otg_suspend_state = {
56 .event = 1,
57};
58
59#define HA_DATA_PULSE
60
61static struct usb_dr_mmap *usb_dr_regs;
62static struct fsl_otg *fsl_otg_dev;
63static int srp_wait_done;
64
65/* FSM timers */
66struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
67 *b_ase0_brst_tmr, *b_se0_srp_tmr;
68
69/* Driver specific timers */
70struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
71 *b_srp_wait_tmr, *a_wait_enum_tmr;
72
73static struct list_head active_timers;
74
75static struct fsl_otg_config fsl_otg_initdata = {
76 .otg_port = 1,
77};
78
79#ifdef CONFIG_PPC32
80static u32 _fsl_readl_be(const unsigned __iomem *p)
81{
82 return in_be32(p);
83}
84
85static u32 _fsl_readl_le(const unsigned __iomem *p)
86{
87 return in_le32(p);
88}
89
90static void _fsl_writel_be(u32 v, unsigned __iomem *p)
91{
92 out_be32(p, v);
93}
94
95static void _fsl_writel_le(u32 v, unsigned __iomem *p)
96{
97 out_le32(p, v);
98}
99
100static u32 (*_fsl_readl)(const unsigned __iomem *p);
101static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
102
103#define fsl_readl(p) (*_fsl_readl)((p))
104#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
105
106#else
107#define fsl_readl(addr) readl(addr)
108#define fsl_writel(val, addr) writel(val, addr)
109#endif /* CONFIG_PPC32 */
110
111/* Routines to access transceiver ULPI registers */
112u8 view_ulpi(u8 addr)
113{
114 u32 temp;
115
116 temp = 0x40000000 | (addr << 16);
117 fsl_writel(temp, &usb_dr_regs->ulpiview);
118 udelay(1000);
119 while (temp & 0x40)
120 temp = fsl_readl(&usb_dr_regs->ulpiview);
121 return (le32_to_cpu(temp) & 0x0000ff00) >> 8;
122}
123
124int write_ulpi(u8 addr, u8 data)
125{
126 u32 temp;
127
128 temp = 0x60000000 | (addr << 16) | data;
129 fsl_writel(temp, &usb_dr_regs->ulpiview);
130 return 0;
131}
132
133/* -------------------------------------------------------------*/
134/* Operations that will be called from OTG Finite State Machine */
135
136/* Charge vbus for vbus pulsing in SRP */
137void fsl_otg_chrg_vbus(int on)
138{
139 u32 tmp;
140
141 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
142
143 if (on)
144 /* stop discharging, start charging */
145 tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) |
146 OTGSC_CTRL_VBUS_CHARGE;
147 else
148 /* stop charging */
149 tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
150
151 fsl_writel(tmp, &usb_dr_regs->otgsc);
152}
153
154/* Discharge vbus through a resistor to ground */
155void fsl_otg_dischrg_vbus(int on)
156{
157 u32 tmp;
158
159 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
160
161 if (on)
162 /* stop charging, start discharging */
163 tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) |
164 OTGSC_CTRL_VBUS_DISCHARGE;
165 else
166 /* stop discharging */
167 tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
168
169 fsl_writel(tmp, &usb_dr_regs->otgsc);
170}
171
172/* A-device driver vbus, controlled through PP bit in PORTSC */
173void fsl_otg_drv_vbus(int on)
174{
175 u32 tmp;
176
177 if (on) {
178 tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS;
179 fsl_writel(tmp | PORTSC_PORT_POWER, &usb_dr_regs->portsc);
180 } else {
181 tmp = fsl_readl(&usb_dr_regs->portsc) &
182 ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER;
183 fsl_writel(tmp, &usb_dr_regs->portsc);
184 }
185}
186
187/*
188 * Pull-up D+, signalling connect by periperal. Also used in
189 * data-line pulsing in SRP
190 */
191void fsl_otg_loc_conn(int on)
192{
193 u32 tmp;
194
195 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
196
197 if (on)
198 tmp |= OTGSC_CTRL_DATA_PULSING;
199 else
200 tmp &= ~OTGSC_CTRL_DATA_PULSING;
201
202 fsl_writel(tmp, &usb_dr_regs->otgsc);
203}
204
205/*
206 * Generate SOF by host. This is controlled through suspend/resume the
207 * port. In host mode, controller will automatically send SOF.
208 * Suspend will block the data on the port.
209 */
210void fsl_otg_loc_sof(int on)
211{
212 u32 tmp;
213
214 tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
215 if (on)
216 tmp |= PORTSC_PORT_FORCE_RESUME;
217 else
218 tmp |= PORTSC_PORT_SUSPEND;
219
220 fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc);
221
222}
223
224/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
225void fsl_otg_start_pulse(void)
226{
227 u32 tmp;
228
229 srp_wait_done = 0;
230#ifdef HA_DATA_PULSE
231 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
232 tmp |= OTGSC_HA_DATA_PULSE;
233 fsl_writel(tmp, &usb_dr_regs->otgsc);
234#else
235 fsl_otg_loc_conn(1);
236#endif
237
238 fsl_otg_add_timer(b_data_pulse_tmr);
239}
240
241void b_data_pulse_end(unsigned long foo)
242{
243#ifdef HA_DATA_PULSE
244#else
245 fsl_otg_loc_conn(0);
246#endif
247
248 /* Do VBUS pulse after data pulse */
249 fsl_otg_pulse_vbus();
250}
251
252void fsl_otg_pulse_vbus(void)
253{
254 srp_wait_done = 0;
255 fsl_otg_chrg_vbus(1);
256 /* start the timer to end vbus charge */
257 fsl_otg_add_timer(b_vbus_pulse_tmr);
258}
259
260void b_vbus_pulse_end(unsigned long foo)
261{
262 fsl_otg_chrg_vbus(0);
263
264 /*
265 * As USB3300 using the same a_sess_vld and b_sess_vld voltage
266 * we need to discharge the bus for a while to distinguish
267 * residual voltage of vbus pulsing and A device pull up
268 */
269 fsl_otg_dischrg_vbus(1);
270 fsl_otg_add_timer(b_srp_wait_tmr);
271}
272
273void b_srp_end(unsigned long foo)
274{
275 fsl_otg_dischrg_vbus(0);
276 srp_wait_done = 1;
277
278 if ((fsl_otg_dev->phy.state == OTG_STATE_B_SRP_INIT) &&
279 fsl_otg_dev->fsm.b_sess_vld)
280 fsl_otg_dev->fsm.b_srp_done = 1;
281}
282
283/*
284 * Workaround for a_host suspending too fast. When a_bus_req=0,
285 * a_host will start by SRP. It needs to set b_hnp_enable before
286 * actually suspending to start HNP
287 */
288void a_wait_enum(unsigned long foo)
289{
290 VDBG("a_wait_enum timeout\n");
291 if (!fsl_otg_dev->phy.otg->host->b_hnp_enable)
292 fsl_otg_add_timer(a_wait_enum_tmr);
293 else
294 otg_statemachine(&fsl_otg_dev->fsm);
295}
296
297/* The timeout callback function to set time out bit */
298void set_tmout(unsigned long indicator)
299{
300 *(int *)indicator = 1;
301}
302
303/* Initialize timers */
304int fsl_otg_init_timers(struct otg_fsm *fsm)
305{
306 /* FSM used timers */
307 a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
308 (unsigned long)&fsm->a_wait_vrise_tmout);
309 if (!a_wait_vrise_tmr)
310 return -ENOMEM;
311
312 a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
313 (unsigned long)&fsm->a_wait_bcon_tmout);
314 if (!a_wait_bcon_tmr)
315 return -ENOMEM;
316
317 a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
318 (unsigned long)&fsm->a_aidl_bdis_tmout);
319 if (!a_aidl_bdis_tmr)
320 return -ENOMEM;
321
322 b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
323 (unsigned long)&fsm->b_ase0_brst_tmout);
324 if (!b_ase0_brst_tmr)
325 return -ENOMEM;
326
327 b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
328 (unsigned long)&fsm->b_se0_srp);
329 if (!b_se0_srp_tmr)
330 return -ENOMEM;
331
332 b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
333 (unsigned long)&fsm->b_srp_done);
334 if (!b_srp_fail_tmr)
335 return -ENOMEM;
336
337 a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
338 (unsigned long)&fsm);
339 if (!a_wait_enum_tmr)
340 return -ENOMEM;
341
342 /* device driver used timers */
343 b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
344 if (!b_srp_wait_tmr)
345 return -ENOMEM;
346
347 b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
348 TB_DATA_PLS, 0);
349 if (!b_data_pulse_tmr)
350 return -ENOMEM;
351
352 b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
353 TB_VBUS_PLS, 0);
354 if (!b_vbus_pulse_tmr)
355 return -ENOMEM;
356
357 return 0;
358}
359
360/* Uninitialize timers */
361void fsl_otg_uninit_timers(void)
362{
363 /* FSM used timers */
364 kfree(a_wait_vrise_tmr);
365 kfree(a_wait_bcon_tmr);
366 kfree(a_aidl_bdis_tmr);
367 kfree(b_ase0_brst_tmr);
368 kfree(b_se0_srp_tmr);
369 kfree(b_srp_fail_tmr);
370 kfree(a_wait_enum_tmr);
371
372 /* device driver used timers */
373 kfree(b_srp_wait_tmr);
374 kfree(b_data_pulse_tmr);
375 kfree(b_vbus_pulse_tmr);
376}
377
378/* Add timer to timer list */
379void fsl_otg_add_timer(void *gtimer)
380{
381 struct fsl_otg_timer *timer = gtimer;
382 struct fsl_otg_timer *tmp_timer;
383
384 /*
385 * Check if the timer is already in the active list,
386 * if so update timer count
387 */
388 list_for_each_entry(tmp_timer, &active_timers, list)
389 if (tmp_timer == timer) {
390 timer->count = timer->expires;
391 return;
392 }
393 timer->count = timer->expires;
394 list_add_tail(&timer->list, &active_timers);
395}
396
397/* Remove timer from the timer list; clear timeout status */
398void fsl_otg_del_timer(void *gtimer)
399{
400 struct fsl_otg_timer *timer = gtimer;
401 struct fsl_otg_timer *tmp_timer, *del_tmp;
402
403 list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
404 if (tmp_timer == timer)
405 list_del(&timer->list);
406}
407
408/*
409 * Reduce timer count by 1, and find timeout conditions.
410 * Called by fsl_otg 1ms timer interrupt
411 */
412int fsl_otg_tick_timer(void)
413{
414 struct fsl_otg_timer *tmp_timer, *del_tmp;
415 int expired = 0;
416
417 list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
418 tmp_timer->count--;
419 /* check if timer expires */
420 if (!tmp_timer->count) {
421 list_del(&tmp_timer->list);
422 tmp_timer->function(tmp_timer->data);
423 expired = 1;
424 }
425 }
426
427 return expired;
428}
429
430/* Reset controller, not reset the bus */
431void otg_reset_controller(void)
432{
433 u32 command;
434
435 command = fsl_readl(&usb_dr_regs->usbcmd);
436 command |= (1 << 1);
437 fsl_writel(command, &usb_dr_regs->usbcmd);
438 while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
439 ;
440}
441
442/* Call suspend/resume routines in host driver */
443int fsl_otg_start_host(struct otg_fsm *fsm, int on)
444{
445 struct usb_otg *otg = fsm->otg;
446 struct device *dev;
447 struct fsl_otg *otg_dev = container_of(otg->phy, struct fsl_otg, phy);
448 u32 retval = 0;
449
450 if (!otg->host)
451 return -ENODEV;
452 dev = otg->host->controller;
453
454 /*
455 * Update a_vbus_vld state as a_vbus_vld int is disabled
456 * in device mode
457 */
458 fsm->a_vbus_vld =
459 !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
460 if (on) {
461 /* start fsl usb host controller */
462 if (otg_dev->host_working)
463 goto end;
464 else {
465 otg_reset_controller();
466 VDBG("host on......\n");
467 if (dev->driver->pm && dev->driver->pm->resume) {
468 retval = dev->driver->pm->resume(dev);
469 if (fsm->id) {
470 /* default-b */
471 fsl_otg_drv_vbus(1);
472 /*
473 * Workaround: b_host can't driver
474 * vbus, but PP in PORTSC needs to
475 * be 1 for host to work.
476 * So we set drv_vbus bit in
477 * transceiver to 0 thru ULPI.
478 */
479 write_ulpi(0x0c, 0x20);
480 }
481 }
482
483 otg_dev->host_working = 1;
484 }
485 } else {
486 /* stop fsl usb host controller */
487 if (!otg_dev->host_working)
488 goto end;
489 else {
490 VDBG("host off......\n");
491 if (dev && dev->driver) {
492 if (dev->driver->pm && dev->driver->pm->suspend)
493 retval = dev->driver->pm->suspend(dev);
494 if (fsm->id)
495 /* default-b */
496 fsl_otg_drv_vbus(0);
497 }
498 otg_dev->host_working = 0;
499 }
500 }
501end:
502 return retval;
503}
504
505/*
506 * Call suspend and resume function in udc driver
507 * to stop and start udc driver.
508 */
509int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
510{
511 struct usb_otg *otg = fsm->otg;
512 struct device *dev;
513
514 if (!otg->gadget || !otg->gadget->dev.parent)
515 return -ENODEV;
516
517 VDBG("gadget %s\n", on ? "on" : "off");
518 dev = otg->gadget->dev.parent;
519
520 if (on) {
521 if (dev->driver->resume)
522 dev->driver->resume(dev);
523 } else {
524 if (dev->driver->suspend)
525 dev->driver->suspend(dev, otg_suspend_state);
526 }
527
528 return 0;
529}
530
531/*
532 * Called by initialization code of host driver. Register host controller
533 * to the OTG. Suspend host for OTG role detection.
534 */
535static int fsl_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
536{
537 struct fsl_otg *otg_dev;
538
539 if (!otg)
540 return -ENODEV;
541
542 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
543 if (otg_dev != fsl_otg_dev)
544 return -ENODEV;
545
546 otg->host = host;
547
548 otg_dev->fsm.a_bus_drop = 0;
549 otg_dev->fsm.a_bus_req = 1;
550
551 if (host) {
552 VDBG("host off......\n");
553
554 otg->host->otg_port = fsl_otg_initdata.otg_port;
555 otg->host->is_b_host = otg_dev->fsm.id;
556 /*
557 * must leave time for khubd to finish its thing
558 * before yanking the host driver out from under it,
559 * so suspend the host after a short delay.
560 */
561 otg_dev->host_working = 1;
562 schedule_delayed_work(&otg_dev->otg_event, 100);
563 return 0;
564 } else {
565 /* host driver going away */
566 if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
567 OTGSC_STS_USB_ID)) {
568 /* Mini-A cable connected */
569 struct otg_fsm *fsm = &otg_dev->fsm;
570
571 otg->phy->state = OTG_STATE_UNDEFINED;
572 fsm->protocol = PROTO_UNDEF;
573 }
574 }
575
576 otg_dev->host_working = 0;
577
578 otg_statemachine(&otg_dev->fsm);
579
580 return 0;
581}
582
583/* Called by initialization code of udc. Register udc to OTG. */
584static int fsl_otg_set_peripheral(struct usb_otg *otg,
585 struct usb_gadget *gadget)
586{
587 struct fsl_otg *otg_dev;
588
589 if (!otg)
590 return -ENODEV;
591
592 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
593 VDBG("otg_dev 0x%x\n", (int)otg_dev);
594 VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
595 if (otg_dev != fsl_otg_dev)
596 return -ENODEV;
597
598 if (!gadget) {
599 if (!otg->default_a)
600 otg->gadget->ops->vbus_draw(otg->gadget, 0);
601 usb_gadget_vbus_disconnect(otg->gadget);
602 otg->gadget = 0;
603 otg_dev->fsm.b_bus_req = 0;
604 otg_statemachine(&otg_dev->fsm);
605 return 0;
606 }
607
608 otg->gadget = gadget;
609 otg->gadget->is_a_peripheral = !otg_dev->fsm.id;
610
611 otg_dev->fsm.b_bus_req = 1;
612
613 /* start the gadget right away if the ID pin says Mini-B */
614 DBG("ID pin=%d\n", otg_dev->fsm.id);
615 if (otg_dev->fsm.id == 1) {
616 fsl_otg_start_host(&otg_dev->fsm, 0);
617 otg_drv_vbus(&otg_dev->fsm, 0);
618 fsl_otg_start_gadget(&otg_dev->fsm, 1);
619 }
620
621 return 0;
622}
623
624/* Set OTG port power, only for B-device */
625static int fsl_otg_set_power(struct usb_phy *phy, unsigned mA)
626{
627 if (!fsl_otg_dev)
628 return -ENODEV;
629 if (phy->state == OTG_STATE_B_PERIPHERAL)
630 pr_info("FSL OTG: Draw %d mA\n", mA);
631
632 return 0;
633}
634
635/*
636 * Delayed pin detect interrupt processing.
637 *
638 * When the Mini-A cable is disconnected from the board,
639 * the pin-detect interrupt happens before the disconnect
640 * interrupts for the connected device(s). In order to
641 * process the disconnect interrupt(s) prior to switching
642 * roles, the pin-detect interrupts are delayed, and handled
643 * by this routine.
644 */
645static void fsl_otg_event(struct work_struct *work)
646{
647 struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
648 struct otg_fsm *fsm = &og->fsm;
649
650 if (fsm->id) { /* switch to gadget */
651 fsl_otg_start_host(fsm, 0);
652 otg_drv_vbus(fsm, 0);
653 fsl_otg_start_gadget(fsm, 1);
654 }
655}
656
657/* B-device start SRP */
658static int fsl_otg_start_srp(struct usb_otg *otg)
659{
660 struct fsl_otg *otg_dev;
661
662 if (!otg || otg->phy->state != OTG_STATE_B_IDLE)
663 return -ENODEV;
664
665 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
666 if (otg_dev != fsl_otg_dev)
667 return -ENODEV;
668
669 otg_dev->fsm.b_bus_req = 1;
670 otg_statemachine(&otg_dev->fsm);
671
672 return 0;
673}
674
675/* A_host suspend will call this function to start hnp */
676static int fsl_otg_start_hnp(struct usb_otg *otg)
677{
678 struct fsl_otg *otg_dev;
679
680 if (!otg)
681 return -ENODEV;
682
683 otg_dev = container_of(otg->phy, struct fsl_otg, phy);
684 if (otg_dev != fsl_otg_dev)
685 return -ENODEV;
686
687 DBG("start_hnp...n");
688
689 /* clear a_bus_req to enter a_suspend state */
690 otg_dev->fsm.a_bus_req = 0;
691 otg_statemachine(&otg_dev->fsm);
692
693 return 0;
694}
695
696/*
697 * Interrupt handler. OTG/host/peripheral share the same int line.
698 * OTG driver clears OTGSC interrupts and leaves USB interrupts
699 * intact. It needs to have knowledge of some USB interrupts
700 * such as port change.
701 */
702irqreturn_t fsl_otg_isr(int irq, void *dev_id)
703{
704 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
705 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
706 u32 otg_int_src, otg_sc;
707
708 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
709 otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
710
711 /* Only clear otg interrupts */
712 fsl_writel(otg_sc, &usb_dr_regs->otgsc);
713
714 /*FIXME: ID change not generate when init to 0 */
715 fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
716 otg->default_a = (fsm->id == 0);
717
718 /* process OTG interrupts */
719 if (otg_int_src) {
720 if (otg_int_src & OTGSC_INTSTS_USB_ID) {
721 fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
722 otg->default_a = (fsm->id == 0);
723 /* clear conn information */
724 if (fsm->id)
725 fsm->b_conn = 0;
726 else
727 fsm->a_conn = 0;
728
729 if (otg->host)
730 otg->host->is_b_host = fsm->id;
731 if (otg->gadget)
732 otg->gadget->is_a_peripheral = !fsm->id;
733 VDBG("ID int (ID is %d)\n", fsm->id);
734
735 if (fsm->id) { /* switch to gadget */
736 schedule_delayed_work(
737 &((struct fsl_otg *)dev_id)->otg_event,
738 100);
739 } else { /* switch to host */
740 cancel_delayed_work(&
741 ((struct fsl_otg *)dev_id)->
742 otg_event);
743 fsl_otg_start_gadget(fsm, 0);
744 otg_drv_vbus(fsm, 1);
745 fsl_otg_start_host(fsm, 1);
746 }
747 return IRQ_HANDLED;
748 }
749 }
750 return IRQ_NONE;
751}
752
753static struct otg_fsm_ops fsl_otg_ops = {
754 .chrg_vbus = fsl_otg_chrg_vbus,
755 .drv_vbus = fsl_otg_drv_vbus,
756 .loc_conn = fsl_otg_loc_conn,
757 .loc_sof = fsl_otg_loc_sof,
758 .start_pulse = fsl_otg_start_pulse,
759
760 .add_timer = fsl_otg_add_timer,
761 .del_timer = fsl_otg_del_timer,
762
763 .start_host = fsl_otg_start_host,
764 .start_gadget = fsl_otg_start_gadget,
765};
766
767/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
768static int fsl_otg_conf(struct platform_device *pdev)
769{
770 struct fsl_otg *fsl_otg_tc;
771 int status;
772
773 if (fsl_otg_dev)
774 return 0;
775
776 /* allocate space to fsl otg device */
777 fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
778 if (!fsl_otg_tc)
779 return -ENOMEM;
780
781 fsl_otg_tc->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
782 if (!fsl_otg_tc->phy.otg) {
783 kfree(fsl_otg_tc);
784 return -ENOMEM;
785 }
786
787 INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
788
789 INIT_LIST_HEAD(&active_timers);
790 status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
791 if (status) {
792 pr_info("Couldn't init OTG timers\n");
793 goto err;
794 }
795 spin_lock_init(&fsl_otg_tc->fsm.lock);
796
797 /* Set OTG state machine operations */
798 fsl_otg_tc->fsm.ops = &fsl_otg_ops;
799
800 /* initialize the otg structure */
801 fsl_otg_tc->phy.label = DRIVER_DESC;
802 fsl_otg_tc->phy.set_power = fsl_otg_set_power;
803
804 fsl_otg_tc->phy.otg->phy = &fsl_otg_tc->phy;
805 fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host;
806 fsl_otg_tc->phy.otg->set_peripheral = fsl_otg_set_peripheral;
807 fsl_otg_tc->phy.otg->start_hnp = fsl_otg_start_hnp;
808 fsl_otg_tc->phy.otg->start_srp = fsl_otg_start_srp;
809
810 fsl_otg_dev = fsl_otg_tc;
811
812 /* Store the otg transceiver */
813 status = usb_add_phy(&fsl_otg_tc->phy, USB_PHY_TYPE_USB2);
814 if (status) {
815 pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n");
816 goto err;
817 }
818
819 return 0;
820err:
821 fsl_otg_uninit_timers();
822 kfree(fsl_otg_tc->phy.otg);
823 kfree(fsl_otg_tc);
824 return status;
825}
826
827/* OTG Initialization */
828int usb_otg_start(struct platform_device *pdev)
829{
830 struct fsl_otg *p_otg;
831 struct usb_phy *otg_trans = usb_get_phy(USB_PHY_TYPE_USB2);
832 struct otg_fsm *fsm;
833 int status;
834 struct resource *res;
835 u32 temp;
836 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
837
838 p_otg = container_of(otg_trans, struct fsl_otg, phy);
839 fsm = &p_otg->fsm;
840
841 /* Initialize the state machine structure with default values */
842 SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
843 fsm->otg = p_otg->phy.otg;
844
845 /* We don't require predefined MEM/IRQ resource index */
846 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847 if (!res)
848 return -ENXIO;
849
850 /* We don't request_mem_region here to enable resource sharing
851 * with host/device */
852
853 usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
854 p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
855 pdata->regs = (void *)usb_dr_regs;
856
857 if (pdata->init && pdata->init(pdev) != 0)
858 return -EINVAL;
859
860 if (pdata->big_endian_mmio) {
861 _fsl_readl = _fsl_readl_be;
862 _fsl_writel = _fsl_writel_be;
863 } else {
864 _fsl_readl = _fsl_readl_le;
865 _fsl_writel = _fsl_writel_le;
866 }
867
868 /* request irq */
869 p_otg->irq = platform_get_irq(pdev, 0);
870 status = request_irq(p_otg->irq, fsl_otg_isr,
871 IRQF_SHARED, driver_name, p_otg);
872 if (status) {
873 dev_dbg(p_otg->phy.dev, "can't get IRQ %d, error %d\n",
874 p_otg->irq, status);
875 iounmap(p_otg->dr_mem_map);
876 kfree(p_otg->phy.otg);
877 kfree(p_otg);
878 return status;
879 }
880
881 /* stop the controller */
882 temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
883 temp &= ~USB_CMD_RUN_STOP;
884 fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
885
886 /* reset the controller */
887 temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
888 temp |= USB_CMD_CTRL_RESET;
889 fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
890
891 /* wait reset completed */
892 while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
893 ;
894
895 /* configure the VBUSHS as IDLE(both host and device) */
896 temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
897 fsl_writel(temp, &p_otg->dr_mem_map->usbmode);
898
899 /* configure PHY interface */
900 temp = fsl_readl(&p_otg->dr_mem_map->portsc);
901 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
902 switch (pdata->phy_mode) {
903 case FSL_USB2_PHY_ULPI:
904 temp |= PORTSC_PTS_ULPI;
905 break;
906 case FSL_USB2_PHY_UTMI_WIDE:
907 temp |= PORTSC_PTW_16BIT;
908 /* fall through */
909 case FSL_USB2_PHY_UTMI:
910 temp |= PORTSC_PTS_UTMI;
911 /* fall through */
912 default:
913 break;
914 }
915 fsl_writel(temp, &p_otg->dr_mem_map->portsc);
916
917 if (pdata->have_sysif_regs) {
918 /* configure control enable IO output, big endian register */
919 temp = __raw_readl(&p_otg->dr_mem_map->control);
920 temp |= USB_CTRL_IOENB;
921 __raw_writel(temp, &p_otg->dr_mem_map->control);
922 }
923
924 /* disable all interrupt and clear all OTGSC status */
925 temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
926 temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
927 temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
928 fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
929
930 /*
931 * The identification (id) input is FALSE when a Mini-A plug is inserted
932 * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
933 * Also: record initial state of ID pin
934 */
935 if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
936 p_otg->phy.state = OTG_STATE_UNDEFINED;
937 p_otg->fsm.id = 1;
938 } else {
939 p_otg->phy.state = OTG_STATE_A_IDLE;
940 p_otg->fsm.id = 0;
941 }
942
943 DBG("initial ID pin=%d\n", p_otg->fsm.id);
944
945 /* enable OTG ID pin interrupt */
946 temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
947 temp |= OTGSC_INTR_USB_ID_EN;
948 temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
949 fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
950
951 return 0;
952}
953
954/*
955 * state file in sysfs
956 */
957static int show_fsl_usb2_otg_state(struct device *dev,
958 struct device_attribute *attr, char *buf)
959{
960 struct otg_fsm *fsm = &fsl_otg_dev->fsm;
961 char *next = buf;
962 unsigned size = PAGE_SIZE;
963 unsigned long flags;
964 int t;
965
966 spin_lock_irqsave(&fsm->lock, flags);
967
968 /* basic driver infomation */
969 t = scnprintf(next, size,
970 DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
971 DRIVER_VERSION);
972 size -= t;
973 next += t;
974
975 /* Registers */
976 t = scnprintf(next, size,
977 "OTGSC: 0x%08x\n"
978 "PORTSC: 0x%08x\n"
979 "USBMODE: 0x%08x\n"
980 "USBCMD: 0x%08x\n"
981 "USBSTS: 0x%08x\n"
982 "USBINTR: 0x%08x\n",
983 fsl_readl(&usb_dr_regs->otgsc),
984 fsl_readl(&usb_dr_regs->portsc),
985 fsl_readl(&usb_dr_regs->usbmode),
986 fsl_readl(&usb_dr_regs->usbcmd),
987 fsl_readl(&usb_dr_regs->usbsts),
988 fsl_readl(&usb_dr_regs->usbintr));
989 size -= t;
990 next += t;
991
992 /* State */
993 t = scnprintf(next, size,
994 "OTG state: %s\n\n",
995 usb_otg_state_string(fsl_otg_dev->phy.state));
996 size -= t;
997 next += t;
998
999 /* State Machine Variables */
1000 t = scnprintf(next, size,
1001 "a_bus_req: %d\n"
1002 "b_bus_req: %d\n"
1003 "a_bus_resume: %d\n"
1004 "a_bus_suspend: %d\n"
1005 "a_conn: %d\n"
1006 "a_sess_vld: %d\n"
1007 "a_srp_det: %d\n"
1008 "a_vbus_vld: %d\n"
1009 "b_bus_resume: %d\n"
1010 "b_bus_suspend: %d\n"
1011 "b_conn: %d\n"
1012 "b_se0_srp: %d\n"
1013 "b_sess_end: %d\n"
1014 "b_sess_vld: %d\n"
1015 "id: %d\n",
1016 fsm->a_bus_req,
1017 fsm->b_bus_req,
1018 fsm->a_bus_resume,
1019 fsm->a_bus_suspend,
1020 fsm->a_conn,
1021 fsm->a_sess_vld,
1022 fsm->a_srp_det,
1023 fsm->a_vbus_vld,
1024 fsm->b_bus_resume,
1025 fsm->b_bus_suspend,
1026 fsm->b_conn,
1027 fsm->b_se0_srp,
1028 fsm->b_sess_end,
1029 fsm->b_sess_vld,
1030 fsm->id);
1031 size -= t;
1032 next += t;
1033
1034 spin_unlock_irqrestore(&fsm->lock, flags);
1035
1036 return PAGE_SIZE - size;
1037}
1038
1039static DEVICE_ATTR(fsl_usb2_otg_state, S_IRUGO, show_fsl_usb2_otg_state, NULL);
1040
1041
1042/* Char driver interface to control some OTG input */
1043
1044/*
1045 * Handle some ioctl command, such as get otg
1046 * status and set host suspend
1047 */
1048static long fsl_otg_ioctl(struct file *file, unsigned int cmd,
1049 unsigned long arg)
1050{
1051 u32 retval = 0;
1052
1053 switch (cmd) {
1054 case GET_OTG_STATUS:
1055 retval = fsl_otg_dev->host_working;
1056 break;
1057
1058 case SET_A_SUSPEND_REQ:
1059 fsl_otg_dev->fsm.a_suspend_req = arg;
1060 break;
1061
1062 case SET_A_BUS_DROP:
1063 fsl_otg_dev->fsm.a_bus_drop = arg;
1064 break;
1065
1066 case SET_A_BUS_REQ:
1067 fsl_otg_dev->fsm.a_bus_req = arg;
1068 break;
1069
1070 case SET_B_BUS_REQ:
1071 fsl_otg_dev->fsm.b_bus_req = arg;
1072 break;
1073
1074 default:
1075 break;
1076 }
1077
1078 otg_statemachine(&fsl_otg_dev->fsm);
1079
1080 return retval;
1081}
1082
1083static int fsl_otg_open(struct inode *inode, struct file *file)
1084{
1085 return 0;
1086}
1087
1088static int fsl_otg_release(struct inode *inode, struct file *file)
1089{
1090 return 0;
1091}
1092
1093static const struct file_operations otg_fops = {
1094 .owner = THIS_MODULE,
1095 .llseek = NULL,
1096 .read = NULL,
1097 .write = NULL,
1098 .unlocked_ioctl = fsl_otg_ioctl,
1099 .open = fsl_otg_open,
1100 .release = fsl_otg_release,
1101};
1102
1103static int fsl_otg_probe(struct platform_device *pdev)
1104{
1105 int ret;
1106
1107 if (!pdev->dev.platform_data)
1108 return -ENODEV;
1109
1110 /* configure the OTG */
1111 ret = fsl_otg_conf(pdev);
1112 if (ret) {
1113 dev_err(&pdev->dev, "Couldn't configure OTG module\n");
1114 return ret;
1115 }
1116
1117 /* start OTG */
1118 ret = usb_otg_start(pdev);
1119 if (ret) {
1120 dev_err(&pdev->dev, "Can't init FSL OTG device\n");
1121 return ret;
1122 }
1123
1124 ret = register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops);
1125 if (ret) {
1126 dev_err(&pdev->dev, "unable to register FSL OTG device\n");
1127 return ret;
1128 }
1129
1130 ret = device_create_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
1131 if (ret)
1132 dev_warn(&pdev->dev, "Can't register sysfs attribute\n");
1133
1134 return ret;
1135}
1136
1137static int fsl_otg_remove(struct platform_device *pdev)
1138{
1139 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
1140
1141 usb_remove_phy(&fsl_otg_dev->phy);
1142 free_irq(fsl_otg_dev->irq, fsl_otg_dev);
1143
1144 iounmap((void *)usb_dr_regs);
1145
1146 fsl_otg_uninit_timers();
1147 kfree(fsl_otg_dev->phy.otg);
1148 kfree(fsl_otg_dev);
1149
1150 device_remove_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
1151
1152 unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
1153
1154 if (pdata->exit)
1155 pdata->exit(pdev);
1156
1157 return 0;
1158}
1159
1160struct platform_driver fsl_otg_driver = {
1161 .probe = fsl_otg_probe,
1162 .remove = fsl_otg_remove,
1163 .driver = {
1164 .name = driver_name,
1165 .owner = THIS_MODULE,
1166 },
1167};
1168
1169module_platform_driver(fsl_otg_driver);
1170
1171MODULE_DESCRIPTION(DRIVER_INFO);
1172MODULE_AUTHOR(DRIVER_AUTHOR);
1173MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/fsl_otg.h b/drivers/usb/phy/fsl_otg.h
new file mode 100644
index 000000000000..ca266280895d
--- /dev/null
+++ b/drivers/usb/phy/fsl_otg.h
@@ -0,0 +1,406 @@
1/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify it
4 * under the terms of the GNU General Public License as published by the
5 * Free Software Foundation; either version 2 of the License, or (at your
6 * option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 */
17
18#include "otg_fsm.h"
19#include <linux/usb/otg.h>
20#include <linux/ioctl.h>
21
22/* USB Command Register Bit Masks */
23#define USB_CMD_RUN_STOP (0x1<<0)
24#define USB_CMD_CTRL_RESET (0x1<<1)
25#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4)
26#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5)
27#define USB_CMD_INT_AA_DOORBELL (0x1<<6)
28#define USB_CMD_ASP (0x3<<8)
29#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11)
30#define USB_CMD_SUTW (0x1<<13)
31#define USB_CMD_ATDTW (0x1<<14)
32#define USB_CMD_ITC (0xFF<<16)
33
34/* bit 15,3,2 are frame list size */
35#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2)
36#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2)
37#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2)
38#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2)
39#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2)
40#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2)
41#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2)
42#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2)
43
44/* bit 9-8 are async schedule park mode count */
45#define USB_CMD_ASP_00 (0x0<<8)
46#define USB_CMD_ASP_01 (0x1<<8)
47#define USB_CMD_ASP_10 (0x2<<8)
48#define USB_CMD_ASP_11 (0x3<<8)
49#define USB_CMD_ASP_BIT_POS (8)
50
51/* bit 23-16 are interrupt threshold control */
52#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16)
53#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16)
54#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16)
55#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16)
56#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16)
57#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16)
58#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16)
59#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16)
60#define USB_CMD_ITC_BIT_POS (16)
61
62/* USB Status Register Bit Masks */
63#define USB_STS_INT (0x1<<0)
64#define USB_STS_ERR (0x1<<1)
65#define USB_STS_PORT_CHANGE (0x1<<2)
66#define USB_STS_FRM_LST_ROLL (0x1<<3)
67#define USB_STS_SYS_ERR (0x1<<4)
68#define USB_STS_IAA (0x1<<5)
69#define USB_STS_RESET_RECEIVED (0x1<<6)
70#define USB_STS_SOF (0x1<<7)
71#define USB_STS_DCSUSPEND (0x1<<8)
72#define USB_STS_HC_HALTED (0x1<<12)
73#define USB_STS_RCL (0x1<<13)
74#define USB_STS_PERIODIC_SCHEDULE (0x1<<14)
75#define USB_STS_ASYNC_SCHEDULE (0x1<<15)
76
77/* USB Interrupt Enable Register Bit Masks */
78#define USB_INTR_INT_EN (0x1<<0)
79#define USB_INTR_ERR_INT_EN (0x1<<1)
80#define USB_INTR_PC_DETECT_EN (0x1<<2)
81#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3)
82#define USB_INTR_SYS_ERR_EN (0x1<<4)
83#define USB_INTR_ASYN_ADV_EN (0x1<<5)
84#define USB_INTR_RESET_EN (0x1<<6)
85#define USB_INTR_SOF_EN (0x1<<7)
86#define USB_INTR_DEVICE_SUSPEND (0x1<<8)
87
88/* Device Address bit masks */
89#define USB_DEVICE_ADDRESS_MASK (0x7F<<25)
90#define USB_DEVICE_ADDRESS_BIT_POS (25)
91/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
92#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0)
93#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1)
94#define PORTSC_PORT_ENABLE (0x1<<2)
95#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3)
96#define PORTSC_OVER_CURRENT_ACT (0x1<<4)
97#define PORTSC_OVER_CUURENT_CHG (0x1<<5)
98#define PORTSC_PORT_FORCE_RESUME (0x1<<6)
99#define PORTSC_PORT_SUSPEND (0x1<<7)
100#define PORTSC_PORT_RESET (0x1<<8)
101#define PORTSC_LINE_STATUS_BITS (0x3<<10)
102#define PORTSC_PORT_POWER (0x1<<12)
103#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14)
104#define PORTSC_PORT_TEST_CTRL (0xF<<16)
105#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20)
106#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21)
107#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
108#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23)
109#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24)
110#define PORTSC_PORT_SPEED_MASK (0x3<<26)
111#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28)
112#define PORTSC_PHY_TYPE_SEL (0x3<<30)
113/* bit 11-10 are line status */
114#define PORTSC_LINE_STATUS_SE0 (0x0<<10)
115#define PORTSC_LINE_STATUS_JSTATE (0x1<<10)
116#define PORTSC_LINE_STATUS_KSTATE (0x2<<10)
117#define PORTSC_LINE_STATUS_UNDEF (0x3<<10)
118#define PORTSC_LINE_STATUS_BIT_POS (10)
119
120/* bit 15-14 are port indicator control */
121#define PORTSC_PIC_OFF (0x0<<14)
122#define PORTSC_PIC_AMBER (0x1<<14)
123#define PORTSC_PIC_GREEN (0x2<<14)
124#define PORTSC_PIC_UNDEF (0x3<<14)
125#define PORTSC_PIC_BIT_POS (14)
126
127/* bit 19-16 are port test control */
128#define PORTSC_PTC_DISABLE (0x0<<16)
129#define PORTSC_PTC_JSTATE (0x1<<16)
130#define PORTSC_PTC_KSTATE (0x2<<16)
131#define PORTSC_PTC_SEQNAK (0x3<<16)
132#define PORTSC_PTC_PACKET (0x4<<16)
133#define PORTSC_PTC_FORCE_EN (0x5<<16)
134#define PORTSC_PTC_BIT_POS (16)
135
136/* bit 27-26 are port speed */
137#define PORTSC_PORT_SPEED_FULL (0x0<<26)
138#define PORTSC_PORT_SPEED_LOW (0x1<<26)
139#define PORTSC_PORT_SPEED_HIGH (0x2<<26)
140#define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
141#define PORTSC_SPEED_BIT_POS (26)
142
143/* bit 28 is parallel transceiver width for UTMI interface */
144#define PORTSC_PTW (0x1<<28)
145#define PORTSC_PTW_8BIT (0x0<<28)
146#define PORTSC_PTW_16BIT (0x1<<28)
147
148/* bit 31-30 are port transceiver select */
149#define PORTSC_PTS_UTMI (0x0<<30)
150#define PORTSC_PTS_ULPI (0x2<<30)
151#define PORTSC_PTS_FSLS_SERIAL (0x3<<30)
152#define PORTSC_PTS_BIT_POS (30)
153
154#define PORTSC_W1C_BITS \
155 (PORTSC_CONNECT_STATUS_CHANGE | \
156 PORTSC_PORT_EN_DIS_CHANGE | \
157 PORTSC_OVER_CUURENT_CHG)
158
159/* OTG Status Control Register Bit Masks */
160#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0)
161#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1)
162#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3)
163#define OTGSC_CTRL_DATA_PULSING (0x1<<4)
164#define OTGSC_CTRL_ID_PULL_EN (0x1<<5)
165#define OTGSC_HA_DATA_PULSE (0x1<<6)
166#define OTGSC_HA_BA (0x1<<7)
167#define OTGSC_STS_USB_ID (0x1<<8)
168#define OTGSC_STS_A_VBUS_VALID (0x1<<9)
169#define OTGSC_STS_A_SESSION_VALID (0x1<<10)
170#define OTGSC_STS_B_SESSION_VALID (0x1<<11)
171#define OTGSC_STS_B_SESSION_END (0x1<<12)
172#define OTGSC_STS_1MS_TOGGLE (0x1<<13)
173#define OTGSC_STS_DATA_PULSING (0x1<<14)
174#define OTGSC_INTSTS_USB_ID (0x1<<16)
175#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17)
176#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18)
177#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19)
178#define OTGSC_INTSTS_B_SESSION_END (0x1<<20)
179#define OTGSC_INTSTS_1MS (0x1<<21)
180#define OTGSC_INTSTS_DATA_PULSING (0x1<<22)
181#define OTGSC_INTR_USB_ID_EN (0x1<<24)
182#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25)
183#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26)
184#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27)
185#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
186#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29)
187#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30)
188#define OTGSC_INTSTS_MASK (0x00ff0000)
189
190/* USB MODE Register Bit Masks */
191#define USB_MODE_CTRL_MODE_IDLE (0x0<<0)
192#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0)
193#define USB_MODE_CTRL_MODE_HOST (0x3<<0)
194#define USB_MODE_CTRL_MODE_RSV (0x1<<0)
195#define USB_MODE_SETUP_LOCK_OFF (0x1<<3)
196#define USB_MODE_STREAM_DISABLE (0x1<<4)
197#define USB_MODE_ES (0x1<<2) /* Endian Select */
198
199/* control Register Bit Masks */
200#define USB_CTRL_IOENB (0x1<<2)
201#define USB_CTRL_ULPI_INT0EN (0x1<<0)
202
203/* BCSR5 */
204#define BCSR5_INT_USB (0x02)
205
206/* USB module clk cfg */
207#define SCCR_OFFS (0xA08)
208#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */
209#define SCCR_USB_MPHCM_11 (0x00c00000)
210#define SCCR_USB_MPHCM_01 (0x00400000)
211#define SCCR_USB_MPHCM_10 (0x00800000)
212#define SCCR_USB_DRCM_11 (0x00300000)
213#define SCCR_USB_DRCM_01 (0x00100000)
214#define SCCR_USB_DRCM_10 (0x00200000)
215
216#define SICRL_OFFS (0x114)
217#define SICRL_USB0 (0x40000000)
218#define SICRL_USB1 (0x20000000)
219
220#define SICRH_OFFS (0x118)
221#define SICRH_USB_UTMI (0x00020000)
222
223/* OTG interrupt enable bit masks */
224#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \
225 (OTGSC_INTR_USB_ID_EN | \
226 OTGSC_INTR_1MS_TIMER_EN | \
227 OTGSC_INTR_A_VBUS_VALID_EN | \
228 OTGSC_INTR_A_SESSION_VALID_EN | \
229 OTGSC_INTR_B_SESSION_VALID_EN | \
230 OTGSC_INTR_B_SESSION_END_EN | \
231 OTGSC_INTR_DATA_PULSING_EN)
232
233/* OTG interrupt status bit masks */
234#define OTGSC_INTERRUPT_STATUS_BITS_MASK \
235 (OTGSC_INTSTS_USB_ID | \
236 OTGSC_INTR_1MS_TIMER_EN | \
237 OTGSC_INTSTS_A_VBUS_VALID | \
238 OTGSC_INTSTS_A_SESSION_VALID | \
239 OTGSC_INTSTS_B_SESSION_VALID | \
240 OTGSC_INTSTS_B_SESSION_END | \
241 OTGSC_INTSTS_DATA_PULSING)
242
243/*
244 * A-DEVICE timing constants
245 */
246
247/* Wait for VBUS Rise */
248#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
249
250/* Wait for B-Connect */
251#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
252 * This is only used to get out of
253 * OTG_STATE_A_WAIT_BCON state if there was
254 * no connection for these many milliseconds
255 */
256
257/* A-Idle to B-Disconnect */
258/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
259 * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
260 * in the test description
261 */
262#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
263
264/* B-Idle to A-Disconnect */
265#define TA_BIDL_ADIS (12) /* 3 to 200 ms */
266
267/* B-device timing constants */
268
269
270/* Data-Line Pulse Time*/
271#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
272#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
273#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
274
275/* SRP Initiate Time */
276#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
277
278/* SRP Fail Time */
279#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
280
281/* SRP result wait time */
282#define TB_SRP_WAIT (60)
283
284/* VBus time */
285#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
286
287/* Discharge time */
288/* This time should be less than 10ms. It varies from system to system. */
289#define TB_VBUS_DSCHRG (8)
290
291/* A-SE0 to B-Reset */
292#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
293
294/* A bus suspend timer before we can switch to b_wait_aconn */
295#define TB_A_SUSPEND (7)
296#define TB_BUS_RESUME (12)
297
298/* SE0 Time Before SRP */
299#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
300
301#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
302
303struct usb_dr_mmap {
304 /* Capability register */
305 u8 res1[256];
306 u16 caplength; /* Capability Register Length */
307 u16 hciversion; /* Host Controller Interface Version */
308 u32 hcsparams; /* Host Controller Structual Parameters */
309 u32 hccparams; /* Host Controller Capability Parameters */
310 u8 res2[20];
311 u32 dciversion; /* Device Controller Interface Version */
312 u32 dccparams; /* Device Controller Capability Parameters */
313 u8 res3[24];
314 /* Operation register */
315 u32 usbcmd; /* USB Command Register */
316 u32 usbsts; /* USB Status Register */
317 u32 usbintr; /* USB Interrupt Enable Register */
318 u32 frindex; /* Frame Index Register */
319 u8 res4[4];
320 u32 deviceaddr; /* Device Address */
321 u32 endpointlistaddr; /* Endpoint List Address Register */
322 u8 res5[4];
323 u32 burstsize; /* Master Interface Data Burst Size Register */
324 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
325 u8 res6[8];
326 u32 ulpiview; /* ULPI register access */
327 u8 res7[12];
328 u32 configflag; /* Configure Flag Register */
329 u32 portsc; /* Port 1 Status and Control Register */
330 u8 res8[28];
331 u32 otgsc; /* On-The-Go Status and Control */
332 u32 usbmode; /* USB Mode Register */
333 u32 endptsetupstat; /* Endpoint Setup Status Register */
334 u32 endpointprime; /* Endpoint Initialization Register */
335 u32 endptflush; /* Endpoint Flush Register */
336 u32 endptstatus; /* Endpoint Status Register */
337 u32 endptcomplete; /* Endpoint Complete Register */
338 u32 endptctrl[6]; /* Endpoint Control Registers */
339 u8 res9[552];
340 u32 snoop1;
341 u32 snoop2;
342 u32 age_cnt_thresh; /* Age Count Threshold Register */
343 u32 pri_ctrl; /* Priority Control Register */
344 u32 si_ctrl; /* System Interface Control Register */
345 u8 res10[236];
346 u32 control; /* General Purpose Control Register */
347};
348
349struct fsl_otg_timer {
350 unsigned long expires; /* Number of count increase to timeout */
351 unsigned long count; /* Tick counter */
352 void (*function)(unsigned long); /* Timeout function */
353 unsigned long data; /* Data passed to function */
354 struct list_head list;
355};
356
357inline struct fsl_otg_timer *otg_timer_initializer
358(void (*function)(unsigned long), unsigned long expires, unsigned long data)
359{
360 struct fsl_otg_timer *timer;
361
362 timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
363 if (!timer)
364 return NULL;
365 timer->function = function;
366 timer->expires = expires;
367 timer->data = data;
368 return timer;
369}
370
371struct fsl_otg {
372 struct usb_phy phy;
373 struct otg_fsm fsm;
374 struct usb_dr_mmap *dr_mem_map;
375 struct delayed_work otg_event;
376
377 /* used for usb host */
378 struct work_struct work_wq;
379 u8 host_working;
380
381 int irq;
382};
383
384struct fsl_otg_config {
385 u8 otg_port;
386};
387
388/* For SRP and HNP handle */
389#define FSL_OTG_MAJOR 240
390#define FSL_OTG_NAME "fsl-usb2-otg"
391/* Command to OTG driver ioctl */
392#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR
393/* if otg work as host, it should return 1, otherwise return 0 */
394#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int)
395#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int)
396#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int)
397#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int)
398#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int)
399#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int)
400#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int)
401#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
402#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
403
404void fsl_otg_add_timer(void *timer);
405void fsl_otg_del_timer(void *timer);
406void fsl_otg_pulse_vbus(void);
diff --git a/drivers/usb/phy/gpio_vbus.c b/drivers/usb/phy/gpio_vbus.c
new file mode 100644
index 000000000000..a7d4ac591982
--- /dev/null
+++ b/drivers/usb/phy/gpio_vbus.c
@@ -0,0 +1,416 @@
1/*
2 * gpio-vbus.c - simple GPIO VBUS sensing driver for B peripheral devices
3 *
4 * Copyright (c) 2008 Philipp Zabel <philipp.zabel@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/interrupt.h>
17#include <linux/usb.h>
18#include <linux/workqueue.h>
19
20#include <linux/regulator/consumer.h>
21
22#include <linux/usb/gadget.h>
23#include <linux/usb/gpio_vbus.h>
24#include <linux/usb/otg.h>
25
26
27/*
28 * A simple GPIO VBUS sensing driver for B peripheral only devices
29 * with internal transceivers. It can control a D+ pullup GPIO and
30 * a regulator to limit the current drawn from VBUS.
31 *
32 * Needs to be loaded before the UDC driver that will use it.
33 */
34struct gpio_vbus_data {
35 struct usb_phy phy;
36 struct device *dev;
37 struct regulator *vbus_draw;
38 int vbus_draw_enabled;
39 unsigned mA;
40 struct delayed_work work;
41 int vbus;
42 int irq;
43};
44
45
46/*
47 * This driver relies on "both edges" triggering. VBUS has 100 msec to
48 * stabilize, so the peripheral controller driver may need to cope with
49 * some bouncing due to current surges (e.g. charging local capacitance)
50 * and contact chatter.
51 *
52 * REVISIT in desperate straits, toggling between rising and falling
53 * edges might be workable.
54 */
55#define VBUS_IRQ_FLAGS \
56 (IRQF_SHARED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
57
58
59/* interface to regulator framework */
60static void set_vbus_draw(struct gpio_vbus_data *gpio_vbus, unsigned mA)
61{
62 struct regulator *vbus_draw = gpio_vbus->vbus_draw;
63 int enabled;
64
65 if (!vbus_draw)
66 return;
67
68 enabled = gpio_vbus->vbus_draw_enabled;
69 if (mA) {
70 regulator_set_current_limit(vbus_draw, 0, 1000 * mA);
71 if (!enabled) {
72 regulator_enable(vbus_draw);
73 gpio_vbus->vbus_draw_enabled = 1;
74 }
75 } else {
76 if (enabled) {
77 regulator_disable(vbus_draw);
78 gpio_vbus->vbus_draw_enabled = 0;
79 }
80 }
81 gpio_vbus->mA = mA;
82}
83
84static int is_vbus_powered(struct gpio_vbus_mach_info *pdata)
85{
86 int vbus;
87
88 vbus = gpio_get_value(pdata->gpio_vbus);
89 if (pdata->gpio_vbus_inverted)
90 vbus = !vbus;
91
92 return vbus;
93}
94
95static void gpio_vbus_work(struct work_struct *work)
96{
97 struct gpio_vbus_data *gpio_vbus =
98 container_of(work, struct gpio_vbus_data, work.work);
99 struct gpio_vbus_mach_info *pdata = gpio_vbus->dev->platform_data;
100 int gpio, status, vbus;
101
102 if (!gpio_vbus->phy.otg->gadget)
103 return;
104
105 vbus = is_vbus_powered(pdata);
106 if ((vbus ^ gpio_vbus->vbus) == 0)
107 return;
108 gpio_vbus->vbus = vbus;
109
110 /* Peripheral controllers which manage the pullup themselves won't have
111 * gpio_pullup configured here. If it's configured here, we'll do what
112 * isp1301_omap::b_peripheral() does and enable the pullup here... although
113 * that may complicate usb_gadget_{,dis}connect() support.
114 */
115 gpio = pdata->gpio_pullup;
116
117 if (vbus) {
118 status = USB_EVENT_VBUS;
119 gpio_vbus->phy.state = OTG_STATE_B_PERIPHERAL;
120 gpio_vbus->phy.last_event = status;
121 usb_gadget_vbus_connect(gpio_vbus->phy.otg->gadget);
122
123 /* drawing a "unit load" is *always* OK, except for OTG */
124 set_vbus_draw(gpio_vbus, 100);
125
126 /* optionally enable D+ pullup */
127 if (gpio_is_valid(gpio))
128 gpio_set_value(gpio, !pdata->gpio_pullup_inverted);
129
130 atomic_notifier_call_chain(&gpio_vbus->phy.notifier,
131 status, gpio_vbus->phy.otg->gadget);
132 } else {
133 /* optionally disable D+ pullup */
134 if (gpio_is_valid(gpio))
135 gpio_set_value(gpio, pdata->gpio_pullup_inverted);
136
137 set_vbus_draw(gpio_vbus, 0);
138
139 usb_gadget_vbus_disconnect(gpio_vbus->phy.otg->gadget);
140 status = USB_EVENT_NONE;
141 gpio_vbus->phy.state = OTG_STATE_B_IDLE;
142 gpio_vbus->phy.last_event = status;
143
144 atomic_notifier_call_chain(&gpio_vbus->phy.notifier,
145 status, gpio_vbus->phy.otg->gadget);
146 }
147}
148
149/* VBUS change IRQ handler */
150static irqreturn_t gpio_vbus_irq(int irq, void *data)
151{
152 struct platform_device *pdev = data;
153 struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
154 struct gpio_vbus_data *gpio_vbus = platform_get_drvdata(pdev);
155 struct usb_otg *otg = gpio_vbus->phy.otg;
156
157 dev_dbg(&pdev->dev, "VBUS %s (gadget: %s)\n",
158 is_vbus_powered(pdata) ? "supplied" : "inactive",
159 otg->gadget ? otg->gadget->name : "none");
160
161 if (otg->gadget)
162 schedule_delayed_work(&gpio_vbus->work, msecs_to_jiffies(100));
163
164 return IRQ_HANDLED;
165}
166
167/* OTG transceiver interface */
168
169/* bind/unbind the peripheral controller */
170static int gpio_vbus_set_peripheral(struct usb_otg *otg,
171 struct usb_gadget *gadget)
172{
173 struct gpio_vbus_data *gpio_vbus;
174 struct gpio_vbus_mach_info *pdata;
175 struct platform_device *pdev;
176 int gpio;
177
178 gpio_vbus = container_of(otg->phy, struct gpio_vbus_data, phy);
179 pdev = to_platform_device(gpio_vbus->dev);
180 pdata = gpio_vbus->dev->platform_data;
181 gpio = pdata->gpio_pullup;
182
183 if (!gadget) {
184 dev_dbg(&pdev->dev, "unregistering gadget '%s'\n",
185 otg->gadget->name);
186
187 /* optionally disable D+ pullup */
188 if (gpio_is_valid(gpio))
189 gpio_set_value(gpio, pdata->gpio_pullup_inverted);
190
191 set_vbus_draw(gpio_vbus, 0);
192
193 usb_gadget_vbus_disconnect(otg->gadget);
194 otg->phy->state = OTG_STATE_UNDEFINED;
195
196 otg->gadget = NULL;
197 return 0;
198 }
199
200 otg->gadget = gadget;
201 dev_dbg(&pdev->dev, "registered gadget '%s'\n", gadget->name);
202
203 /* initialize connection state */
204 gpio_vbus->vbus = 0; /* start with disconnected */
205 gpio_vbus_irq(gpio_vbus->irq, pdev);
206 return 0;
207}
208
209/* effective for B devices, ignored for A-peripheral */
210static int gpio_vbus_set_power(struct usb_phy *phy, unsigned mA)
211{
212 struct gpio_vbus_data *gpio_vbus;
213
214 gpio_vbus = container_of(phy, struct gpio_vbus_data, phy);
215
216 if (phy->state == OTG_STATE_B_PERIPHERAL)
217 set_vbus_draw(gpio_vbus, mA);
218 return 0;
219}
220
221/* for non-OTG B devices: set/clear transceiver suspend mode */
222static int gpio_vbus_set_suspend(struct usb_phy *phy, int suspend)
223{
224 struct gpio_vbus_data *gpio_vbus;
225
226 gpio_vbus = container_of(phy, struct gpio_vbus_data, phy);
227
228 /* draw max 0 mA from vbus in suspend mode; or the previously
229 * recorded amount of current if not suspended
230 *
231 * NOTE: high powered configs (mA > 100) may draw up to 2.5 mA
232 * if they're wake-enabled ... we don't handle that yet.
233 */
234 return gpio_vbus_set_power(phy, suspend ? 0 : gpio_vbus->mA);
235}
236
237/* platform driver interface */
238
239static int __init gpio_vbus_probe(struct platform_device *pdev)
240{
241 struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
242 struct gpio_vbus_data *gpio_vbus;
243 struct resource *res;
244 int err, gpio, irq;
245 unsigned long irqflags;
246
247 if (!pdata || !gpio_is_valid(pdata->gpio_vbus))
248 return -EINVAL;
249 gpio = pdata->gpio_vbus;
250
251 gpio_vbus = kzalloc(sizeof(struct gpio_vbus_data), GFP_KERNEL);
252 if (!gpio_vbus)
253 return -ENOMEM;
254
255 gpio_vbus->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
256 if (!gpio_vbus->phy.otg) {
257 kfree(gpio_vbus);
258 return -ENOMEM;
259 }
260
261 platform_set_drvdata(pdev, gpio_vbus);
262 gpio_vbus->dev = &pdev->dev;
263 gpio_vbus->phy.label = "gpio-vbus";
264 gpio_vbus->phy.set_power = gpio_vbus_set_power;
265 gpio_vbus->phy.set_suspend = gpio_vbus_set_suspend;
266 gpio_vbus->phy.state = OTG_STATE_UNDEFINED;
267
268 gpio_vbus->phy.otg->phy = &gpio_vbus->phy;
269 gpio_vbus->phy.otg->set_peripheral = gpio_vbus_set_peripheral;
270
271 err = gpio_request(gpio, "vbus_detect");
272 if (err) {
273 dev_err(&pdev->dev, "can't request vbus gpio %d, err: %d\n",
274 gpio, err);
275 goto err_gpio;
276 }
277 gpio_direction_input(gpio);
278
279 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
280 if (res) {
281 irq = res->start;
282 irqflags = (res->flags & IRQF_TRIGGER_MASK) | IRQF_SHARED;
283 } else {
284 irq = gpio_to_irq(gpio);
285 irqflags = VBUS_IRQ_FLAGS;
286 }
287
288 gpio_vbus->irq = irq;
289
290 /* if data line pullup is in use, initialize it to "not pulling up" */
291 gpio = pdata->gpio_pullup;
292 if (gpio_is_valid(gpio)) {
293 err = gpio_request(gpio, "udc_pullup");
294 if (err) {
295 dev_err(&pdev->dev,
296 "can't request pullup gpio %d, err: %d\n",
297 gpio, err);
298 gpio_free(pdata->gpio_vbus);
299 goto err_gpio;
300 }
301 gpio_direction_output(gpio, pdata->gpio_pullup_inverted);
302 }
303
304 err = request_irq(irq, gpio_vbus_irq, irqflags, "vbus_detect", pdev);
305 if (err) {
306 dev_err(&pdev->dev, "can't request irq %i, err: %d\n",
307 irq, err);
308 goto err_irq;
309 }
310
311 ATOMIC_INIT_NOTIFIER_HEAD(&gpio_vbus->phy.notifier);
312
313 INIT_DELAYED_WORK(&gpio_vbus->work, gpio_vbus_work);
314
315 gpio_vbus->vbus_draw = regulator_get(&pdev->dev, "vbus_draw");
316 if (IS_ERR(gpio_vbus->vbus_draw)) {
317 dev_dbg(&pdev->dev, "can't get vbus_draw regulator, err: %ld\n",
318 PTR_ERR(gpio_vbus->vbus_draw));
319 gpio_vbus->vbus_draw = NULL;
320 }
321
322 /* only active when a gadget is registered */
323 err = usb_add_phy(&gpio_vbus->phy, USB_PHY_TYPE_USB2);
324 if (err) {
325 dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
326 err);
327 goto err_otg;
328 }
329
330 device_init_wakeup(&pdev->dev, pdata->wakeup);
331
332 return 0;
333err_otg:
334 regulator_put(gpio_vbus->vbus_draw);
335 free_irq(irq, pdev);
336err_irq:
337 if (gpio_is_valid(pdata->gpio_pullup))
338 gpio_free(pdata->gpio_pullup);
339 gpio_free(pdata->gpio_vbus);
340err_gpio:
341 platform_set_drvdata(pdev, NULL);
342 kfree(gpio_vbus->phy.otg);
343 kfree(gpio_vbus);
344 return err;
345}
346
347static int __exit gpio_vbus_remove(struct platform_device *pdev)
348{
349 struct gpio_vbus_data *gpio_vbus = platform_get_drvdata(pdev);
350 struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
351 int gpio = pdata->gpio_vbus;
352
353 device_init_wakeup(&pdev->dev, 0);
354 cancel_delayed_work_sync(&gpio_vbus->work);
355 regulator_put(gpio_vbus->vbus_draw);
356
357 usb_remove_phy(&gpio_vbus->phy);
358
359 free_irq(gpio_vbus->irq, pdev);
360 if (gpio_is_valid(pdata->gpio_pullup))
361 gpio_free(pdata->gpio_pullup);
362 gpio_free(gpio);
363 platform_set_drvdata(pdev, NULL);
364 kfree(gpio_vbus->phy.otg);
365 kfree(gpio_vbus);
366
367 return 0;
368}
369
370#ifdef CONFIG_PM
371static int gpio_vbus_pm_suspend(struct device *dev)
372{
373 struct gpio_vbus_data *gpio_vbus = dev_get_drvdata(dev);
374
375 if (device_may_wakeup(dev))
376 enable_irq_wake(gpio_vbus->irq);
377
378 return 0;
379}
380
381static int gpio_vbus_pm_resume(struct device *dev)
382{
383 struct gpio_vbus_data *gpio_vbus = dev_get_drvdata(dev);
384
385 if (device_may_wakeup(dev))
386 disable_irq_wake(gpio_vbus->irq);
387
388 return 0;
389}
390
391static const struct dev_pm_ops gpio_vbus_dev_pm_ops = {
392 .suspend = gpio_vbus_pm_suspend,
393 .resume = gpio_vbus_pm_resume,
394};
395#endif
396
397/* NOTE: the gpio-vbus device may *NOT* be hotplugged */
398
399MODULE_ALIAS("platform:gpio-vbus");
400
401static struct platform_driver gpio_vbus_driver = {
402 .driver = {
403 .name = "gpio-vbus",
404 .owner = THIS_MODULE,
405#ifdef CONFIG_PM
406 .pm = &gpio_vbus_dev_pm_ops,
407#endif
408 },
409 .remove = __exit_p(gpio_vbus_remove),
410};
411
412module_platform_driver_probe(gpio_vbus_driver, gpio_vbus_probe);
413
414MODULE_DESCRIPTION("simple GPIO controlled OTG transceiver driver");
415MODULE_AUTHOR("Philipp Zabel");
416MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/isp1301_omap.c b/drivers/usb/phy/isp1301_omap.c
new file mode 100644
index 000000000000..8fe0c3b95261
--- /dev/null
+++ b/drivers/usb/phy/isp1301_omap.c
@@ -0,0 +1,1656 @@
1/*
2 * isp1301_omap - ISP 1301 USB transceiver, talking to OMAP OTG controller
3 *
4 * Copyright (C) 2004 Texas Instruments
5 * Copyright (C) 2004 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/slab.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/gpio.h>
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31#include <linux/usb.h>
32#include <linux/usb/otg.h>
33#include <linux/i2c.h>
34#include <linux/workqueue.h>
35
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <mach/mux.h>
40
41#include <mach/usb.h>
42
43#ifndef DEBUG
44#undef VERBOSE
45#endif
46
47
48#define DRIVER_VERSION "24 August 2004"
49#define DRIVER_NAME (isp1301_driver.driver.name)
50
51MODULE_DESCRIPTION("ISP1301 USB OTG Transceiver Driver");
52MODULE_LICENSE("GPL");
53
54struct isp1301 {
55 struct usb_phy phy;
56 struct i2c_client *client;
57 void (*i2c_release)(struct device *dev);
58
59 int irq_type;
60
61 u32 last_otg_ctrl;
62 unsigned working:1;
63
64 struct timer_list timer;
65
66 /* use keventd context to change the state for us */
67 struct work_struct work;
68
69 unsigned long todo;
70# define WORK_UPDATE_ISP 0 /* update ISP from OTG */
71# define WORK_UPDATE_OTG 1 /* update OTG from ISP */
72# define WORK_HOST_RESUME 4 /* resume host */
73# define WORK_TIMER 6 /* timer fired */
74# define WORK_STOP 7 /* don't resubmit */
75};
76
77
78/* bits in OTG_CTRL */
79
80#define OTG_XCEIV_OUTPUTS \
81 (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
82#define OTG_XCEIV_INPUTS \
83 (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
84#define OTG_CTRL_BITS \
85 (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|OTG_B_HNPEN|OTG_BUSDROP)
86 /* and OTG_PULLUP is sometimes written */
87
88#define OTG_CTRL_MASK (OTG_DRIVER_SEL| \
89 OTG_XCEIV_OUTPUTS|OTG_XCEIV_INPUTS| \
90 OTG_CTRL_BITS)
91
92
93/*-------------------------------------------------------------------------*/
94
95/* board-specific PM hooks */
96
97#if defined(CONFIG_MACH_OMAP_H2) || defined(CONFIG_MACH_OMAP_H3)
98
99#if defined(CONFIG_TPS65010) || defined(CONFIG_TPS65010_MODULE)
100
101#include <linux/i2c/tps65010.h>
102
103#else
104
105static inline int tps65010_set_vbus_draw(unsigned mA)
106{
107 pr_debug("tps65010: draw %d mA (STUB)\n", mA);
108 return 0;
109}
110
111#endif
112
113static void enable_vbus_draw(struct isp1301 *isp, unsigned mA)
114{
115 int status = tps65010_set_vbus_draw(mA);
116 if (status < 0)
117 pr_debug(" VBUS %d mA error %d\n", mA, status);
118}
119
120#else
121
122static void enable_vbus_draw(struct isp1301 *isp, unsigned mA)
123{
124 /* H4 controls this by DIP switch S2.4; no soft control.
125 * ON means the charger is always enabled. Leave it OFF
126 * unless the OTG port is used only in B-peripheral mode.
127 */
128}
129
130#endif
131
132static void enable_vbus_source(struct isp1301 *isp)
133{
134 /* this board won't supply more than 8mA vbus power.
135 * some boards can switch a 100ma "unit load" (or more).
136 */
137}
138
139
140/* products will deliver OTG messages with LEDs, GUI, etc */
141static inline void notresponding(struct isp1301 *isp)
142{
143 printk(KERN_NOTICE "OTG device not responding.\n");
144}
145
146
147/*-------------------------------------------------------------------------*/
148
149static struct i2c_driver isp1301_driver;
150
151/* smbus apis are used for portability */
152
153static inline u8
154isp1301_get_u8(struct isp1301 *isp, u8 reg)
155{
156 return i2c_smbus_read_byte_data(isp->client, reg + 0);
157}
158
159static inline int
160isp1301_get_u16(struct isp1301 *isp, u8 reg)
161{
162 return i2c_smbus_read_word_data(isp->client, reg);
163}
164
165static inline int
166isp1301_set_bits(struct isp1301 *isp, u8 reg, u8 bits)
167{
168 return i2c_smbus_write_byte_data(isp->client, reg + 0, bits);
169}
170
171static inline int
172isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits)
173{
174 return i2c_smbus_write_byte_data(isp->client, reg + 1, bits);
175}
176
177/*-------------------------------------------------------------------------*/
178
179/* identification */
180#define ISP1301_VENDOR_ID 0x00 /* u16 read */
181#define ISP1301_PRODUCT_ID 0x02 /* u16 read */
182#define ISP1301_BCD_DEVICE 0x14 /* u16 read */
183
184#define I2C_VENDOR_ID_PHILIPS 0x04cc
185#define I2C_PRODUCT_ID_PHILIPS_1301 0x1301
186
187/* operational registers */
188#define ISP1301_MODE_CONTROL_1 0x04 /* u8 read, set, +1 clear */
189# define MC1_SPEED (1 << 0)
190# define MC1_SUSPEND (1 << 1)
191# define MC1_DAT_SE0 (1 << 2)
192# define MC1_TRANSPARENT (1 << 3)
193# define MC1_BDIS_ACON_EN (1 << 4)
194# define MC1_OE_INT_EN (1 << 5)
195# define MC1_UART_EN (1 << 6)
196# define MC1_MASK 0x7f
197#define ISP1301_MODE_CONTROL_2 0x12 /* u8 read, set, +1 clear */
198# define MC2_GLOBAL_PWR_DN (1 << 0)
199# define MC2_SPD_SUSP_CTRL (1 << 1)
200# define MC2_BI_DI (1 << 2)
201# define MC2_TRANSP_BDIR0 (1 << 3)
202# define MC2_TRANSP_BDIR1 (1 << 4)
203# define MC2_AUDIO_EN (1 << 5)
204# define MC2_PSW_EN (1 << 6)
205# define MC2_EN2V7 (1 << 7)
206#define ISP1301_OTG_CONTROL_1 0x06 /* u8 read, set, +1 clear */
207# define OTG1_DP_PULLUP (1 << 0)
208# define OTG1_DM_PULLUP (1 << 1)
209# define OTG1_DP_PULLDOWN (1 << 2)
210# define OTG1_DM_PULLDOWN (1 << 3)
211# define OTG1_ID_PULLDOWN (1 << 4)
212# define OTG1_VBUS_DRV (1 << 5)
213# define OTG1_VBUS_DISCHRG (1 << 6)
214# define OTG1_VBUS_CHRG (1 << 7)
215#define ISP1301_OTG_STATUS 0x10 /* u8 readonly */
216# define OTG_B_SESS_END (1 << 6)
217# define OTG_B_SESS_VLD (1 << 7)
218
219#define ISP1301_INTERRUPT_SOURCE 0x08 /* u8 read */
220#define ISP1301_INTERRUPT_LATCH 0x0A /* u8 read, set, +1 clear */
221
222#define ISP1301_INTERRUPT_FALLING 0x0C /* u8 read, set, +1 clear */
223#define ISP1301_INTERRUPT_RISING 0x0E /* u8 read, set, +1 clear */
224
225/* same bitfields in all interrupt registers */
226# define INTR_VBUS_VLD (1 << 0)
227# define INTR_SESS_VLD (1 << 1)
228# define INTR_DP_HI (1 << 2)
229# define INTR_ID_GND (1 << 3)
230# define INTR_DM_HI (1 << 4)
231# define INTR_ID_FLOAT (1 << 5)
232# define INTR_BDIS_ACON (1 << 6)
233# define INTR_CR_INT (1 << 7)
234
235/*-------------------------------------------------------------------------*/
236
237static inline const char *state_name(struct isp1301 *isp)
238{
239 return usb_otg_state_string(isp->phy.state);
240}
241
242/*-------------------------------------------------------------------------*/
243
244/* NOTE: some of this ISP1301 setup is specific to H2 boards;
245 * not everything is guarded by board-specific checks, or even using
246 * omap_usb_config data to deduce MC1_DAT_SE0 and MC2_BI_DI.
247 *
248 * ALSO: this currently doesn't use ISP1301 low-power modes
249 * while OTG is running.
250 */
251
252static void power_down(struct isp1301 *isp)
253{
254 isp->phy.state = OTG_STATE_UNDEFINED;
255
256 // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
257 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
258
259 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN);
260 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
261}
262
263static void power_up(struct isp1301 *isp)
264{
265 // isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
266 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
267
268 /* do this only when cpu is driving transceiver,
269 * so host won't see a low speed device...
270 */
271 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
272}
273
274#define NO_HOST_SUSPEND
275
276static int host_suspend(struct isp1301 *isp)
277{
278#ifdef NO_HOST_SUSPEND
279 return 0;
280#else
281 struct device *dev;
282
283 if (!isp->phy.otg->host)
284 return -ENODEV;
285
286 /* Currently ASSUMES only the OTG port matters;
287 * other ports could be active...
288 */
289 dev = isp->phy.otg->host->controller;
290 return dev->driver->suspend(dev, 3, 0);
291#endif
292}
293
294static int host_resume(struct isp1301 *isp)
295{
296#ifdef NO_HOST_SUSPEND
297 return 0;
298#else
299 struct device *dev;
300
301 if (!isp->phy.otg->host)
302 return -ENODEV;
303
304 dev = isp->phy.otg->host->controller;
305 return dev->driver->resume(dev, 0);
306#endif
307}
308
309static int gadget_suspend(struct isp1301 *isp)
310{
311 isp->phy.otg->gadget->b_hnp_enable = 0;
312 isp->phy.otg->gadget->a_hnp_support = 0;
313 isp->phy.otg->gadget->a_alt_hnp_support = 0;
314 return usb_gadget_vbus_disconnect(isp->phy.otg->gadget);
315}
316
317/*-------------------------------------------------------------------------*/
318
319#define TIMER_MINUTES 10
320#define TIMER_JIFFIES (TIMER_MINUTES * 60 * HZ)
321
322/* Almost all our I2C messaging comes from a work queue's task context.
323 * NOTE: guaranteeing certain response times might mean we shouldn't
324 * share keventd's work queue; a realtime task might be safest.
325 */
326static void isp1301_defer_work(struct isp1301 *isp, int work)
327{
328 int status;
329
330 if (isp && !test_and_set_bit(work, &isp->todo)) {
331 (void) get_device(&isp->client->dev);
332 status = schedule_work(&isp->work);
333 if (!status && !isp->working)
334 dev_vdbg(&isp->client->dev,
335 "work item %d may be lost\n", work);
336 }
337}
338
339/* called from irq handlers */
340static void a_idle(struct isp1301 *isp, const char *tag)
341{
342 u32 l;
343
344 if (isp->phy.state == OTG_STATE_A_IDLE)
345 return;
346
347 isp->phy.otg->default_a = 1;
348 if (isp->phy.otg->host) {
349 isp->phy.otg->host->is_b_host = 0;
350 host_suspend(isp);
351 }
352 if (isp->phy.otg->gadget) {
353 isp->phy.otg->gadget->is_a_peripheral = 1;
354 gadget_suspend(isp);
355 }
356 isp->phy.state = OTG_STATE_A_IDLE;
357 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
358 omap_writel(l, OTG_CTRL);
359 isp->last_otg_ctrl = l;
360 pr_debug(" --> %s/%s\n", state_name(isp), tag);
361}
362
363/* called from irq handlers */
364static void b_idle(struct isp1301 *isp, const char *tag)
365{
366 u32 l;
367
368 if (isp->phy.state == OTG_STATE_B_IDLE)
369 return;
370
371 isp->phy.otg->default_a = 0;
372 if (isp->phy.otg->host) {
373 isp->phy.otg->host->is_b_host = 1;
374 host_suspend(isp);
375 }
376 if (isp->phy.otg->gadget) {
377 isp->phy.otg->gadget->is_a_peripheral = 0;
378 gadget_suspend(isp);
379 }
380 isp->phy.state = OTG_STATE_B_IDLE;
381 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
382 omap_writel(l, OTG_CTRL);
383 isp->last_otg_ctrl = l;
384 pr_debug(" --> %s/%s\n", state_name(isp), tag);
385}
386
387static void
388dump_regs(struct isp1301 *isp, const char *label)
389{
390#ifdef DEBUG
391 u8 ctrl = isp1301_get_u8(isp, ISP1301_OTG_CONTROL_1);
392 u8 status = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
393 u8 src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
394
395 pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n",
396 omap_readl(OTG_CTRL), label, state_name(isp),
397 ctrl, status, src);
398 /* mode control and irq enables don't change much */
399#endif
400}
401
402/*-------------------------------------------------------------------------*/
403
404#ifdef CONFIG_USB_OTG
405
406/*
407 * The OMAP OTG controller handles most of the OTG state transitions.
408 *
409 * We translate isp1301 outputs (mostly voltage comparator status) into
410 * OTG inputs; OTG outputs (mostly pullup/pulldown controls) and HNP state
411 * flags into isp1301 inputs ... and infer state transitions.
412 */
413
414#ifdef VERBOSE
415
416static void check_state(struct isp1301 *isp, const char *tag)
417{
418 enum usb_otg_state state = OTG_STATE_UNDEFINED;
419 u8 fsm = omap_readw(OTG_TEST) & 0x0ff;
420 unsigned extra = 0;
421
422 switch (fsm) {
423
424 /* default-b */
425 case 0x0:
426 state = OTG_STATE_B_IDLE;
427 break;
428 case 0x3:
429 case 0x7:
430 extra = 1;
431 case 0x1:
432 state = OTG_STATE_B_PERIPHERAL;
433 break;
434 case 0x11:
435 state = OTG_STATE_B_SRP_INIT;
436 break;
437
438 /* extra dual-role default-b states */
439 case 0x12:
440 case 0x13:
441 case 0x16:
442 extra = 1;
443 case 0x17:
444 state = OTG_STATE_B_WAIT_ACON;
445 break;
446 case 0x34:
447 state = OTG_STATE_B_HOST;
448 break;
449
450 /* default-a */
451 case 0x36:
452 state = OTG_STATE_A_IDLE;
453 break;
454 case 0x3c:
455 state = OTG_STATE_A_WAIT_VFALL;
456 break;
457 case 0x7d:
458 state = OTG_STATE_A_VBUS_ERR;
459 break;
460 case 0x9e:
461 case 0x9f:
462 extra = 1;
463 case 0x89:
464 state = OTG_STATE_A_PERIPHERAL;
465 break;
466 case 0xb7:
467 state = OTG_STATE_A_WAIT_VRISE;
468 break;
469 case 0xb8:
470 state = OTG_STATE_A_WAIT_BCON;
471 break;
472 case 0xb9:
473 state = OTG_STATE_A_HOST;
474 break;
475 case 0xba:
476 state = OTG_STATE_A_SUSPEND;
477 break;
478 default:
479 break;
480 }
481 if (isp->phy.state == state && !extra)
482 return;
483 pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
484 usb_otg_state_string(state), fsm, state_name(isp),
485 omap_readl(OTG_CTRL));
486}
487
488#else
489
490static inline void check_state(struct isp1301 *isp, const char *tag) { }
491
492#endif
493
494/* outputs from ISP1301_INTERRUPT_SOURCE */
495static void update_otg1(struct isp1301 *isp, u8 int_src)
496{
497 u32 otg_ctrl;
498
499 otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
500 otg_ctrl &= ~OTG_XCEIV_INPUTS;
501 otg_ctrl &= ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD);
502
503 if (int_src & INTR_SESS_VLD)
504 otg_ctrl |= OTG_ASESSVLD;
505 else if (isp->phy.state == OTG_STATE_A_WAIT_VFALL) {
506 a_idle(isp, "vfall");
507 otg_ctrl &= ~OTG_CTRL_BITS;
508 }
509 if (int_src & INTR_VBUS_VLD)
510 otg_ctrl |= OTG_VBUSVLD;
511 if (int_src & INTR_ID_GND) { /* default-A */
512 if (isp->phy.state == OTG_STATE_B_IDLE
513 || isp->phy.state
514 == OTG_STATE_UNDEFINED) {
515 a_idle(isp, "init");
516 return;
517 }
518 } else { /* default-B */
519 otg_ctrl |= OTG_ID;
520 if (isp->phy.state == OTG_STATE_A_IDLE
521 || isp->phy.state == OTG_STATE_UNDEFINED) {
522 b_idle(isp, "init");
523 return;
524 }
525 }
526 omap_writel(otg_ctrl, OTG_CTRL);
527}
528
529/* outputs from ISP1301_OTG_STATUS */
530static void update_otg2(struct isp1301 *isp, u8 otg_status)
531{
532 u32 otg_ctrl;
533
534 otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
535 otg_ctrl &= ~OTG_XCEIV_INPUTS;
536 otg_ctrl &= ~(OTG_BSESSVLD | OTG_BSESSEND);
537 if (otg_status & OTG_B_SESS_VLD)
538 otg_ctrl |= OTG_BSESSVLD;
539 else if (otg_status & OTG_B_SESS_END)
540 otg_ctrl |= OTG_BSESSEND;
541 omap_writel(otg_ctrl, OTG_CTRL);
542}
543
544/* inputs going to ISP1301 */
545static void otg_update_isp(struct isp1301 *isp)
546{
547 u32 otg_ctrl, otg_change;
548 u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP;
549
550 otg_ctrl = omap_readl(OTG_CTRL);
551 otg_change = otg_ctrl ^ isp->last_otg_ctrl;
552 isp->last_otg_ctrl = otg_ctrl;
553 otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS;
554
555 switch (isp->phy.state) {
556 case OTG_STATE_B_IDLE:
557 case OTG_STATE_B_PERIPHERAL:
558 case OTG_STATE_B_SRP_INIT:
559 if (!(otg_ctrl & OTG_PULLUP)) {
560 // if (otg_ctrl & OTG_B_HNPEN) {
561 if (isp->phy.otg->gadget->b_hnp_enable) {
562 isp->phy.state = OTG_STATE_B_WAIT_ACON;
563 pr_debug(" --> b_wait_acon\n");
564 }
565 goto pulldown;
566 }
567pullup:
568 set |= OTG1_DP_PULLUP;
569 clr |= OTG1_DP_PULLDOWN;
570 break;
571 case OTG_STATE_A_SUSPEND:
572 case OTG_STATE_A_PERIPHERAL:
573 if (otg_ctrl & OTG_PULLUP)
574 goto pullup;
575 /* FALLTHROUGH */
576 // case OTG_STATE_B_WAIT_ACON:
577 default:
578pulldown:
579 set |= OTG1_DP_PULLDOWN;
580 clr |= OTG1_DP_PULLUP;
581 break;
582 }
583
584# define toggle(OTG,ISP) do { \
585 if (otg_ctrl & OTG) set |= ISP; \
586 else clr |= ISP; \
587 } while (0)
588
589 if (!(isp->phy.otg->host))
590 otg_ctrl &= ~OTG_DRV_VBUS;
591
592 switch (isp->phy.state) {
593 case OTG_STATE_A_SUSPEND:
594 if (otg_ctrl & OTG_DRV_VBUS) {
595 set |= OTG1_VBUS_DRV;
596 break;
597 }
598 /* HNP failed for some reason (A_AIDL_BDIS timeout) */
599 notresponding(isp);
600
601 /* FALLTHROUGH */
602 case OTG_STATE_A_VBUS_ERR:
603 isp->phy.state = OTG_STATE_A_WAIT_VFALL;
604 pr_debug(" --> a_wait_vfall\n");
605 /* FALLTHROUGH */
606 case OTG_STATE_A_WAIT_VFALL:
607 /* FIXME usbcore thinks port power is still on ... */
608 clr |= OTG1_VBUS_DRV;
609 break;
610 case OTG_STATE_A_IDLE:
611 if (otg_ctrl & OTG_DRV_VBUS) {
612 isp->phy.state = OTG_STATE_A_WAIT_VRISE;
613 pr_debug(" --> a_wait_vrise\n");
614 }
615 /* FALLTHROUGH */
616 default:
617 toggle(OTG_DRV_VBUS, OTG1_VBUS_DRV);
618 }
619
620 toggle(OTG_PU_VBUS, OTG1_VBUS_CHRG);
621 toggle(OTG_PD_VBUS, OTG1_VBUS_DISCHRG);
622
623# undef toggle
624
625 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, set);
626 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, clr);
627
628 /* HNP switch to host or peripheral; and SRP */
629 if (otg_change & OTG_PULLUP) {
630 u32 l;
631
632 switch (isp->phy.state) {
633 case OTG_STATE_B_IDLE:
634 if (clr & OTG1_DP_PULLUP)
635 break;
636 isp->phy.state = OTG_STATE_B_PERIPHERAL;
637 pr_debug(" --> b_peripheral\n");
638 break;
639 case OTG_STATE_A_SUSPEND:
640 if (clr & OTG1_DP_PULLUP)
641 break;
642 isp->phy.state = OTG_STATE_A_PERIPHERAL;
643 pr_debug(" --> a_peripheral\n");
644 break;
645 default:
646 break;
647 }
648 l = omap_readl(OTG_CTRL);
649 l |= OTG_PULLUP;
650 omap_writel(l, OTG_CTRL);
651 }
652
653 check_state(isp, __func__);
654 dump_regs(isp, "otg->isp1301");
655}
656
657static irqreturn_t omap_otg_irq(int irq, void *_isp)
658{
659 u16 otg_irq = omap_readw(OTG_IRQ_SRC);
660 u32 otg_ctrl;
661 int ret = IRQ_NONE;
662 struct isp1301 *isp = _isp;
663 struct usb_otg *otg = isp->phy.otg;
664
665 /* update ISP1301 transceiver from OTG controller */
666 if (otg_irq & OPRT_CHG) {
667 omap_writew(OPRT_CHG, OTG_IRQ_SRC);
668 isp1301_defer_work(isp, WORK_UPDATE_ISP);
669 ret = IRQ_HANDLED;
670
671 /* SRP to become b_peripheral failed */
672 } else if (otg_irq & B_SRP_TMROUT) {
673 pr_debug("otg: B_SRP_TIMEOUT, %06x\n", omap_readl(OTG_CTRL));
674 notresponding(isp);
675
676 /* gadget drivers that care should monitor all kinds of
677 * remote wakeup (SRP, normal) using their own timer
678 * to give "check cable and A-device" messages.
679 */
680 if (isp->phy.state == OTG_STATE_B_SRP_INIT)
681 b_idle(isp, "srp_timeout");
682
683 omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
684 ret = IRQ_HANDLED;
685
686 /* HNP to become b_host failed */
687 } else if (otg_irq & B_HNP_FAIL) {
688 pr_debug("otg: %s B_HNP_FAIL, %06x\n",
689 state_name(isp), omap_readl(OTG_CTRL));
690 notresponding(isp);
691
692 otg_ctrl = omap_readl(OTG_CTRL);
693 otg_ctrl |= OTG_BUSDROP;
694 otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
695 omap_writel(otg_ctrl, OTG_CTRL);
696
697 /* subset of b_peripheral()... */
698 isp->phy.state = OTG_STATE_B_PERIPHERAL;
699 pr_debug(" --> b_peripheral\n");
700
701 omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
702 ret = IRQ_HANDLED;
703
704 /* detect SRP from B-device ... */
705 } else if (otg_irq & A_SRP_DETECT) {
706 pr_debug("otg: %s SRP_DETECT, %06x\n",
707 state_name(isp), omap_readl(OTG_CTRL));
708
709 isp1301_defer_work(isp, WORK_UPDATE_OTG);
710 switch (isp->phy.state) {
711 case OTG_STATE_A_IDLE:
712 if (!otg->host)
713 break;
714 isp1301_defer_work(isp, WORK_HOST_RESUME);
715 otg_ctrl = omap_readl(OTG_CTRL);
716 otg_ctrl |= OTG_A_BUSREQ;
717 otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
718 & ~OTG_XCEIV_INPUTS
719 & OTG_CTRL_MASK;
720 omap_writel(otg_ctrl, OTG_CTRL);
721 break;
722 default:
723 break;
724 }
725
726 omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
727 ret = IRQ_HANDLED;
728
729 /* timer expired: T(a_wait_bcon) and maybe T(a_wait_vrise)
730 * we don't track them separately
731 */
732 } else if (otg_irq & A_REQ_TMROUT) {
733 otg_ctrl = omap_readl(OTG_CTRL);
734 pr_info("otg: BCON_TMOUT from %s, %06x\n",
735 state_name(isp), otg_ctrl);
736 notresponding(isp);
737
738 otg_ctrl |= OTG_BUSDROP;
739 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
740 omap_writel(otg_ctrl, OTG_CTRL);
741 isp->phy.state = OTG_STATE_A_WAIT_VFALL;
742
743 omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
744 ret = IRQ_HANDLED;
745
746 /* A-supplied voltage fell too low; overcurrent */
747 } else if (otg_irq & A_VBUS_ERR) {
748 otg_ctrl = omap_readl(OTG_CTRL);
749 printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n",
750 state_name(isp), otg_irq, otg_ctrl);
751
752 otg_ctrl |= OTG_BUSDROP;
753 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
754 omap_writel(otg_ctrl, OTG_CTRL);
755 isp->phy.state = OTG_STATE_A_VBUS_ERR;
756
757 omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
758 ret = IRQ_HANDLED;
759
760 /* switch driver; the transceiver code activates it,
761 * ungating the udc clock or resuming OHCI.
762 */
763 } else if (otg_irq & DRIVER_SWITCH) {
764 int kick = 0;
765
766 otg_ctrl = omap_readl(OTG_CTRL);
767 printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n",
768 state_name(isp),
769 (otg_ctrl & OTG_DRIVER_SEL)
770 ? "gadget" : "host",
771 otg_ctrl);
772 isp1301_defer_work(isp, WORK_UPDATE_ISP);
773
774 /* role is peripheral */
775 if (otg_ctrl & OTG_DRIVER_SEL) {
776 switch (isp->phy.state) {
777 case OTG_STATE_A_IDLE:
778 b_idle(isp, __func__);
779 break;
780 default:
781 break;
782 }
783 isp1301_defer_work(isp, WORK_UPDATE_ISP);
784
785 /* role is host */
786 } else {
787 if (!(otg_ctrl & OTG_ID)) {
788 otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
789 omap_writel(otg_ctrl | OTG_A_BUSREQ, OTG_CTRL);
790 }
791
792 if (otg->host) {
793 switch (isp->phy.state) {
794 case OTG_STATE_B_WAIT_ACON:
795 isp->phy.state = OTG_STATE_B_HOST;
796 pr_debug(" --> b_host\n");
797 kick = 1;
798 break;
799 case OTG_STATE_A_WAIT_BCON:
800 isp->phy.state = OTG_STATE_A_HOST;
801 pr_debug(" --> a_host\n");
802 break;
803 case OTG_STATE_A_PERIPHERAL:
804 isp->phy.state = OTG_STATE_A_WAIT_BCON;
805 pr_debug(" --> a_wait_bcon\n");
806 break;
807 default:
808 break;
809 }
810 isp1301_defer_work(isp, WORK_HOST_RESUME);
811 }
812 }
813
814 omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
815 ret = IRQ_HANDLED;
816
817 if (kick)
818 usb_bus_start_enum(otg->host, otg->host->otg_port);
819 }
820
821 check_state(isp, __func__);
822 return ret;
823}
824
825static struct platform_device *otg_dev;
826
827static int isp1301_otg_init(struct isp1301 *isp)
828{
829 u32 l;
830
831 if (!otg_dev)
832 return -ENODEV;
833
834 dump_regs(isp, __func__);
835 /* some of these values are board-specific... */
836 l = omap_readl(OTG_SYSCON_2);
837 l |= OTG_EN
838 /* for B-device: */
839 | SRP_GPDATA /* 9msec Bdev D+ pulse */
840 | SRP_GPDVBUS /* discharge after VBUS pulse */
841 // | (3 << 24) /* 2msec VBUS pulse */
842 /* for A-device: */
843 | (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */
844 | SRP_DPW /* detect 167+ns SRP pulses */
845 | SRP_DATA | SRP_VBUS /* accept both kinds of SRP pulse */
846 ;
847 omap_writel(l, OTG_SYSCON_2);
848
849 update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
850 update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
851
852 check_state(isp, __func__);
853 pr_debug("otg: %s, %s %06x\n",
854 state_name(isp), __func__, omap_readl(OTG_CTRL));
855
856 omap_writew(DRIVER_SWITCH | OPRT_CHG
857 | B_SRP_TMROUT | B_HNP_FAIL
858 | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, OTG_IRQ_EN);
859
860 l = omap_readl(OTG_SYSCON_2);
861 l |= OTG_EN;
862 omap_writel(l, OTG_SYSCON_2);
863
864 return 0;
865}
866
867static int otg_probe(struct platform_device *dev)
868{
869 // struct omap_usb_config *config = dev->platform_data;
870
871 otg_dev = dev;
872 return 0;
873}
874
875static int otg_remove(struct platform_device *dev)
876{
877 otg_dev = NULL;
878 return 0;
879}
880
881static struct platform_driver omap_otg_driver = {
882 .probe = otg_probe,
883 .remove = otg_remove,
884 .driver = {
885 .owner = THIS_MODULE,
886 .name = "omap_otg",
887 },
888};
889
890static int otg_bind(struct isp1301 *isp)
891{
892 int status;
893
894 if (otg_dev)
895 return -EBUSY;
896
897 status = platform_driver_register(&omap_otg_driver);
898 if (status < 0)
899 return status;
900
901 if (otg_dev)
902 status = request_irq(otg_dev->resource[1].start, omap_otg_irq,
903 0, DRIVER_NAME, isp);
904 else
905 status = -ENODEV;
906
907 if (status < 0)
908 platform_driver_unregister(&omap_otg_driver);
909 return status;
910}
911
912static void otg_unbind(struct isp1301 *isp)
913{
914 if (!otg_dev)
915 return;
916 free_irq(otg_dev->resource[1].start, isp);
917}
918
919#else
920
921/* OTG controller isn't clocked */
922
923#endif /* CONFIG_USB_OTG */
924
925/*-------------------------------------------------------------------------*/
926
927static void b_peripheral(struct isp1301 *isp)
928{
929 u32 l;
930
931 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
932 omap_writel(l, OTG_CTRL);
933
934 usb_gadget_vbus_connect(isp->phy.otg->gadget);
935
936#ifdef CONFIG_USB_OTG
937 enable_vbus_draw(isp, 8);
938 otg_update_isp(isp);
939#else
940 enable_vbus_draw(isp, 100);
941 /* UDC driver just set OTG_BSESSVLD */
942 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLUP);
943 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLDOWN);
944 isp->phy.state = OTG_STATE_B_PERIPHERAL;
945 pr_debug(" --> b_peripheral\n");
946 dump_regs(isp, "2periph");
947#endif
948}
949
950static void isp_update_otg(struct isp1301 *isp, u8 stat)
951{
952 struct usb_otg *otg = isp->phy.otg;
953 u8 isp_stat, isp_bstat;
954 enum usb_otg_state state = isp->phy.state;
955
956 if (stat & INTR_BDIS_ACON)
957 pr_debug("OTG: BDIS_ACON, %s\n", state_name(isp));
958
959 /* start certain state transitions right away */
960 isp_stat = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
961 if (isp_stat & INTR_ID_GND) {
962 if (otg->default_a) {
963 switch (state) {
964 case OTG_STATE_B_IDLE:
965 a_idle(isp, "idle");
966 /* FALLTHROUGH */
967 case OTG_STATE_A_IDLE:
968 enable_vbus_source(isp);
969 /* FALLTHROUGH */
970 case OTG_STATE_A_WAIT_VRISE:
971 /* we skip over OTG_STATE_A_WAIT_BCON, since
972 * the HC will transition to A_HOST (or
973 * A_SUSPEND!) without our noticing except
974 * when HNP is used.
975 */
976 if (isp_stat & INTR_VBUS_VLD)
977 isp->phy.state = OTG_STATE_A_HOST;
978 break;
979 case OTG_STATE_A_WAIT_VFALL:
980 if (!(isp_stat & INTR_SESS_VLD))
981 a_idle(isp, "vfell");
982 break;
983 default:
984 if (!(isp_stat & INTR_VBUS_VLD))
985 isp->phy.state = OTG_STATE_A_VBUS_ERR;
986 break;
987 }
988 isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
989 } else {
990 switch (state) {
991 case OTG_STATE_B_PERIPHERAL:
992 case OTG_STATE_B_HOST:
993 case OTG_STATE_B_WAIT_ACON:
994 usb_gadget_vbus_disconnect(otg->gadget);
995 break;
996 default:
997 break;
998 }
999 if (state != OTG_STATE_A_IDLE)
1000 a_idle(isp, "id");
1001 if (otg->host && state == OTG_STATE_A_IDLE)
1002 isp1301_defer_work(isp, WORK_HOST_RESUME);
1003 isp_bstat = 0;
1004 }
1005 } else {
1006 u32 l;
1007
1008 /* if user unplugged mini-A end of cable,
1009 * don't bypass A_WAIT_VFALL.
1010 */
1011 if (otg->default_a) {
1012 switch (state) {
1013 default:
1014 isp->phy.state = OTG_STATE_A_WAIT_VFALL;
1015 break;
1016 case OTG_STATE_A_WAIT_VFALL:
1017 state = OTG_STATE_A_IDLE;
1018 /* khubd may take a while to notice and
1019 * handle this disconnect, so don't go
1020 * to B_IDLE quite yet.
1021 */
1022 break;
1023 case OTG_STATE_A_IDLE:
1024 host_suspend(isp);
1025 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1,
1026 MC1_BDIS_ACON_EN);
1027 isp->phy.state = OTG_STATE_B_IDLE;
1028 l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
1029 l &= ~OTG_CTRL_BITS;
1030 omap_writel(l, OTG_CTRL);
1031 break;
1032 case OTG_STATE_B_IDLE:
1033 break;
1034 }
1035 }
1036 isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
1037
1038 switch (isp->phy.state) {
1039 case OTG_STATE_B_PERIPHERAL:
1040 case OTG_STATE_B_WAIT_ACON:
1041 case OTG_STATE_B_HOST:
1042 if (likely(isp_bstat & OTG_B_SESS_VLD))
1043 break;
1044 enable_vbus_draw(isp, 0);
1045#ifndef CONFIG_USB_OTG
1046 /* UDC driver will clear OTG_BSESSVLD */
1047 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1,
1048 OTG1_DP_PULLDOWN);
1049 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
1050 OTG1_DP_PULLUP);
1051 dump_regs(isp, __func__);
1052#endif
1053 /* FALLTHROUGH */
1054 case OTG_STATE_B_SRP_INIT:
1055 b_idle(isp, __func__);
1056 l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
1057 omap_writel(l, OTG_CTRL);
1058 /* FALLTHROUGH */
1059 case OTG_STATE_B_IDLE:
1060 if (otg->gadget && (isp_bstat & OTG_B_SESS_VLD)) {
1061#ifdef CONFIG_USB_OTG
1062 update_otg1(isp, isp_stat);
1063 update_otg2(isp, isp_bstat);
1064#endif
1065 b_peripheral(isp);
1066 } else if (!(isp_stat & (INTR_VBUS_VLD|INTR_SESS_VLD)))
1067 isp_bstat |= OTG_B_SESS_END;
1068 break;
1069 case OTG_STATE_A_WAIT_VFALL:
1070 break;
1071 default:
1072 pr_debug("otg: unsupported b-device %s\n",
1073 state_name(isp));
1074 break;
1075 }
1076 }
1077
1078 if (state != isp->phy.state)
1079 pr_debug(" isp, %s -> %s\n",
1080 usb_otg_state_string(state), state_name(isp));
1081
1082#ifdef CONFIG_USB_OTG
1083 /* update the OTG controller state to match the isp1301; may
1084 * trigger OPRT_CHG irqs for changes going to the isp1301.
1085 */
1086 update_otg1(isp, isp_stat);
1087 update_otg2(isp, isp_bstat);
1088 check_state(isp, __func__);
1089#endif
1090
1091 dump_regs(isp, "isp1301->otg");
1092}
1093
1094/*-------------------------------------------------------------------------*/
1095
1096static u8 isp1301_clear_latch(struct isp1301 *isp)
1097{
1098 u8 latch = isp1301_get_u8(isp, ISP1301_INTERRUPT_LATCH);
1099 isp1301_clear_bits(isp, ISP1301_INTERRUPT_LATCH, latch);
1100 return latch;
1101}
1102
1103static void
1104isp1301_work(struct work_struct *work)
1105{
1106 struct isp1301 *isp = container_of(work, struct isp1301, work);
1107 int stop;
1108
1109 /* implicit lock: we're the only task using this device */
1110 isp->working = 1;
1111 do {
1112 stop = test_bit(WORK_STOP, &isp->todo);
1113
1114#ifdef CONFIG_USB_OTG
1115 /* transfer state from otg engine to isp1301 */
1116 if (test_and_clear_bit(WORK_UPDATE_ISP, &isp->todo)) {
1117 otg_update_isp(isp);
1118 put_device(&isp->client->dev);
1119 }
1120#endif
1121 /* transfer state from isp1301 to otg engine */
1122 if (test_and_clear_bit(WORK_UPDATE_OTG, &isp->todo)) {
1123 u8 stat = isp1301_clear_latch(isp);
1124
1125 isp_update_otg(isp, stat);
1126 put_device(&isp->client->dev);
1127 }
1128
1129 if (test_and_clear_bit(WORK_HOST_RESUME, &isp->todo)) {
1130 u32 otg_ctrl;
1131
1132 /*
1133 * skip A_WAIT_VRISE; hc transitions invisibly
1134 * skip A_WAIT_BCON; same.
1135 */
1136 switch (isp->phy.state) {
1137 case OTG_STATE_A_WAIT_BCON:
1138 case OTG_STATE_A_WAIT_VRISE:
1139 isp->phy.state = OTG_STATE_A_HOST;
1140 pr_debug(" --> a_host\n");
1141 otg_ctrl = omap_readl(OTG_CTRL);
1142 otg_ctrl |= OTG_A_BUSREQ;
1143 otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
1144 & OTG_CTRL_MASK;
1145 omap_writel(otg_ctrl, OTG_CTRL);
1146 break;
1147 case OTG_STATE_B_WAIT_ACON:
1148 isp->phy.state = OTG_STATE_B_HOST;
1149 pr_debug(" --> b_host (acon)\n");
1150 break;
1151 case OTG_STATE_B_HOST:
1152 case OTG_STATE_B_IDLE:
1153 case OTG_STATE_A_IDLE:
1154 break;
1155 default:
1156 pr_debug(" host resume in %s\n",
1157 state_name(isp));
1158 }
1159 host_resume(isp);
1160 // mdelay(10);
1161 put_device(&isp->client->dev);
1162 }
1163
1164 if (test_and_clear_bit(WORK_TIMER, &isp->todo)) {
1165#ifdef VERBOSE
1166 dump_regs(isp, "timer");
1167 if (!stop)
1168 mod_timer(&isp->timer, jiffies + TIMER_JIFFIES);
1169#endif
1170 put_device(&isp->client->dev);
1171 }
1172
1173 if (isp->todo)
1174 dev_vdbg(&isp->client->dev,
1175 "work done, todo = 0x%lx\n",
1176 isp->todo);
1177 if (stop) {
1178 dev_dbg(&isp->client->dev, "stop\n");
1179 break;
1180 }
1181 } while (isp->todo);
1182 isp->working = 0;
1183}
1184
1185static irqreturn_t isp1301_irq(int irq, void *isp)
1186{
1187 isp1301_defer_work(isp, WORK_UPDATE_OTG);
1188 return IRQ_HANDLED;
1189}
1190
1191static void isp1301_timer(unsigned long _isp)
1192{
1193 isp1301_defer_work((void *)_isp, WORK_TIMER);
1194}
1195
1196/*-------------------------------------------------------------------------*/
1197
1198static void isp1301_release(struct device *dev)
1199{
1200 struct isp1301 *isp;
1201
1202 isp = dev_get_drvdata(dev);
1203
1204 /* FIXME -- not with a "new style" driver, it doesn't!! */
1205
1206 /* ugly -- i2c hijacks our memory hook to wait_for_completion() */
1207 if (isp->i2c_release)
1208 isp->i2c_release(dev);
1209 kfree(isp->phy.otg);
1210 kfree (isp);
1211}
1212
1213static struct isp1301 *the_transceiver;
1214
1215static int __exit isp1301_remove(struct i2c_client *i2c)
1216{
1217 struct isp1301 *isp;
1218
1219 isp = i2c_get_clientdata(i2c);
1220
1221 isp1301_clear_bits(isp, ISP1301_INTERRUPT_FALLING, ~0);
1222 isp1301_clear_bits(isp, ISP1301_INTERRUPT_RISING, ~0);
1223 free_irq(i2c->irq, isp);
1224#ifdef CONFIG_USB_OTG
1225 otg_unbind(isp);
1226#endif
1227 if (machine_is_omap_h2())
1228 gpio_free(2);
1229
1230 isp->timer.data = 0;
1231 set_bit(WORK_STOP, &isp->todo);
1232 del_timer_sync(&isp->timer);
1233 flush_work(&isp->work);
1234
1235 put_device(&i2c->dev);
1236 the_transceiver = NULL;
1237
1238 return 0;
1239}
1240
1241/*-------------------------------------------------------------------------*/
1242
1243/* NOTE: three modes are possible here, only one of which
1244 * will be standards-conformant on any given system:
1245 *
1246 * - OTG mode (dual-role), required if there's a Mini-AB connector
1247 * - HOST mode, for when there's one or more A (host) connectors
1248 * - DEVICE mode, for when there's a B/Mini-B (device) connector
1249 *
1250 * As a rule, you won't have an isp1301 chip unless it's there to
1251 * support the OTG mode. Other modes help testing USB controllers
1252 * in isolation from (full) OTG support, or maybe so later board
1253 * revisions can help to support those feature.
1254 */
1255
1256#ifdef CONFIG_USB_OTG
1257
1258static int isp1301_otg_enable(struct isp1301 *isp)
1259{
1260 power_up(isp);
1261 isp1301_otg_init(isp);
1262
1263 /* NOTE: since we don't change this, this provides
1264 * a few more interrupts than are strictly needed.
1265 */
1266 isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
1267 INTR_VBUS_VLD | INTR_SESS_VLD | INTR_ID_GND);
1268 isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
1269 INTR_VBUS_VLD | INTR_SESS_VLD | INTR_ID_GND);
1270
1271 dev_info(&isp->client->dev, "ready for dual-role USB ...\n");
1272
1273 return 0;
1274}
1275
1276#endif
1277
1278/* add or disable the host device+driver */
1279static int
1280isp1301_set_host(struct usb_otg *otg, struct usb_bus *host)
1281{
1282 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1283
1284 if (!otg || isp != the_transceiver)
1285 return -ENODEV;
1286
1287 if (!host) {
1288 omap_writew(0, OTG_IRQ_EN);
1289 power_down(isp);
1290 otg->host = NULL;
1291 return 0;
1292 }
1293
1294#ifdef CONFIG_USB_OTG
1295 otg->host = host;
1296 dev_dbg(&isp->client->dev, "registered host\n");
1297 host_suspend(isp);
1298 if (otg->gadget)
1299 return isp1301_otg_enable(isp);
1300 return 0;
1301
1302#elif !defined(CONFIG_USB_GADGET_OMAP)
1303 // FIXME update its refcount
1304 otg->host = host;
1305
1306 power_up(isp);
1307
1308 if (machine_is_omap_h2())
1309 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
1310
1311 dev_info(&isp->client->dev, "A-Host sessions ok\n");
1312 isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
1313 INTR_ID_GND);
1314 isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
1315 INTR_ID_GND);
1316
1317 /* If this has a Mini-AB connector, this mode is highly
1318 * nonstandard ... but can be handy for testing, especially with
1319 * the Mini-A end of an OTG cable. (Or something nonstandard
1320 * like MiniB-to-StandardB, maybe built with a gender mender.)
1321 */
1322 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_VBUS_DRV);
1323
1324 dump_regs(isp, __func__);
1325
1326 return 0;
1327
1328#else
1329 dev_dbg(&isp->client->dev, "host sessions not allowed\n");
1330 return -EINVAL;
1331#endif
1332
1333}
1334
1335static int
1336isp1301_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget)
1337{
1338 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1339
1340 if (!otg || isp != the_transceiver)
1341 return -ENODEV;
1342
1343 if (!gadget) {
1344 omap_writew(0, OTG_IRQ_EN);
1345 if (!otg->default_a)
1346 enable_vbus_draw(isp, 0);
1347 usb_gadget_vbus_disconnect(otg->gadget);
1348 otg->gadget = NULL;
1349 power_down(isp);
1350 return 0;
1351 }
1352
1353#ifdef CONFIG_USB_OTG
1354 otg->gadget = gadget;
1355 dev_dbg(&isp->client->dev, "registered gadget\n");
1356 /* gadget driver may be suspended until vbus_connect () */
1357 if (otg->host)
1358 return isp1301_otg_enable(isp);
1359 return 0;
1360
1361#elif !defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OHCI_HCD_MODULE)
1362 otg->gadget = gadget;
1363 // FIXME update its refcount
1364
1365 {
1366 u32 l;
1367
1368 l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
1369 l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS);
1370 l |= OTG_ID;
1371 omap_writel(l, OTG_CTRL);
1372 }
1373
1374 power_up(isp);
1375 isp->phy.state = OTG_STATE_B_IDLE;
1376
1377 if (machine_is_omap_h2() || machine_is_omap_h3())
1378 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
1379
1380 isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING,
1381 INTR_SESS_VLD);
1382 isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
1383 INTR_VBUS_VLD);
1384 dev_info(&isp->client->dev, "B-Peripheral sessions ok\n");
1385 dump_regs(isp, __func__);
1386
1387 /* If this has a Mini-AB connector, this mode is highly
1388 * nonstandard ... but can be handy for testing, so long
1389 * as you don't plug a Mini-A cable into the jack.
1390 */
1391 if (isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE) & INTR_VBUS_VLD)
1392 b_peripheral(isp);
1393
1394 return 0;
1395
1396#else
1397 dev_dbg(&isp->client->dev, "peripheral sessions not allowed\n");
1398 return -EINVAL;
1399#endif
1400}
1401
1402
1403/*-------------------------------------------------------------------------*/
1404
1405static int
1406isp1301_set_power(struct usb_phy *dev, unsigned mA)
1407{
1408 if (!the_transceiver)
1409 return -ENODEV;
1410 if (dev->state == OTG_STATE_B_PERIPHERAL)
1411 enable_vbus_draw(the_transceiver, mA);
1412 return 0;
1413}
1414
1415static int
1416isp1301_start_srp(struct usb_otg *otg)
1417{
1418 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1419 u32 otg_ctrl;
1420
1421 if (!otg || isp != the_transceiver
1422 || isp->phy.state != OTG_STATE_B_IDLE)
1423 return -ENODEV;
1424
1425 otg_ctrl = omap_readl(OTG_CTRL);
1426 if (!(otg_ctrl & OTG_BSESSEND))
1427 return -EINVAL;
1428
1429 otg_ctrl |= OTG_B_BUSREQ;
1430 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK;
1431 omap_writel(otg_ctrl, OTG_CTRL);
1432 isp->phy.state = OTG_STATE_B_SRP_INIT;
1433
1434 pr_debug("otg: SRP, %s ... %06x\n", state_name(isp),
1435 omap_readl(OTG_CTRL));
1436#ifdef CONFIG_USB_OTG
1437 check_state(isp, __func__);
1438#endif
1439 return 0;
1440}
1441
1442static int
1443isp1301_start_hnp(struct usb_otg *otg)
1444{
1445#ifdef CONFIG_USB_OTG
1446 struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
1447 u32 l;
1448
1449 if (!otg || isp != the_transceiver)
1450 return -ENODEV;
1451 if (otg->default_a && (otg->host == NULL || !otg->host->b_hnp_enable))
1452 return -ENOTCONN;
1453 if (!otg->default_a && (otg->gadget == NULL
1454 || !otg->gadget->b_hnp_enable))
1455 return -ENOTCONN;
1456
1457 /* We want hardware to manage most HNP protocol timings.
1458 * So do this part as early as possible...
1459 */
1460 switch (isp->phy.state) {
1461 case OTG_STATE_B_HOST:
1462 isp->phy.state = OTG_STATE_B_PERIPHERAL;
1463 /* caller will suspend next */
1464 break;
1465 case OTG_STATE_A_HOST:
1466#if 0
1467 /* autoconnect mode avoids irq latency bugs */
1468 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1,
1469 MC1_BDIS_ACON_EN);
1470#endif
1471 /* caller must suspend then clear A_BUSREQ */
1472 usb_gadget_vbus_connect(otg->gadget);
1473 l = omap_readl(OTG_CTRL);
1474 l |= OTG_A_SETB_HNPEN;
1475 omap_writel(l, OTG_CTRL);
1476
1477 break;
1478 case OTG_STATE_A_PERIPHERAL:
1479 /* initiated by B-Host suspend */
1480 break;
1481 default:
1482 return -EILSEQ;
1483 }
1484 pr_debug("otg: HNP %s, %06x ...\n",
1485 state_name(isp), omap_readl(OTG_CTRL));
1486 check_state(isp, __func__);
1487 return 0;
1488#else
1489 /* srp-only */
1490 return -EINVAL;
1491#endif
1492}
1493
1494/*-------------------------------------------------------------------------*/
1495
1496static int
1497isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
1498{
1499 int status;
1500 struct isp1301 *isp;
1501
1502 if (the_transceiver)
1503 return 0;
1504
1505 isp = kzalloc(sizeof *isp, GFP_KERNEL);
1506 if (!isp)
1507 return 0;
1508
1509 isp->phy.otg = kzalloc(sizeof *isp->phy.otg, GFP_KERNEL);
1510 if (!isp->phy.otg) {
1511 kfree(isp);
1512 return 0;
1513 }
1514
1515 INIT_WORK(&isp->work, isp1301_work);
1516 init_timer(&isp->timer);
1517 isp->timer.function = isp1301_timer;
1518 isp->timer.data = (unsigned long) isp;
1519
1520 i2c_set_clientdata(i2c, isp);
1521 isp->client = i2c;
1522
1523 /* verify the chip (shouldn't be necessary) */
1524 status = isp1301_get_u16(isp, ISP1301_VENDOR_ID);
1525 if (status != I2C_VENDOR_ID_PHILIPS) {
1526 dev_dbg(&i2c->dev, "not philips id: %d\n", status);
1527 goto fail;
1528 }
1529 status = isp1301_get_u16(isp, ISP1301_PRODUCT_ID);
1530 if (status != I2C_PRODUCT_ID_PHILIPS_1301) {
1531 dev_dbg(&i2c->dev, "not isp1301, %d\n", status);
1532 goto fail;
1533 }
1534 isp->i2c_release = i2c->dev.release;
1535 i2c->dev.release = isp1301_release;
1536
1537 /* initial development used chiprev 2.00 */
1538 status = i2c_smbus_read_word_data(i2c, ISP1301_BCD_DEVICE);
1539 dev_info(&i2c->dev, "chiprev %x.%02x, driver " DRIVER_VERSION "\n",
1540 status >> 8, status & 0xff);
1541
1542 /* make like power-on reset */
1543 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_MASK);
1544
1545 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_BI_DI);
1546 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, ~MC2_BI_DI);
1547
1548 isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1,
1549 OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
1550 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
1551 ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
1552
1553 isp1301_clear_bits(isp, ISP1301_INTERRUPT_LATCH, ~0);
1554 isp1301_clear_bits(isp, ISP1301_INTERRUPT_FALLING, ~0);
1555 isp1301_clear_bits(isp, ISP1301_INTERRUPT_RISING, ~0);
1556
1557#ifdef CONFIG_USB_OTG
1558 status = otg_bind(isp);
1559 if (status < 0) {
1560 dev_dbg(&i2c->dev, "can't bind OTG\n");
1561 goto fail;
1562 }
1563#endif
1564
1565 if (machine_is_omap_h2()) {
1566 /* full speed signaling by default */
1567 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1,
1568 MC1_SPEED);
1569 isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2,
1570 MC2_SPD_SUSP_CTRL);
1571
1572 /* IRQ wired at M14 */
1573 omap_cfg_reg(M14_1510_GPIO2);
1574 if (gpio_request(2, "isp1301") == 0)
1575 gpio_direction_input(2);
1576 isp->irq_type = IRQF_TRIGGER_FALLING;
1577 }
1578
1579 status = request_irq(i2c->irq, isp1301_irq,
1580 isp->irq_type, DRIVER_NAME, isp);
1581 if (status < 0) {
1582 dev_dbg(&i2c->dev, "can't get IRQ %d, err %d\n",
1583 i2c->irq, status);
1584 goto fail;
1585 }
1586
1587 isp->phy.dev = &i2c->dev;
1588 isp->phy.label = DRIVER_NAME;
1589 isp->phy.set_power = isp1301_set_power,
1590
1591 isp->phy.otg->phy = &isp->phy;
1592 isp->phy.otg->set_host = isp1301_set_host,
1593 isp->phy.otg->set_peripheral = isp1301_set_peripheral,
1594 isp->phy.otg->start_srp = isp1301_start_srp,
1595 isp->phy.otg->start_hnp = isp1301_start_hnp,
1596
1597 enable_vbus_draw(isp, 0);
1598 power_down(isp);
1599 the_transceiver = isp;
1600
1601#ifdef CONFIG_USB_OTG
1602 update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
1603 update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
1604#endif
1605
1606 dump_regs(isp, __func__);
1607
1608#ifdef VERBOSE
1609 mod_timer(&isp->timer, jiffies + TIMER_JIFFIES);
1610 dev_dbg(&i2c->dev, "scheduled timer, %d min\n", TIMER_MINUTES);
1611#endif
1612
1613 status = usb_add_phy(&isp->phy, USB_PHY_TYPE_USB2);
1614 if (status < 0)
1615 dev_err(&i2c->dev, "can't register transceiver, %d\n",
1616 status);
1617
1618 return 0;
1619
1620fail:
1621 kfree(isp->phy.otg);
1622 kfree(isp);
1623 return -ENODEV;
1624}
1625
1626static const struct i2c_device_id isp1301_id[] = {
1627 { "isp1301_omap", 0 },
1628 { }
1629};
1630MODULE_DEVICE_TABLE(i2c, isp1301_id);
1631
1632static struct i2c_driver isp1301_driver = {
1633 .driver = {
1634 .name = "isp1301_omap",
1635 },
1636 .probe = isp1301_probe,
1637 .remove = __exit_p(isp1301_remove),
1638 .id_table = isp1301_id,
1639};
1640
1641/*-------------------------------------------------------------------------*/
1642
1643static int __init isp_init(void)
1644{
1645 return i2c_add_driver(&isp1301_driver);
1646}
1647subsys_initcall(isp_init);
1648
1649static void __exit isp_exit(void)
1650{
1651 if (the_transceiver)
1652 usb_remove_phy(&the_transceiver->phy);
1653 i2c_del_driver(&isp1301_driver);
1654}
1655module_exit(isp_exit);
1656
diff --git a/drivers/usb/phy/msm_otg.c b/drivers/usb/phy/msm_otg.c
new file mode 100644
index 000000000000..749fbf41fb6f
--- /dev/null
+++ b/drivers/usb/phy/msm_otg.c
@@ -0,0 +1,1762 @@
1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24#include <linux/interrupt.h>
25#include <linux/err.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/ioport.h>
29#include <linux/uaccess.h>
30#include <linux/debugfs.h>
31#include <linux/seq_file.h>
32#include <linux/pm_runtime.h>
33
34#include <linux/usb.h>
35#include <linux/usb/otg.h>
36#include <linux/usb/ulpi.h>
37#include <linux/usb/gadget.h>
38#include <linux/usb/hcd.h>
39#include <linux/usb/msm_hsusb.h>
40#include <linux/usb/msm_hsusb_hw.h>
41#include <linux/regulator/consumer.h>
42
43#include <mach/clk.h>
44
45#define MSM_USB_BASE (motg->regs)
46#define DRIVER_NAME "msm_otg"
47
48#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
49
50#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
51#define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
52#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
53#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
54
55#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
56#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
57#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
58#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
59
60#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
61#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
62
63static struct regulator *hsusb_3p3;
64static struct regulator *hsusb_1p8;
65static struct regulator *hsusb_vddcx;
66
67static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
68{
69 int ret = 0;
70
71 if (init) {
72 hsusb_vddcx = regulator_get(motg->phy.dev, "HSUSB_VDDCX");
73 if (IS_ERR(hsusb_vddcx)) {
74 dev_err(motg->phy.dev, "unable to get hsusb vddcx\n");
75 return PTR_ERR(hsusb_vddcx);
76 }
77
78 ret = regulator_set_voltage(hsusb_vddcx,
79 USB_PHY_VDD_DIG_VOL_MIN,
80 USB_PHY_VDD_DIG_VOL_MAX);
81 if (ret) {
82 dev_err(motg->phy.dev, "unable to set the voltage "
83 "for hsusb vddcx\n");
84 regulator_put(hsusb_vddcx);
85 return ret;
86 }
87
88 ret = regulator_enable(hsusb_vddcx);
89 if (ret) {
90 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
91 regulator_put(hsusb_vddcx);
92 }
93 } else {
94 ret = regulator_set_voltage(hsusb_vddcx, 0,
95 USB_PHY_VDD_DIG_VOL_MAX);
96 if (ret)
97 dev_err(motg->phy.dev, "unable to set the voltage "
98 "for hsusb vddcx\n");
99 ret = regulator_disable(hsusb_vddcx);
100 if (ret)
101 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
102
103 regulator_put(hsusb_vddcx);
104 }
105
106 return ret;
107}
108
109static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
110{
111 int rc = 0;
112
113 if (init) {
114 hsusb_3p3 = regulator_get(motg->phy.dev, "HSUSB_3p3");
115 if (IS_ERR(hsusb_3p3)) {
116 dev_err(motg->phy.dev, "unable to get hsusb 3p3\n");
117 return PTR_ERR(hsusb_3p3);
118 }
119
120 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
121 USB_PHY_3P3_VOL_MAX);
122 if (rc) {
123 dev_err(motg->phy.dev, "unable to set voltage level "
124 "for hsusb 3p3\n");
125 goto put_3p3;
126 }
127 rc = regulator_enable(hsusb_3p3);
128 if (rc) {
129 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
130 goto put_3p3;
131 }
132 hsusb_1p8 = regulator_get(motg->phy.dev, "HSUSB_1p8");
133 if (IS_ERR(hsusb_1p8)) {
134 dev_err(motg->phy.dev, "unable to get hsusb 1p8\n");
135 rc = PTR_ERR(hsusb_1p8);
136 goto disable_3p3;
137 }
138 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
139 USB_PHY_1P8_VOL_MAX);
140 if (rc) {
141 dev_err(motg->phy.dev, "unable to set voltage level "
142 "for hsusb 1p8\n");
143 goto put_1p8;
144 }
145 rc = regulator_enable(hsusb_1p8);
146 if (rc) {
147 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
148 goto put_1p8;
149 }
150
151 return 0;
152 }
153
154 regulator_disable(hsusb_1p8);
155put_1p8:
156 regulator_put(hsusb_1p8);
157disable_3p3:
158 regulator_disable(hsusb_3p3);
159put_3p3:
160 regulator_put(hsusb_3p3);
161 return rc;
162}
163
164#ifdef CONFIG_PM_SLEEP
165#define USB_PHY_SUSP_DIG_VOL 500000
166static int msm_hsusb_config_vddcx(int high)
167{
168 int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
169 int min_vol;
170 int ret;
171
172 if (high)
173 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
174 else
175 min_vol = USB_PHY_SUSP_DIG_VOL;
176
177 ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
178 if (ret) {
179 pr_err("%s: unable to set the voltage for regulator "
180 "HSUSB_VDDCX\n", __func__);
181 return ret;
182 }
183
184 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
185
186 return ret;
187}
188#endif
189
190static int msm_hsusb_ldo_set_mode(int on)
191{
192 int ret = 0;
193
194 if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
195 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
196 return -ENODEV;
197 }
198
199 if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
200 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
201 return -ENODEV;
202 }
203
204 if (on) {
205 ret = regulator_set_optimum_mode(hsusb_1p8,
206 USB_PHY_1P8_HPM_LOAD);
207 if (ret < 0) {
208 pr_err("%s: Unable to set HPM of the regulator "
209 "HSUSB_1p8\n", __func__);
210 return ret;
211 }
212 ret = regulator_set_optimum_mode(hsusb_3p3,
213 USB_PHY_3P3_HPM_LOAD);
214 if (ret < 0) {
215 pr_err("%s: Unable to set HPM of the regulator "
216 "HSUSB_3p3\n", __func__);
217 regulator_set_optimum_mode(hsusb_1p8,
218 USB_PHY_1P8_LPM_LOAD);
219 return ret;
220 }
221 } else {
222 ret = regulator_set_optimum_mode(hsusb_1p8,
223 USB_PHY_1P8_LPM_LOAD);
224 if (ret < 0)
225 pr_err("%s: Unable to set LPM of the regulator "
226 "HSUSB_1p8\n", __func__);
227 ret = regulator_set_optimum_mode(hsusb_3p3,
228 USB_PHY_3P3_LPM_LOAD);
229 if (ret < 0)
230 pr_err("%s: Unable to set LPM of the regulator "
231 "HSUSB_3p3\n", __func__);
232 }
233
234 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
235 return ret < 0 ? ret : 0;
236}
237
238static int ulpi_read(struct usb_phy *phy, u32 reg)
239{
240 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
241 int cnt = 0;
242
243 /* initiate read operation */
244 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
245 USB_ULPI_VIEWPORT);
246
247 /* wait for completion */
248 while (cnt < ULPI_IO_TIMEOUT_USEC) {
249 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
250 break;
251 udelay(1);
252 cnt++;
253 }
254
255 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
256 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
257 readl(USB_ULPI_VIEWPORT));
258 return -ETIMEDOUT;
259 }
260 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
261}
262
263static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
264{
265 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
266 int cnt = 0;
267
268 /* initiate write operation */
269 writel(ULPI_RUN | ULPI_WRITE |
270 ULPI_ADDR(reg) | ULPI_DATA(val),
271 USB_ULPI_VIEWPORT);
272
273 /* wait for completion */
274 while (cnt < ULPI_IO_TIMEOUT_USEC) {
275 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
276 break;
277 udelay(1);
278 cnt++;
279 }
280
281 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
282 dev_err(phy->dev, "ulpi_write: timeout\n");
283 return -ETIMEDOUT;
284 }
285 return 0;
286}
287
288static struct usb_phy_io_ops msm_otg_io_ops = {
289 .read = ulpi_read,
290 .write = ulpi_write,
291};
292
293static void ulpi_init(struct msm_otg *motg)
294{
295 struct msm_otg_platform_data *pdata = motg->pdata;
296 int *seq = pdata->phy_init_seq;
297
298 if (!seq)
299 return;
300
301 while (seq[0] >= 0) {
302 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
303 seq[0], seq[1]);
304 ulpi_write(&motg->phy, seq[0], seq[1]);
305 seq += 2;
306 }
307}
308
309static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
310{
311 int ret;
312
313 if (assert) {
314 ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
315 if (ret)
316 dev_err(motg->phy.dev, "usb hs_clk assert failed\n");
317 } else {
318 ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
319 if (ret)
320 dev_err(motg->phy.dev, "usb hs_clk deassert failed\n");
321 }
322 return ret;
323}
324
325static int msm_otg_phy_clk_reset(struct msm_otg *motg)
326{
327 int ret;
328
329 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_ASSERT);
330 if (ret) {
331 dev_err(motg->phy.dev, "usb phy clk assert failed\n");
332 return ret;
333 }
334 usleep_range(10000, 12000);
335 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_DEASSERT);
336 if (ret)
337 dev_err(motg->phy.dev, "usb phy clk deassert failed\n");
338 return ret;
339}
340
341static int msm_otg_phy_reset(struct msm_otg *motg)
342{
343 u32 val;
344 int ret;
345 int retries;
346
347 ret = msm_otg_link_clk_reset(motg, 1);
348 if (ret)
349 return ret;
350 ret = msm_otg_phy_clk_reset(motg);
351 if (ret)
352 return ret;
353 ret = msm_otg_link_clk_reset(motg, 0);
354 if (ret)
355 return ret;
356
357 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
358 writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
359
360 for (retries = 3; retries > 0; retries--) {
361 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM,
362 ULPI_CLR(ULPI_FUNC_CTRL));
363 if (!ret)
364 break;
365 ret = msm_otg_phy_clk_reset(motg);
366 if (ret)
367 return ret;
368 }
369 if (!retries)
370 return -ETIMEDOUT;
371
372 /* This reset calibrates the phy, if the above write succeeded */
373 ret = msm_otg_phy_clk_reset(motg);
374 if (ret)
375 return ret;
376
377 for (retries = 3; retries > 0; retries--) {
378 ret = ulpi_read(&motg->phy, ULPI_DEBUG);
379 if (ret != -ETIMEDOUT)
380 break;
381 ret = msm_otg_phy_clk_reset(motg);
382 if (ret)
383 return ret;
384 }
385 if (!retries)
386 return -ETIMEDOUT;
387
388 dev_info(motg->phy.dev, "phy_reset: success\n");
389 return 0;
390}
391
392#define LINK_RESET_TIMEOUT_USEC (250 * 1000)
393static int msm_otg_reset(struct usb_phy *phy)
394{
395 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
396 struct msm_otg_platform_data *pdata = motg->pdata;
397 int cnt = 0;
398 int ret;
399 u32 val = 0;
400 u32 ulpi_val = 0;
401
402 ret = msm_otg_phy_reset(motg);
403 if (ret) {
404 dev_err(phy->dev, "phy_reset failed\n");
405 return ret;
406 }
407
408 ulpi_init(motg);
409
410 writel(USBCMD_RESET, USB_USBCMD);
411 while (cnt < LINK_RESET_TIMEOUT_USEC) {
412 if (!(readl(USB_USBCMD) & USBCMD_RESET))
413 break;
414 udelay(1);
415 cnt++;
416 }
417 if (cnt >= LINK_RESET_TIMEOUT_USEC)
418 return -ETIMEDOUT;
419
420 /* select ULPI phy */
421 writel(0x80000000, USB_PORTSC);
422
423 msleep(100);
424
425 writel(0x0, USB_AHBBURST);
426 writel(0x00, USB_AHBMODE);
427
428 if (pdata->otg_control == OTG_PHY_CONTROL) {
429 val = readl(USB_OTGSC);
430 if (pdata->mode == USB_OTG) {
431 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
432 val |= OTGSC_IDIE | OTGSC_BSVIE;
433 } else if (pdata->mode == USB_PERIPHERAL) {
434 ulpi_val = ULPI_INT_SESS_VALID;
435 val |= OTGSC_BSVIE;
436 }
437 writel(val, USB_OTGSC);
438 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
439 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
440 }
441
442 return 0;
443}
444
445#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
446#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
447
448#ifdef CONFIG_PM_SLEEP
449static int msm_otg_suspend(struct msm_otg *motg)
450{
451 struct usb_phy *phy = &motg->phy;
452 struct usb_bus *bus = phy->otg->host;
453 struct msm_otg_platform_data *pdata = motg->pdata;
454 int cnt = 0;
455
456 if (atomic_read(&motg->in_lpm))
457 return 0;
458
459 disable_irq(motg->irq);
460 /*
461 * Chipidea 45-nm PHY suspend sequence:
462 *
463 * Interrupt Latch Register auto-clear feature is not present
464 * in all PHY versions. Latch register is clear on read type.
465 * Clear latch register to avoid spurious wakeup from
466 * low power mode (LPM).
467 *
468 * PHY comparators are disabled when PHY enters into low power
469 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
470 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
471 * PHY comparators. This save significant amount of power.
472 *
473 * PLL is not turned off when PHY enters into low power mode (LPM).
474 * Disable PLL for maximum power savings.
475 */
476
477 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
478 ulpi_read(phy, 0x14);
479 if (pdata->otg_control == OTG_PHY_CONTROL)
480 ulpi_write(phy, 0x01, 0x30);
481 ulpi_write(phy, 0x08, 0x09);
482 }
483
484 /*
485 * PHY may take some time or even fail to enter into low power
486 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
487 * in failure case.
488 */
489 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
490 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
491 if (readl(USB_PORTSC) & PORTSC_PHCD)
492 break;
493 udelay(1);
494 cnt++;
495 }
496
497 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
498 dev_err(phy->dev, "Unable to suspend PHY\n");
499 msm_otg_reset(phy);
500 enable_irq(motg->irq);
501 return -ETIMEDOUT;
502 }
503
504 /*
505 * PHY has capability to generate interrupt asynchronously in low
506 * power mode (LPM). This interrupt is level triggered. So USB IRQ
507 * line must be disabled till async interrupt enable bit is cleared
508 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
509 * block data communication from PHY.
510 */
511 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
512
513 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
514 motg->pdata->otg_control == OTG_PMIC_CONTROL)
515 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
516
517 clk_disable(motg->pclk);
518 clk_disable(motg->clk);
519 if (motg->core_clk)
520 clk_disable(motg->core_clk);
521
522 if (!IS_ERR(motg->pclk_src))
523 clk_disable(motg->pclk_src);
524
525 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
526 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
527 msm_hsusb_ldo_set_mode(0);
528 msm_hsusb_config_vddcx(0);
529 }
530
531 if (device_may_wakeup(phy->dev))
532 enable_irq_wake(motg->irq);
533 if (bus)
534 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
535
536 atomic_set(&motg->in_lpm, 1);
537 enable_irq(motg->irq);
538
539 dev_info(phy->dev, "USB in low power mode\n");
540
541 return 0;
542}
543
544static int msm_otg_resume(struct msm_otg *motg)
545{
546 struct usb_phy *phy = &motg->phy;
547 struct usb_bus *bus = phy->otg->host;
548 int cnt = 0;
549 unsigned temp;
550
551 if (!atomic_read(&motg->in_lpm))
552 return 0;
553
554 if (!IS_ERR(motg->pclk_src))
555 clk_enable(motg->pclk_src);
556
557 clk_enable(motg->pclk);
558 clk_enable(motg->clk);
559 if (motg->core_clk)
560 clk_enable(motg->core_clk);
561
562 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
563 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
564 msm_hsusb_ldo_set_mode(1);
565 msm_hsusb_config_vddcx(1);
566 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
567 }
568
569 temp = readl(USB_USBCMD);
570 temp &= ~ASYNC_INTR_CTRL;
571 temp &= ~ULPI_STP_CTRL;
572 writel(temp, USB_USBCMD);
573
574 /*
575 * PHY comes out of low power mode (LPM) in case of wakeup
576 * from asynchronous interrupt.
577 */
578 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
579 goto skip_phy_resume;
580
581 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
582 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
583 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
584 break;
585 udelay(1);
586 cnt++;
587 }
588
589 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
590 /*
591 * This is a fatal error. Reset the link and
592 * PHY. USB state can not be restored. Re-insertion
593 * of USB cable is the only way to get USB working.
594 */
595 dev_err(phy->dev, "Unable to resume USB."
596 "Re-plugin the cable\n");
597 msm_otg_reset(phy);
598 }
599
600skip_phy_resume:
601 if (device_may_wakeup(phy->dev))
602 disable_irq_wake(motg->irq);
603 if (bus)
604 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
605
606 atomic_set(&motg->in_lpm, 0);
607
608 if (motg->async_int) {
609 motg->async_int = 0;
610 pm_runtime_put(phy->dev);
611 enable_irq(motg->irq);
612 }
613
614 dev_info(phy->dev, "USB exited from low power mode\n");
615
616 return 0;
617}
618#endif
619
620static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
621{
622 if (motg->cur_power == mA)
623 return;
624
625 /* TODO: Notify PMIC about available current */
626 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
627 motg->cur_power = mA;
628}
629
630static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
631{
632 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
633
634 /*
635 * Gadget driver uses set_power method to notify about the
636 * available current based on suspend/configured states.
637 *
638 * IDEV_CHG can be drawn irrespective of suspend/un-configured
639 * states when CDP/ACA is connected.
640 */
641 if (motg->chg_type == USB_SDP_CHARGER)
642 msm_otg_notify_charger(motg, mA);
643
644 return 0;
645}
646
647static void msm_otg_start_host(struct usb_phy *phy, int on)
648{
649 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
650 struct msm_otg_platform_data *pdata = motg->pdata;
651 struct usb_hcd *hcd;
652
653 if (!phy->otg->host)
654 return;
655
656 hcd = bus_to_hcd(phy->otg->host);
657
658 if (on) {
659 dev_dbg(phy->dev, "host on\n");
660
661 if (pdata->vbus_power)
662 pdata->vbus_power(1);
663 /*
664 * Some boards have a switch cotrolled by gpio
665 * to enable/disable internal HUB. Enable internal
666 * HUB before kicking the host.
667 */
668 if (pdata->setup_gpio)
669 pdata->setup_gpio(OTG_STATE_A_HOST);
670#ifdef CONFIG_USB
671 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
672#endif
673 } else {
674 dev_dbg(phy->dev, "host off\n");
675
676#ifdef CONFIG_USB
677 usb_remove_hcd(hcd);
678#endif
679 if (pdata->setup_gpio)
680 pdata->setup_gpio(OTG_STATE_UNDEFINED);
681 if (pdata->vbus_power)
682 pdata->vbus_power(0);
683 }
684}
685
686static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
687{
688 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
689 struct usb_hcd *hcd;
690
691 /*
692 * Fail host registration if this board can support
693 * only peripheral configuration.
694 */
695 if (motg->pdata->mode == USB_PERIPHERAL) {
696 dev_info(otg->phy->dev, "Host mode is not supported\n");
697 return -ENODEV;
698 }
699
700 if (!host) {
701 if (otg->phy->state == OTG_STATE_A_HOST) {
702 pm_runtime_get_sync(otg->phy->dev);
703 msm_otg_start_host(otg->phy, 0);
704 otg->host = NULL;
705 otg->phy->state = OTG_STATE_UNDEFINED;
706 schedule_work(&motg->sm_work);
707 } else {
708 otg->host = NULL;
709 }
710
711 return 0;
712 }
713
714 hcd = bus_to_hcd(host);
715 hcd->power_budget = motg->pdata->power_budget;
716
717 otg->host = host;
718 dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
719
720 /*
721 * Kick the state machine work, if peripheral is not supported
722 * or peripheral is already registered with us.
723 */
724 if (motg->pdata->mode == USB_HOST || otg->gadget) {
725 pm_runtime_get_sync(otg->phy->dev);
726 schedule_work(&motg->sm_work);
727 }
728
729 return 0;
730}
731
732static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
733{
734 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
735 struct msm_otg_platform_data *pdata = motg->pdata;
736
737 if (!phy->otg->gadget)
738 return;
739
740 if (on) {
741 dev_dbg(phy->dev, "gadget on\n");
742 /*
743 * Some boards have a switch cotrolled by gpio
744 * to enable/disable internal HUB. Disable internal
745 * HUB before kicking the gadget.
746 */
747 if (pdata->setup_gpio)
748 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
749 usb_gadget_vbus_connect(phy->otg->gadget);
750 } else {
751 dev_dbg(phy->dev, "gadget off\n");
752 usb_gadget_vbus_disconnect(phy->otg->gadget);
753 if (pdata->setup_gpio)
754 pdata->setup_gpio(OTG_STATE_UNDEFINED);
755 }
756
757}
758
759static int msm_otg_set_peripheral(struct usb_otg *otg,
760 struct usb_gadget *gadget)
761{
762 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
763
764 /*
765 * Fail peripheral registration if this board can support
766 * only host configuration.
767 */
768 if (motg->pdata->mode == USB_HOST) {
769 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
770 return -ENODEV;
771 }
772
773 if (!gadget) {
774 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
775 pm_runtime_get_sync(otg->phy->dev);
776 msm_otg_start_peripheral(otg->phy, 0);
777 otg->gadget = NULL;
778 otg->phy->state = OTG_STATE_UNDEFINED;
779 schedule_work(&motg->sm_work);
780 } else {
781 otg->gadget = NULL;
782 }
783
784 return 0;
785 }
786 otg->gadget = gadget;
787 dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
788
789 /*
790 * Kick the state machine work, if host is not supported
791 * or host is already registered with us.
792 */
793 if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
794 pm_runtime_get_sync(otg->phy->dev);
795 schedule_work(&motg->sm_work);
796 }
797
798 return 0;
799}
800
801static bool msm_chg_check_secondary_det(struct msm_otg *motg)
802{
803 struct usb_phy *phy = &motg->phy;
804 u32 chg_det;
805 bool ret = false;
806
807 switch (motg->pdata->phy_type) {
808 case CI_45NM_INTEGRATED_PHY:
809 chg_det = ulpi_read(phy, 0x34);
810 ret = chg_det & (1 << 4);
811 break;
812 case SNPS_28NM_INTEGRATED_PHY:
813 chg_det = ulpi_read(phy, 0x87);
814 ret = chg_det & 1;
815 break;
816 default:
817 break;
818 }
819 return ret;
820}
821
822static void msm_chg_enable_secondary_det(struct msm_otg *motg)
823{
824 struct usb_phy *phy = &motg->phy;
825 u32 chg_det;
826
827 switch (motg->pdata->phy_type) {
828 case CI_45NM_INTEGRATED_PHY:
829 chg_det = ulpi_read(phy, 0x34);
830 /* Turn off charger block */
831 chg_det |= ~(1 << 1);
832 ulpi_write(phy, chg_det, 0x34);
833 udelay(20);
834 /* control chg block via ULPI */
835 chg_det &= ~(1 << 3);
836 ulpi_write(phy, chg_det, 0x34);
837 /* put it in host mode for enabling D- source */
838 chg_det &= ~(1 << 2);
839 ulpi_write(phy, chg_det, 0x34);
840 /* Turn on chg detect block */
841 chg_det &= ~(1 << 1);
842 ulpi_write(phy, chg_det, 0x34);
843 udelay(20);
844 /* enable chg detection */
845 chg_det &= ~(1 << 0);
846 ulpi_write(phy, chg_det, 0x34);
847 break;
848 case SNPS_28NM_INTEGRATED_PHY:
849 /*
850 * Configure DM as current source, DP as current sink
851 * and enable battery charging comparators.
852 */
853 ulpi_write(phy, 0x8, 0x85);
854 ulpi_write(phy, 0x2, 0x85);
855 ulpi_write(phy, 0x1, 0x85);
856 break;
857 default:
858 break;
859 }
860}
861
862static bool msm_chg_check_primary_det(struct msm_otg *motg)
863{
864 struct usb_phy *phy = &motg->phy;
865 u32 chg_det;
866 bool ret = false;
867
868 switch (motg->pdata->phy_type) {
869 case CI_45NM_INTEGRATED_PHY:
870 chg_det = ulpi_read(phy, 0x34);
871 ret = chg_det & (1 << 4);
872 break;
873 case SNPS_28NM_INTEGRATED_PHY:
874 chg_det = ulpi_read(phy, 0x87);
875 ret = chg_det & 1;
876 break;
877 default:
878 break;
879 }
880 return ret;
881}
882
883static void msm_chg_enable_primary_det(struct msm_otg *motg)
884{
885 struct usb_phy *phy = &motg->phy;
886 u32 chg_det;
887
888 switch (motg->pdata->phy_type) {
889 case CI_45NM_INTEGRATED_PHY:
890 chg_det = ulpi_read(phy, 0x34);
891 /* enable chg detection */
892 chg_det &= ~(1 << 0);
893 ulpi_write(phy, chg_det, 0x34);
894 break;
895 case SNPS_28NM_INTEGRATED_PHY:
896 /*
897 * Configure DP as current source, DM as current sink
898 * and enable battery charging comparators.
899 */
900 ulpi_write(phy, 0x2, 0x85);
901 ulpi_write(phy, 0x1, 0x85);
902 break;
903 default:
904 break;
905 }
906}
907
908static bool msm_chg_check_dcd(struct msm_otg *motg)
909{
910 struct usb_phy *phy = &motg->phy;
911 u32 line_state;
912 bool ret = false;
913
914 switch (motg->pdata->phy_type) {
915 case CI_45NM_INTEGRATED_PHY:
916 line_state = ulpi_read(phy, 0x15);
917 ret = !(line_state & 1);
918 break;
919 case SNPS_28NM_INTEGRATED_PHY:
920 line_state = ulpi_read(phy, 0x87);
921 ret = line_state & 2;
922 break;
923 default:
924 break;
925 }
926 return ret;
927}
928
929static void msm_chg_disable_dcd(struct msm_otg *motg)
930{
931 struct usb_phy *phy = &motg->phy;
932 u32 chg_det;
933
934 switch (motg->pdata->phy_type) {
935 case CI_45NM_INTEGRATED_PHY:
936 chg_det = ulpi_read(phy, 0x34);
937 chg_det &= ~(1 << 5);
938 ulpi_write(phy, chg_det, 0x34);
939 break;
940 case SNPS_28NM_INTEGRATED_PHY:
941 ulpi_write(phy, 0x10, 0x86);
942 break;
943 default:
944 break;
945 }
946}
947
948static void msm_chg_enable_dcd(struct msm_otg *motg)
949{
950 struct usb_phy *phy = &motg->phy;
951 u32 chg_det;
952
953 switch (motg->pdata->phy_type) {
954 case CI_45NM_INTEGRATED_PHY:
955 chg_det = ulpi_read(phy, 0x34);
956 /* Turn on D+ current source */
957 chg_det |= (1 << 5);
958 ulpi_write(phy, chg_det, 0x34);
959 break;
960 case SNPS_28NM_INTEGRATED_PHY:
961 /* Data contact detection enable */
962 ulpi_write(phy, 0x10, 0x85);
963 break;
964 default:
965 break;
966 }
967}
968
969static void msm_chg_block_on(struct msm_otg *motg)
970{
971 struct usb_phy *phy = &motg->phy;
972 u32 func_ctrl, chg_det;
973
974 /* put the controller in non-driving mode */
975 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
976 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
977 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
978 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
979
980 switch (motg->pdata->phy_type) {
981 case CI_45NM_INTEGRATED_PHY:
982 chg_det = ulpi_read(phy, 0x34);
983 /* control chg block via ULPI */
984 chg_det &= ~(1 << 3);
985 ulpi_write(phy, chg_det, 0x34);
986 /* Turn on chg detect block */
987 chg_det &= ~(1 << 1);
988 ulpi_write(phy, chg_det, 0x34);
989 udelay(20);
990 break;
991 case SNPS_28NM_INTEGRATED_PHY:
992 /* Clear charger detecting control bits */
993 ulpi_write(phy, 0x3F, 0x86);
994 /* Clear alt interrupt latch and enable bits */
995 ulpi_write(phy, 0x1F, 0x92);
996 ulpi_write(phy, 0x1F, 0x95);
997 udelay(100);
998 break;
999 default:
1000 break;
1001 }
1002}
1003
1004static void msm_chg_block_off(struct msm_otg *motg)
1005{
1006 struct usb_phy *phy = &motg->phy;
1007 u32 func_ctrl, chg_det;
1008
1009 switch (motg->pdata->phy_type) {
1010 case CI_45NM_INTEGRATED_PHY:
1011 chg_det = ulpi_read(phy, 0x34);
1012 /* Turn off charger block */
1013 chg_det |= ~(1 << 1);
1014 ulpi_write(phy, chg_det, 0x34);
1015 break;
1016 case SNPS_28NM_INTEGRATED_PHY:
1017 /* Clear charger detecting control bits */
1018 ulpi_write(phy, 0x3F, 0x86);
1019 /* Clear alt interrupt latch and enable bits */
1020 ulpi_write(phy, 0x1F, 0x92);
1021 ulpi_write(phy, 0x1F, 0x95);
1022 break;
1023 default:
1024 break;
1025 }
1026
1027 /* put the controller in normal mode */
1028 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1029 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1030 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1031 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1032}
1033
1034#define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1035#define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1036#define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1037#define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1038static void msm_chg_detect_work(struct work_struct *w)
1039{
1040 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1041 struct usb_phy *phy = &motg->phy;
1042 bool is_dcd, tmout, vout;
1043 unsigned long delay;
1044
1045 dev_dbg(phy->dev, "chg detection work\n");
1046 switch (motg->chg_state) {
1047 case USB_CHG_STATE_UNDEFINED:
1048 pm_runtime_get_sync(phy->dev);
1049 msm_chg_block_on(motg);
1050 msm_chg_enable_dcd(motg);
1051 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1052 motg->dcd_retries = 0;
1053 delay = MSM_CHG_DCD_POLL_TIME;
1054 break;
1055 case USB_CHG_STATE_WAIT_FOR_DCD:
1056 is_dcd = msm_chg_check_dcd(motg);
1057 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1058 if (is_dcd || tmout) {
1059 msm_chg_disable_dcd(motg);
1060 msm_chg_enable_primary_det(motg);
1061 delay = MSM_CHG_PRIMARY_DET_TIME;
1062 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1063 } else {
1064 delay = MSM_CHG_DCD_POLL_TIME;
1065 }
1066 break;
1067 case USB_CHG_STATE_DCD_DONE:
1068 vout = msm_chg_check_primary_det(motg);
1069 if (vout) {
1070 msm_chg_enable_secondary_det(motg);
1071 delay = MSM_CHG_SECONDARY_DET_TIME;
1072 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1073 } else {
1074 motg->chg_type = USB_SDP_CHARGER;
1075 motg->chg_state = USB_CHG_STATE_DETECTED;
1076 delay = 0;
1077 }
1078 break;
1079 case USB_CHG_STATE_PRIMARY_DONE:
1080 vout = msm_chg_check_secondary_det(motg);
1081 if (vout)
1082 motg->chg_type = USB_DCP_CHARGER;
1083 else
1084 motg->chg_type = USB_CDP_CHARGER;
1085 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1086 /* fall through */
1087 case USB_CHG_STATE_SECONDARY_DONE:
1088 motg->chg_state = USB_CHG_STATE_DETECTED;
1089 case USB_CHG_STATE_DETECTED:
1090 msm_chg_block_off(motg);
1091 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1092 schedule_work(&motg->sm_work);
1093 return;
1094 default:
1095 return;
1096 }
1097
1098 schedule_delayed_work(&motg->chg_work, delay);
1099}
1100
1101/*
1102 * We support OTG, Peripheral only and Host only configurations. In case
1103 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1104 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1105 * enabled when switch is controlled by user and default mode is supplied
1106 * by board file, which can be changed by userspace later.
1107 */
1108static void msm_otg_init_sm(struct msm_otg *motg)
1109{
1110 struct msm_otg_platform_data *pdata = motg->pdata;
1111 u32 otgsc = readl(USB_OTGSC);
1112
1113 switch (pdata->mode) {
1114 case USB_OTG:
1115 if (pdata->otg_control == OTG_PHY_CONTROL) {
1116 if (otgsc & OTGSC_ID)
1117 set_bit(ID, &motg->inputs);
1118 else
1119 clear_bit(ID, &motg->inputs);
1120
1121 if (otgsc & OTGSC_BSV)
1122 set_bit(B_SESS_VLD, &motg->inputs);
1123 else
1124 clear_bit(B_SESS_VLD, &motg->inputs);
1125 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1126 if (pdata->default_mode == USB_HOST) {
1127 clear_bit(ID, &motg->inputs);
1128 } else if (pdata->default_mode == USB_PERIPHERAL) {
1129 set_bit(ID, &motg->inputs);
1130 set_bit(B_SESS_VLD, &motg->inputs);
1131 } else {
1132 set_bit(ID, &motg->inputs);
1133 clear_bit(B_SESS_VLD, &motg->inputs);
1134 }
1135 }
1136 break;
1137 case USB_HOST:
1138 clear_bit(ID, &motg->inputs);
1139 break;
1140 case USB_PERIPHERAL:
1141 set_bit(ID, &motg->inputs);
1142 if (otgsc & OTGSC_BSV)
1143 set_bit(B_SESS_VLD, &motg->inputs);
1144 else
1145 clear_bit(B_SESS_VLD, &motg->inputs);
1146 break;
1147 default:
1148 break;
1149 }
1150}
1151
1152static void msm_otg_sm_work(struct work_struct *w)
1153{
1154 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1155 struct usb_otg *otg = motg->phy.otg;
1156
1157 switch (otg->phy->state) {
1158 case OTG_STATE_UNDEFINED:
1159 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1160 msm_otg_reset(otg->phy);
1161 msm_otg_init_sm(motg);
1162 otg->phy->state = OTG_STATE_B_IDLE;
1163 /* FALL THROUGH */
1164 case OTG_STATE_B_IDLE:
1165 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1166 if (!test_bit(ID, &motg->inputs) && otg->host) {
1167 /* disable BSV bit */
1168 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1169 msm_otg_start_host(otg->phy, 1);
1170 otg->phy->state = OTG_STATE_A_HOST;
1171 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1172 switch (motg->chg_state) {
1173 case USB_CHG_STATE_UNDEFINED:
1174 msm_chg_detect_work(&motg->chg_work.work);
1175 break;
1176 case USB_CHG_STATE_DETECTED:
1177 switch (motg->chg_type) {
1178 case USB_DCP_CHARGER:
1179 msm_otg_notify_charger(motg,
1180 IDEV_CHG_MAX);
1181 break;
1182 case USB_CDP_CHARGER:
1183 msm_otg_notify_charger(motg,
1184 IDEV_CHG_MAX);
1185 msm_otg_start_peripheral(otg->phy, 1);
1186 otg->phy->state
1187 = OTG_STATE_B_PERIPHERAL;
1188 break;
1189 case USB_SDP_CHARGER:
1190 msm_otg_notify_charger(motg, IUNIT);
1191 msm_otg_start_peripheral(otg->phy, 1);
1192 otg->phy->state
1193 = OTG_STATE_B_PERIPHERAL;
1194 break;
1195 default:
1196 break;
1197 }
1198 break;
1199 default:
1200 break;
1201 }
1202 } else {
1203 /*
1204 * If charger detection work is pending, decrement
1205 * the pm usage counter to balance with the one that
1206 * is incremented in charger detection work.
1207 */
1208 if (cancel_delayed_work_sync(&motg->chg_work)) {
1209 pm_runtime_put_sync(otg->phy->dev);
1210 msm_otg_reset(otg->phy);
1211 }
1212 msm_otg_notify_charger(motg, 0);
1213 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1214 motg->chg_type = USB_INVALID_CHARGER;
1215 }
1216 pm_runtime_put_sync(otg->phy->dev);
1217 break;
1218 case OTG_STATE_B_PERIPHERAL:
1219 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1220 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1221 !test_bit(ID, &motg->inputs)) {
1222 msm_otg_notify_charger(motg, 0);
1223 msm_otg_start_peripheral(otg->phy, 0);
1224 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1225 motg->chg_type = USB_INVALID_CHARGER;
1226 otg->phy->state = OTG_STATE_B_IDLE;
1227 msm_otg_reset(otg->phy);
1228 schedule_work(w);
1229 }
1230 break;
1231 case OTG_STATE_A_HOST:
1232 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1233 if (test_bit(ID, &motg->inputs)) {
1234 msm_otg_start_host(otg->phy, 0);
1235 otg->phy->state = OTG_STATE_B_IDLE;
1236 msm_otg_reset(otg->phy);
1237 schedule_work(w);
1238 }
1239 break;
1240 default:
1241 break;
1242 }
1243}
1244
1245static irqreturn_t msm_otg_irq(int irq, void *data)
1246{
1247 struct msm_otg *motg = data;
1248 struct usb_phy *phy = &motg->phy;
1249 u32 otgsc = 0;
1250
1251 if (atomic_read(&motg->in_lpm)) {
1252 disable_irq_nosync(irq);
1253 motg->async_int = 1;
1254 pm_runtime_get(phy->dev);
1255 return IRQ_HANDLED;
1256 }
1257
1258 otgsc = readl(USB_OTGSC);
1259 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1260 return IRQ_NONE;
1261
1262 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1263 if (otgsc & OTGSC_ID)
1264 set_bit(ID, &motg->inputs);
1265 else
1266 clear_bit(ID, &motg->inputs);
1267 dev_dbg(phy->dev, "ID set/clear\n");
1268 pm_runtime_get_noresume(phy->dev);
1269 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1270 if (otgsc & OTGSC_BSV)
1271 set_bit(B_SESS_VLD, &motg->inputs);
1272 else
1273 clear_bit(B_SESS_VLD, &motg->inputs);
1274 dev_dbg(phy->dev, "BSV set/clear\n");
1275 pm_runtime_get_noresume(phy->dev);
1276 }
1277
1278 writel(otgsc, USB_OTGSC);
1279 schedule_work(&motg->sm_work);
1280 return IRQ_HANDLED;
1281}
1282
1283static int msm_otg_mode_show(struct seq_file *s, void *unused)
1284{
1285 struct msm_otg *motg = s->private;
1286 struct usb_otg *otg = motg->phy.otg;
1287
1288 switch (otg->phy->state) {
1289 case OTG_STATE_A_HOST:
1290 seq_printf(s, "host\n");
1291 break;
1292 case OTG_STATE_B_PERIPHERAL:
1293 seq_printf(s, "peripheral\n");
1294 break;
1295 default:
1296 seq_printf(s, "none\n");
1297 break;
1298 }
1299
1300 return 0;
1301}
1302
1303static int msm_otg_mode_open(struct inode *inode, struct file *file)
1304{
1305 return single_open(file, msm_otg_mode_show, inode->i_private);
1306}
1307
1308static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1309 size_t count, loff_t *ppos)
1310{
1311 struct seq_file *s = file->private_data;
1312 struct msm_otg *motg = s->private;
1313 char buf[16];
1314 struct usb_otg *otg = motg->phy.otg;
1315 int status = count;
1316 enum usb_mode_type req_mode;
1317
1318 memset(buf, 0x00, sizeof(buf));
1319
1320 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1321 status = -EFAULT;
1322 goto out;
1323 }
1324
1325 if (!strncmp(buf, "host", 4)) {
1326 req_mode = USB_HOST;
1327 } else if (!strncmp(buf, "peripheral", 10)) {
1328 req_mode = USB_PERIPHERAL;
1329 } else if (!strncmp(buf, "none", 4)) {
1330 req_mode = USB_NONE;
1331 } else {
1332 status = -EINVAL;
1333 goto out;
1334 }
1335
1336 switch (req_mode) {
1337 case USB_NONE:
1338 switch (otg->phy->state) {
1339 case OTG_STATE_A_HOST:
1340 case OTG_STATE_B_PERIPHERAL:
1341 set_bit(ID, &motg->inputs);
1342 clear_bit(B_SESS_VLD, &motg->inputs);
1343 break;
1344 default:
1345 goto out;
1346 }
1347 break;
1348 case USB_PERIPHERAL:
1349 switch (otg->phy->state) {
1350 case OTG_STATE_B_IDLE:
1351 case OTG_STATE_A_HOST:
1352 set_bit(ID, &motg->inputs);
1353 set_bit(B_SESS_VLD, &motg->inputs);
1354 break;
1355 default:
1356 goto out;
1357 }
1358 break;
1359 case USB_HOST:
1360 switch (otg->phy->state) {
1361 case OTG_STATE_B_IDLE:
1362 case OTG_STATE_B_PERIPHERAL:
1363 clear_bit(ID, &motg->inputs);
1364 break;
1365 default:
1366 goto out;
1367 }
1368 break;
1369 default:
1370 goto out;
1371 }
1372
1373 pm_runtime_get_sync(otg->phy->dev);
1374 schedule_work(&motg->sm_work);
1375out:
1376 return status;
1377}
1378
1379const struct file_operations msm_otg_mode_fops = {
1380 .open = msm_otg_mode_open,
1381 .read = seq_read,
1382 .write = msm_otg_mode_write,
1383 .llseek = seq_lseek,
1384 .release = single_release,
1385};
1386
1387static struct dentry *msm_otg_dbg_root;
1388static struct dentry *msm_otg_dbg_mode;
1389
1390static int msm_otg_debugfs_init(struct msm_otg *motg)
1391{
1392 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1393
1394 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1395 return -ENODEV;
1396
1397 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1398 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1399 if (!msm_otg_dbg_mode) {
1400 debugfs_remove(msm_otg_dbg_root);
1401 msm_otg_dbg_root = NULL;
1402 return -ENODEV;
1403 }
1404
1405 return 0;
1406}
1407
1408static void msm_otg_debugfs_cleanup(void)
1409{
1410 debugfs_remove(msm_otg_dbg_mode);
1411 debugfs_remove(msm_otg_dbg_root);
1412}
1413
1414static int __init msm_otg_probe(struct platform_device *pdev)
1415{
1416 int ret = 0;
1417 struct resource *res;
1418 struct msm_otg *motg;
1419 struct usb_phy *phy;
1420
1421 dev_info(&pdev->dev, "msm_otg probe\n");
1422 if (!pdev->dev.platform_data) {
1423 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1424 return -ENODEV;
1425 }
1426
1427 motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1428 if (!motg) {
1429 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1430 return -ENOMEM;
1431 }
1432
1433 motg->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
1434 if (!motg->phy.otg) {
1435 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1436 return -ENOMEM;
1437 }
1438
1439 motg->pdata = pdev->dev.platform_data;
1440 phy = &motg->phy;
1441 phy->dev = &pdev->dev;
1442
1443 motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
1444 if (IS_ERR(motg->phy_reset_clk)) {
1445 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1446 ret = PTR_ERR(motg->phy_reset_clk);
1447 goto free_motg;
1448 }
1449
1450 motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
1451 if (IS_ERR(motg->clk)) {
1452 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1453 ret = PTR_ERR(motg->clk);
1454 goto put_phy_reset_clk;
1455 }
1456 clk_set_rate(motg->clk, 60000000);
1457
1458 /*
1459 * If USB Core is running its protocol engine based on CORE CLK,
1460 * CORE CLK must be running at >55Mhz for correct HSUSB
1461 * operation and USB core cannot tolerate frequency changes on
1462 * CORE CLK. For such USB cores, vote for maximum clk frequency
1463 * on pclk source
1464 */
1465 if (motg->pdata->pclk_src_name) {
1466 motg->pclk_src = clk_get(&pdev->dev,
1467 motg->pdata->pclk_src_name);
1468 if (IS_ERR(motg->pclk_src))
1469 goto put_clk;
1470 clk_set_rate(motg->pclk_src, INT_MAX);
1471 clk_enable(motg->pclk_src);
1472 } else
1473 motg->pclk_src = ERR_PTR(-ENOENT);
1474
1475
1476 motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1477 if (IS_ERR(motg->pclk)) {
1478 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1479 ret = PTR_ERR(motg->pclk);
1480 goto put_pclk_src;
1481 }
1482
1483 /*
1484 * USB core clock is not present on all MSM chips. This
1485 * clock is introduced to remove the dependency on AXI
1486 * bus frequency.
1487 */
1488 motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
1489 if (IS_ERR(motg->core_clk))
1490 motg->core_clk = NULL;
1491
1492 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1493 if (!res) {
1494 dev_err(&pdev->dev, "failed to get platform resource mem\n");
1495 ret = -ENODEV;
1496 goto put_core_clk;
1497 }
1498
1499 motg->regs = ioremap(res->start, resource_size(res));
1500 if (!motg->regs) {
1501 dev_err(&pdev->dev, "ioremap failed\n");
1502 ret = -ENOMEM;
1503 goto put_core_clk;
1504 }
1505 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1506
1507 motg->irq = platform_get_irq(pdev, 0);
1508 if (!motg->irq) {
1509 dev_err(&pdev->dev, "platform_get_irq failed\n");
1510 ret = -ENODEV;
1511 goto free_regs;
1512 }
1513
1514 clk_enable(motg->clk);
1515 clk_enable(motg->pclk);
1516
1517 ret = msm_hsusb_init_vddcx(motg, 1);
1518 if (ret) {
1519 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1520 goto free_regs;
1521 }
1522
1523 ret = msm_hsusb_ldo_init(motg, 1);
1524 if (ret) {
1525 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1526 goto vddcx_exit;
1527 }
1528 ret = msm_hsusb_ldo_set_mode(1);
1529 if (ret) {
1530 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1531 goto ldo_exit;
1532 }
1533
1534 if (motg->core_clk)
1535 clk_enable(motg->core_clk);
1536
1537 writel(0, USB_USBINTR);
1538 writel(0, USB_OTGSC);
1539
1540 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1541 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1542 ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
1543 "msm_otg", motg);
1544 if (ret) {
1545 dev_err(&pdev->dev, "request irq failed\n");
1546 goto disable_clks;
1547 }
1548
1549 phy->init = msm_otg_reset;
1550 phy->set_power = msm_otg_set_power;
1551
1552 phy->io_ops = &msm_otg_io_ops;
1553
1554 phy->otg->phy = &motg->phy;
1555 phy->otg->set_host = msm_otg_set_host;
1556 phy->otg->set_peripheral = msm_otg_set_peripheral;
1557
1558 ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
1559 if (ret) {
1560 dev_err(&pdev->dev, "usb_add_phy failed\n");
1561 goto free_irq;
1562 }
1563
1564 platform_set_drvdata(pdev, motg);
1565 device_init_wakeup(&pdev->dev, 1);
1566
1567 if (motg->pdata->mode == USB_OTG &&
1568 motg->pdata->otg_control == OTG_USER_CONTROL) {
1569 ret = msm_otg_debugfs_init(motg);
1570 if (ret)
1571 dev_dbg(&pdev->dev, "mode debugfs file is"
1572 "not available\n");
1573 }
1574
1575 pm_runtime_set_active(&pdev->dev);
1576 pm_runtime_enable(&pdev->dev);
1577
1578 return 0;
1579free_irq:
1580 free_irq(motg->irq, motg);
1581disable_clks:
1582 clk_disable(motg->pclk);
1583 clk_disable(motg->clk);
1584ldo_exit:
1585 msm_hsusb_ldo_init(motg, 0);
1586vddcx_exit:
1587 msm_hsusb_init_vddcx(motg, 0);
1588free_regs:
1589 iounmap(motg->regs);
1590put_core_clk:
1591 if (motg->core_clk)
1592 clk_put(motg->core_clk);
1593 clk_put(motg->pclk);
1594put_pclk_src:
1595 if (!IS_ERR(motg->pclk_src)) {
1596 clk_disable(motg->pclk_src);
1597 clk_put(motg->pclk_src);
1598 }
1599put_clk:
1600 clk_put(motg->clk);
1601put_phy_reset_clk:
1602 clk_put(motg->phy_reset_clk);
1603free_motg:
1604 kfree(motg->phy.otg);
1605 kfree(motg);
1606 return ret;
1607}
1608
1609static int msm_otg_remove(struct platform_device *pdev)
1610{
1611 struct msm_otg *motg = platform_get_drvdata(pdev);
1612 struct usb_phy *phy = &motg->phy;
1613 int cnt = 0;
1614
1615 if (phy->otg->host || phy->otg->gadget)
1616 return -EBUSY;
1617
1618 msm_otg_debugfs_cleanup();
1619 cancel_delayed_work_sync(&motg->chg_work);
1620 cancel_work_sync(&motg->sm_work);
1621
1622 pm_runtime_resume(&pdev->dev);
1623
1624 device_init_wakeup(&pdev->dev, 0);
1625 pm_runtime_disable(&pdev->dev);
1626
1627 usb_remove_phy(phy);
1628 free_irq(motg->irq, motg);
1629
1630 /*
1631 * Put PHY in low power mode.
1632 */
1633 ulpi_read(phy, 0x14);
1634 ulpi_write(phy, 0x08, 0x09);
1635
1636 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1637 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1638 if (readl(USB_PORTSC) & PORTSC_PHCD)
1639 break;
1640 udelay(1);
1641 cnt++;
1642 }
1643 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1644 dev_err(phy->dev, "Unable to suspend PHY\n");
1645
1646 clk_disable(motg->pclk);
1647 clk_disable(motg->clk);
1648 if (motg->core_clk)
1649 clk_disable(motg->core_clk);
1650 if (!IS_ERR(motg->pclk_src)) {
1651 clk_disable(motg->pclk_src);
1652 clk_put(motg->pclk_src);
1653 }
1654 msm_hsusb_ldo_init(motg, 0);
1655
1656 iounmap(motg->regs);
1657 pm_runtime_set_suspended(&pdev->dev);
1658
1659 clk_put(motg->phy_reset_clk);
1660 clk_put(motg->pclk);
1661 clk_put(motg->clk);
1662 if (motg->core_clk)
1663 clk_put(motg->core_clk);
1664
1665 kfree(motg->phy.otg);
1666 kfree(motg);
1667
1668 return 0;
1669}
1670
1671#ifdef CONFIG_PM_RUNTIME
1672static int msm_otg_runtime_idle(struct device *dev)
1673{
1674 struct msm_otg *motg = dev_get_drvdata(dev);
1675 struct usb_otg *otg = motg->phy.otg;
1676
1677 dev_dbg(dev, "OTG runtime idle\n");
1678
1679 /*
1680 * It is observed some times that a spurious interrupt
1681 * comes when PHY is put into LPM immediately after PHY reset.
1682 * This 1 sec delay also prevents entering into LPM immediately
1683 * after asynchronous interrupt.
1684 */
1685 if (otg->phy->state != OTG_STATE_UNDEFINED)
1686 pm_schedule_suspend(dev, 1000);
1687
1688 return -EAGAIN;
1689}
1690
1691static int msm_otg_runtime_suspend(struct device *dev)
1692{
1693 struct msm_otg *motg = dev_get_drvdata(dev);
1694
1695 dev_dbg(dev, "OTG runtime suspend\n");
1696 return msm_otg_suspend(motg);
1697}
1698
1699static int msm_otg_runtime_resume(struct device *dev)
1700{
1701 struct msm_otg *motg = dev_get_drvdata(dev);
1702
1703 dev_dbg(dev, "OTG runtime resume\n");
1704 return msm_otg_resume(motg);
1705}
1706#endif
1707
1708#ifdef CONFIG_PM_SLEEP
1709static int msm_otg_pm_suspend(struct device *dev)
1710{
1711 struct msm_otg *motg = dev_get_drvdata(dev);
1712
1713 dev_dbg(dev, "OTG PM suspend\n");
1714 return msm_otg_suspend(motg);
1715}
1716
1717static int msm_otg_pm_resume(struct device *dev)
1718{
1719 struct msm_otg *motg = dev_get_drvdata(dev);
1720 int ret;
1721
1722 dev_dbg(dev, "OTG PM resume\n");
1723
1724 ret = msm_otg_resume(motg);
1725 if (ret)
1726 return ret;
1727
1728 /*
1729 * Runtime PM Documentation recommends bringing the
1730 * device to full powered state upon resume.
1731 */
1732 pm_runtime_disable(dev);
1733 pm_runtime_set_active(dev);
1734 pm_runtime_enable(dev);
1735
1736 return 0;
1737}
1738#endif
1739
1740#ifdef CONFIG_PM
1741static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1742 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1743 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1744 msm_otg_runtime_idle)
1745};
1746#endif
1747
1748static struct platform_driver msm_otg_driver = {
1749 .remove = msm_otg_remove,
1750 .driver = {
1751 .name = DRIVER_NAME,
1752 .owner = THIS_MODULE,
1753#ifdef CONFIG_PM
1754 .pm = &msm_otg_dev_pm_ops,
1755#endif
1756 },
1757};
1758
1759module_platform_driver_probe(msm_otg_driver, msm_otg_probe);
1760
1761MODULE_LICENSE("GPL v2");
1762MODULE_DESCRIPTION("MSM USB transceiver driver");
diff --git a/drivers/usb/phy/mv_otg.c b/drivers/usb/phy/mv_otg.c
new file mode 100644
index 000000000000..b6a9be31133b
--- /dev/null
+++ b/drivers/usb/phy/mv_otg.c
@@ -0,0 +1,923 @@
1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/uaccess.h>
17#include <linux/device.h>
18#include <linux/proc_fs.h>
19#include <linux/clk.h>
20#include <linux/workqueue.h>
21#include <linux/platform_device.h>
22
23#include <linux/usb.h>
24#include <linux/usb/ch9.h>
25#include <linux/usb/otg.h>
26#include <linux/usb/gadget.h>
27#include <linux/usb/hcd.h>
28#include <linux/platform_data/mv_usb.h>
29
30#include "mv_otg.h"
31
32#define DRIVER_DESC "Marvell USB OTG transceiver driver"
33#define DRIVER_VERSION "Jan 20, 2010"
34
35MODULE_DESCRIPTION(DRIVER_DESC);
36MODULE_VERSION(DRIVER_VERSION);
37MODULE_LICENSE("GPL");
38
39static const char driver_name[] = "mv-otg";
40
41static char *state_string[] = {
42 "undefined",
43 "b_idle",
44 "b_srp_init",
45 "b_peripheral",
46 "b_wait_acon",
47 "b_host",
48 "a_idle",
49 "a_wait_vrise",
50 "a_wait_bcon",
51 "a_host",
52 "a_suspend",
53 "a_peripheral",
54 "a_wait_vfall",
55 "a_vbus_err"
56};
57
58static int mv_otg_set_vbus(struct usb_otg *otg, bool on)
59{
60 struct mv_otg *mvotg = container_of(otg->phy, struct mv_otg, phy);
61 if (mvotg->pdata->set_vbus == NULL)
62 return -ENODEV;
63
64 return mvotg->pdata->set_vbus(on);
65}
66
67static int mv_otg_set_host(struct usb_otg *otg,
68 struct usb_bus *host)
69{
70 otg->host = host;
71
72 return 0;
73}
74
75static int mv_otg_set_peripheral(struct usb_otg *otg,
76 struct usb_gadget *gadget)
77{
78 otg->gadget = gadget;
79
80 return 0;
81}
82
83static void mv_otg_run_state_machine(struct mv_otg *mvotg,
84 unsigned long delay)
85{
86 dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
87 if (!mvotg->qwork)
88 return;
89
90 queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
91}
92
93static void mv_otg_timer_await_bcon(unsigned long data)
94{
95 struct mv_otg *mvotg = (struct mv_otg *) data;
96
97 mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
98
99 dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
100
101 if (spin_trylock(&mvotg->wq_lock)) {
102 mv_otg_run_state_machine(mvotg, 0);
103 spin_unlock(&mvotg->wq_lock);
104 }
105}
106
107static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
108{
109 struct timer_list *timer;
110
111 if (id >= OTG_TIMER_NUM)
112 return -EINVAL;
113
114 timer = &mvotg->otg_ctrl.timer[id];
115
116 if (timer_pending(timer))
117 del_timer(timer);
118
119 return 0;
120}
121
122static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
123 unsigned long interval,
124 void (*callback) (unsigned long))
125{
126 struct timer_list *timer;
127
128 if (id >= OTG_TIMER_NUM)
129 return -EINVAL;
130
131 timer = &mvotg->otg_ctrl.timer[id];
132 if (timer_pending(timer)) {
133 dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
134 return -EBUSY;
135 }
136
137 init_timer(timer);
138 timer->data = (unsigned long) mvotg;
139 timer->function = callback;
140 timer->expires = jiffies + interval;
141 add_timer(timer);
142
143 return 0;
144}
145
146static int mv_otg_reset(struct mv_otg *mvotg)
147{
148 unsigned int loops;
149 u32 tmp;
150
151 /* Stop the controller */
152 tmp = readl(&mvotg->op_regs->usbcmd);
153 tmp &= ~USBCMD_RUN_STOP;
154 writel(tmp, &mvotg->op_regs->usbcmd);
155
156 /* Reset the controller to get default values */
157 writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
158
159 loops = 500;
160 while (readl(&mvotg->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
161 if (loops == 0) {
162 dev_err(&mvotg->pdev->dev,
163 "Wait for RESET completed TIMEOUT\n");
164 return -ETIMEDOUT;
165 }
166 loops--;
167 udelay(20);
168 }
169
170 writel(0x0, &mvotg->op_regs->usbintr);
171 tmp = readl(&mvotg->op_regs->usbsts);
172 writel(tmp, &mvotg->op_regs->usbsts);
173
174 return 0;
175}
176
177static void mv_otg_init_irq(struct mv_otg *mvotg)
178{
179 u32 otgsc;
180
181 mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
182 | OTGSC_INTR_A_VBUS_VALID;
183 mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
184 | OTGSC_INTSTS_A_VBUS_VALID;
185
186 if (mvotg->pdata->vbus == NULL) {
187 mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
188 | OTGSC_INTR_B_SESSION_END;
189 mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
190 | OTGSC_INTSTS_B_SESSION_END;
191 }
192
193 if (mvotg->pdata->id == NULL) {
194 mvotg->irq_en |= OTGSC_INTR_USB_ID;
195 mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
196 }
197
198 otgsc = readl(&mvotg->op_regs->otgsc);
199 otgsc |= mvotg->irq_en;
200 writel(otgsc, &mvotg->op_regs->otgsc);
201}
202
203static void mv_otg_start_host(struct mv_otg *mvotg, int on)
204{
205#ifdef CONFIG_USB
206 struct usb_otg *otg = mvotg->phy.otg;
207 struct usb_hcd *hcd;
208
209 if (!otg->host)
210 return;
211
212 dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
213
214 hcd = bus_to_hcd(otg->host);
215
216 if (on)
217 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
218 else
219 usb_remove_hcd(hcd);
220#endif /* CONFIG_USB */
221}
222
223static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
224{
225 struct usb_otg *otg = mvotg->phy.otg;
226
227 if (!otg->gadget)
228 return;
229
230 dev_info(mvotg->phy.dev, "gadget %s\n", on ? "on" : "off");
231
232 if (on)
233 usb_gadget_vbus_connect(otg->gadget);
234 else
235 usb_gadget_vbus_disconnect(otg->gadget);
236}
237
238static void otg_clock_enable(struct mv_otg *mvotg)
239{
240 unsigned int i;
241
242 for (i = 0; i < mvotg->clknum; i++)
243 clk_prepare_enable(mvotg->clk[i]);
244}
245
246static void otg_clock_disable(struct mv_otg *mvotg)
247{
248 unsigned int i;
249
250 for (i = 0; i < mvotg->clknum; i++)
251 clk_disable_unprepare(mvotg->clk[i]);
252}
253
254static int mv_otg_enable_internal(struct mv_otg *mvotg)
255{
256 int retval = 0;
257
258 if (mvotg->active)
259 return 0;
260
261 dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
262
263 otg_clock_enable(mvotg);
264 if (mvotg->pdata->phy_init) {
265 retval = mvotg->pdata->phy_init(mvotg->phy_regs);
266 if (retval) {
267 dev_err(&mvotg->pdev->dev,
268 "init phy error %d\n", retval);
269 otg_clock_disable(mvotg);
270 return retval;
271 }
272 }
273 mvotg->active = 1;
274
275 return 0;
276
277}
278
279static int mv_otg_enable(struct mv_otg *mvotg)
280{
281 if (mvotg->clock_gating)
282 return mv_otg_enable_internal(mvotg);
283
284 return 0;
285}
286
287static void mv_otg_disable_internal(struct mv_otg *mvotg)
288{
289 if (mvotg->active) {
290 dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
291 if (mvotg->pdata->phy_deinit)
292 mvotg->pdata->phy_deinit(mvotg->phy_regs);
293 otg_clock_disable(mvotg);
294 mvotg->active = 0;
295 }
296}
297
298static void mv_otg_disable(struct mv_otg *mvotg)
299{
300 if (mvotg->clock_gating)
301 mv_otg_disable_internal(mvotg);
302}
303
304static void mv_otg_update_inputs(struct mv_otg *mvotg)
305{
306 struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
307 u32 otgsc;
308
309 otgsc = readl(&mvotg->op_regs->otgsc);
310
311 if (mvotg->pdata->vbus) {
312 if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
313 otg_ctrl->b_sess_vld = 1;
314 otg_ctrl->b_sess_end = 0;
315 } else {
316 otg_ctrl->b_sess_vld = 0;
317 otg_ctrl->b_sess_end = 1;
318 }
319 } else {
320 otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
321 otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
322 }
323
324 if (mvotg->pdata->id)
325 otg_ctrl->id = !!mvotg->pdata->id->poll();
326 else
327 otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
328
329 if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
330 otg_ctrl->a_bus_req = 1;
331
332 otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
333 otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
334
335 dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
336 dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
337 dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
338 dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
339 dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
340 dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
341}
342
343static void mv_otg_update_state(struct mv_otg *mvotg)
344{
345 struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
346 struct usb_phy *phy = &mvotg->phy;
347 int old_state = phy->state;
348
349 switch (old_state) {
350 case OTG_STATE_UNDEFINED:
351 phy->state = OTG_STATE_B_IDLE;
352 /* FALL THROUGH */
353 case OTG_STATE_B_IDLE:
354 if (otg_ctrl->id == 0)
355 phy->state = OTG_STATE_A_IDLE;
356 else if (otg_ctrl->b_sess_vld)
357 phy->state = OTG_STATE_B_PERIPHERAL;
358 break;
359 case OTG_STATE_B_PERIPHERAL:
360 if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
361 phy->state = OTG_STATE_B_IDLE;
362 break;
363 case OTG_STATE_A_IDLE:
364 if (otg_ctrl->id)
365 phy->state = OTG_STATE_B_IDLE;
366 else if (!(otg_ctrl->a_bus_drop) &&
367 (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
368 phy->state = OTG_STATE_A_WAIT_VRISE;
369 break;
370 case OTG_STATE_A_WAIT_VRISE:
371 if (otg_ctrl->a_vbus_vld)
372 phy->state = OTG_STATE_A_WAIT_BCON;
373 break;
374 case OTG_STATE_A_WAIT_BCON:
375 if (otg_ctrl->id || otg_ctrl->a_bus_drop
376 || otg_ctrl->a_wait_bcon_timeout) {
377 mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
378 mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
379 phy->state = OTG_STATE_A_WAIT_VFALL;
380 otg_ctrl->a_bus_req = 0;
381 } else if (!otg_ctrl->a_vbus_vld) {
382 mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
383 mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
384 phy->state = OTG_STATE_A_VBUS_ERR;
385 } else if (otg_ctrl->b_conn) {
386 mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
387 mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
388 phy->state = OTG_STATE_A_HOST;
389 }
390 break;
391 case OTG_STATE_A_HOST:
392 if (otg_ctrl->id || !otg_ctrl->b_conn
393 || otg_ctrl->a_bus_drop)
394 phy->state = OTG_STATE_A_WAIT_BCON;
395 else if (!otg_ctrl->a_vbus_vld)
396 phy->state = OTG_STATE_A_VBUS_ERR;
397 break;
398 case OTG_STATE_A_WAIT_VFALL:
399 if (otg_ctrl->id
400 || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
401 || otg_ctrl->a_bus_req)
402 phy->state = OTG_STATE_A_IDLE;
403 break;
404 case OTG_STATE_A_VBUS_ERR:
405 if (otg_ctrl->id || otg_ctrl->a_clr_err
406 || otg_ctrl->a_bus_drop) {
407 otg_ctrl->a_clr_err = 0;
408 phy->state = OTG_STATE_A_WAIT_VFALL;
409 }
410 break;
411 default:
412 break;
413 }
414}
415
416static void mv_otg_work(struct work_struct *work)
417{
418 struct mv_otg *mvotg;
419 struct usb_phy *phy;
420 struct usb_otg *otg;
421 int old_state;
422
423 mvotg = container_of(to_delayed_work(work), struct mv_otg, work);
424
425run:
426 /* work queue is single thread, or we need spin_lock to protect */
427 phy = &mvotg->phy;
428 otg = phy->otg;
429 old_state = phy->state;
430
431 if (!mvotg->active)
432 return;
433
434 mv_otg_update_inputs(mvotg);
435 mv_otg_update_state(mvotg);
436
437 if (old_state != phy->state) {
438 dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
439 state_string[old_state],
440 state_string[phy->state]);
441
442 switch (phy->state) {
443 case OTG_STATE_B_IDLE:
444 otg->default_a = 0;
445 if (old_state == OTG_STATE_B_PERIPHERAL)
446 mv_otg_start_periphrals(mvotg, 0);
447 mv_otg_reset(mvotg);
448 mv_otg_disable(mvotg);
449 break;
450 case OTG_STATE_B_PERIPHERAL:
451 mv_otg_enable(mvotg);
452 mv_otg_start_periphrals(mvotg, 1);
453 break;
454 case OTG_STATE_A_IDLE:
455 otg->default_a = 1;
456 mv_otg_enable(mvotg);
457 if (old_state == OTG_STATE_A_WAIT_VFALL)
458 mv_otg_start_host(mvotg, 0);
459 mv_otg_reset(mvotg);
460 break;
461 case OTG_STATE_A_WAIT_VRISE:
462 mv_otg_set_vbus(otg, 1);
463 break;
464 case OTG_STATE_A_WAIT_BCON:
465 if (old_state != OTG_STATE_A_HOST)
466 mv_otg_start_host(mvotg, 1);
467 mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
468 T_A_WAIT_BCON,
469 mv_otg_timer_await_bcon);
470 /*
471 * Now, we directly enter A_HOST. So set b_conn = 1
472 * here. In fact, it need host driver to notify us.
473 */
474 mvotg->otg_ctrl.b_conn = 1;
475 break;
476 case OTG_STATE_A_HOST:
477 break;
478 case OTG_STATE_A_WAIT_VFALL:
479 /*
480 * Now, we has exited A_HOST. So set b_conn = 0
481 * here. In fact, it need host driver to notify us.
482 */
483 mvotg->otg_ctrl.b_conn = 0;
484 mv_otg_set_vbus(otg, 0);
485 break;
486 case OTG_STATE_A_VBUS_ERR:
487 break;
488 default:
489 break;
490 }
491 goto run;
492 }
493}
494
495static irqreturn_t mv_otg_irq(int irq, void *dev)
496{
497 struct mv_otg *mvotg = dev;
498 u32 otgsc;
499
500 otgsc = readl(&mvotg->op_regs->otgsc);
501 writel(otgsc, &mvotg->op_regs->otgsc);
502
503 /*
504 * if we have vbus, then the vbus detection for B-device
505 * will be done by mv_otg_inputs_irq().
506 */
507 if (mvotg->pdata->vbus)
508 if ((otgsc & OTGSC_STS_USB_ID) &&
509 !(otgsc & OTGSC_INTSTS_USB_ID))
510 return IRQ_NONE;
511
512 if ((otgsc & mvotg->irq_status) == 0)
513 return IRQ_NONE;
514
515 mv_otg_run_state_machine(mvotg, 0);
516
517 return IRQ_HANDLED;
518}
519
520static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
521{
522 struct mv_otg *mvotg = dev;
523
524 /* The clock may disabled at this time */
525 if (!mvotg->active) {
526 mv_otg_enable(mvotg);
527 mv_otg_init_irq(mvotg);
528 }
529
530 mv_otg_run_state_machine(mvotg, 0);
531
532 return IRQ_HANDLED;
533}
534
535static ssize_t
536get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
537{
538 struct mv_otg *mvotg = dev_get_drvdata(dev);
539 return scnprintf(buf, PAGE_SIZE, "%d\n",
540 mvotg->otg_ctrl.a_bus_req);
541}
542
543static ssize_t
544set_a_bus_req(struct device *dev, struct device_attribute *attr,
545 const char *buf, size_t count)
546{
547 struct mv_otg *mvotg = dev_get_drvdata(dev);
548
549 if (count > 2)
550 return -1;
551
552 /* We will use this interface to change to A device */
553 if (mvotg->phy.state != OTG_STATE_B_IDLE
554 && mvotg->phy.state != OTG_STATE_A_IDLE)
555 return -1;
556
557 /* The clock may disabled and we need to set irq for ID detected */
558 mv_otg_enable(mvotg);
559 mv_otg_init_irq(mvotg);
560
561 if (buf[0] == '1') {
562 mvotg->otg_ctrl.a_bus_req = 1;
563 mvotg->otg_ctrl.a_bus_drop = 0;
564 dev_dbg(&mvotg->pdev->dev,
565 "User request: a_bus_req = 1\n");
566
567 if (spin_trylock(&mvotg->wq_lock)) {
568 mv_otg_run_state_machine(mvotg, 0);
569 spin_unlock(&mvotg->wq_lock);
570 }
571 }
572
573 return count;
574}
575
576static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req,
577 set_a_bus_req);
578
579static ssize_t
580set_a_clr_err(struct device *dev, struct device_attribute *attr,
581 const char *buf, size_t count)
582{
583 struct mv_otg *mvotg = dev_get_drvdata(dev);
584 if (!mvotg->phy.otg->default_a)
585 return -1;
586
587 if (count > 2)
588 return -1;
589
590 if (buf[0] == '1') {
591 mvotg->otg_ctrl.a_clr_err = 1;
592 dev_dbg(&mvotg->pdev->dev,
593 "User request: a_clr_err = 1\n");
594 }
595
596 if (spin_trylock(&mvotg->wq_lock)) {
597 mv_otg_run_state_machine(mvotg, 0);
598 spin_unlock(&mvotg->wq_lock);
599 }
600
601 return count;
602}
603
604static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
605
606static ssize_t
607get_a_bus_drop(struct device *dev, struct device_attribute *attr,
608 char *buf)
609{
610 struct mv_otg *mvotg = dev_get_drvdata(dev);
611 return scnprintf(buf, PAGE_SIZE, "%d\n",
612 mvotg->otg_ctrl.a_bus_drop);
613}
614
615static ssize_t
616set_a_bus_drop(struct device *dev, struct device_attribute *attr,
617 const char *buf, size_t count)
618{
619 struct mv_otg *mvotg = dev_get_drvdata(dev);
620 if (!mvotg->phy.otg->default_a)
621 return -1;
622
623 if (count > 2)
624 return -1;
625
626 if (buf[0] == '0') {
627 mvotg->otg_ctrl.a_bus_drop = 0;
628 dev_dbg(&mvotg->pdev->dev,
629 "User request: a_bus_drop = 0\n");
630 } else if (buf[0] == '1') {
631 mvotg->otg_ctrl.a_bus_drop = 1;
632 mvotg->otg_ctrl.a_bus_req = 0;
633 dev_dbg(&mvotg->pdev->dev,
634 "User request: a_bus_drop = 1\n");
635 dev_dbg(&mvotg->pdev->dev,
636 "User request: and a_bus_req = 0\n");
637 }
638
639 if (spin_trylock(&mvotg->wq_lock)) {
640 mv_otg_run_state_machine(mvotg, 0);
641 spin_unlock(&mvotg->wq_lock);
642 }
643
644 return count;
645}
646
647static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR,
648 get_a_bus_drop, set_a_bus_drop);
649
650static struct attribute *inputs_attrs[] = {
651 &dev_attr_a_bus_req.attr,
652 &dev_attr_a_clr_err.attr,
653 &dev_attr_a_bus_drop.attr,
654 NULL,
655};
656
657static struct attribute_group inputs_attr_group = {
658 .name = "inputs",
659 .attrs = inputs_attrs,
660};
661
662int mv_otg_remove(struct platform_device *pdev)
663{
664 struct mv_otg *mvotg = platform_get_drvdata(pdev);
665
666 sysfs_remove_group(&mvotg->pdev->dev.kobj, &inputs_attr_group);
667
668 if (mvotg->qwork) {
669 flush_workqueue(mvotg->qwork);
670 destroy_workqueue(mvotg->qwork);
671 }
672
673 mv_otg_disable(mvotg);
674
675 usb_remove_phy(&mvotg->phy);
676 platform_set_drvdata(pdev, NULL);
677
678 return 0;
679}
680
681static int mv_otg_probe(struct platform_device *pdev)
682{
683 struct mv_usb_platform_data *pdata = pdev->dev.platform_data;
684 struct mv_otg *mvotg;
685 struct usb_otg *otg;
686 struct resource *r;
687 int retval = 0, clk_i, i;
688 size_t size;
689
690 if (pdata == NULL) {
691 dev_err(&pdev->dev, "failed to get platform data\n");
692 return -ENODEV;
693 }
694
695 size = sizeof(*mvotg) + sizeof(struct clk *) * pdata->clknum;
696 mvotg = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
697 if (!mvotg) {
698 dev_err(&pdev->dev, "failed to allocate memory!\n");
699 return -ENOMEM;
700 }
701
702 otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
703 if (!otg)
704 return -ENOMEM;
705
706 platform_set_drvdata(pdev, mvotg);
707
708 mvotg->pdev = pdev;
709 mvotg->pdata = pdata;
710
711 mvotg->clknum = pdata->clknum;
712 for (clk_i = 0; clk_i < mvotg->clknum; clk_i++) {
713 mvotg->clk[clk_i] = devm_clk_get(&pdev->dev,
714 pdata->clkname[clk_i]);
715 if (IS_ERR(mvotg->clk[clk_i])) {
716 retval = PTR_ERR(mvotg->clk[clk_i]);
717 return retval;
718 }
719 }
720
721 mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
722 if (!mvotg->qwork) {
723 dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
724 return -ENOMEM;
725 }
726
727 INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
728
729 /* OTG common part */
730 mvotg->pdev = pdev;
731 mvotg->phy.dev = &pdev->dev;
732 mvotg->phy.otg = otg;
733 mvotg->phy.label = driver_name;
734 mvotg->phy.state = OTG_STATE_UNDEFINED;
735
736 otg->phy = &mvotg->phy;
737 otg->set_host = mv_otg_set_host;
738 otg->set_peripheral = mv_otg_set_peripheral;
739 otg->set_vbus = mv_otg_set_vbus;
740
741 for (i = 0; i < OTG_TIMER_NUM; i++)
742 init_timer(&mvotg->otg_ctrl.timer[i]);
743
744 r = platform_get_resource_byname(mvotg->pdev,
745 IORESOURCE_MEM, "phyregs");
746 if (r == NULL) {
747 dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
748 retval = -ENODEV;
749 goto err_destroy_workqueue;
750 }
751
752 mvotg->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
753 if (mvotg->phy_regs == NULL) {
754 dev_err(&pdev->dev, "failed to map phy I/O memory\n");
755 retval = -EFAULT;
756 goto err_destroy_workqueue;
757 }
758
759 r = platform_get_resource_byname(mvotg->pdev,
760 IORESOURCE_MEM, "capregs");
761 if (r == NULL) {
762 dev_err(&pdev->dev, "no I/O memory resource defined\n");
763 retval = -ENODEV;
764 goto err_destroy_workqueue;
765 }
766
767 mvotg->cap_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
768 if (mvotg->cap_regs == NULL) {
769 dev_err(&pdev->dev, "failed to map I/O memory\n");
770 retval = -EFAULT;
771 goto err_destroy_workqueue;
772 }
773
774 /* we will acces controller register, so enable the udc controller */
775 retval = mv_otg_enable_internal(mvotg);
776 if (retval) {
777 dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
778 goto err_destroy_workqueue;
779 }
780
781 mvotg->op_regs =
782 (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
783 + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
784
785 if (pdata->id) {
786 retval = devm_request_threaded_irq(&pdev->dev, pdata->id->irq,
787 NULL, mv_otg_inputs_irq,
788 IRQF_ONESHOT, "id", mvotg);
789 if (retval) {
790 dev_info(&pdev->dev,
791 "Failed to request irq for ID\n");
792 pdata->id = NULL;
793 }
794 }
795
796 if (pdata->vbus) {
797 mvotg->clock_gating = 1;
798 retval = devm_request_threaded_irq(&pdev->dev, pdata->vbus->irq,
799 NULL, mv_otg_inputs_irq,
800 IRQF_ONESHOT, "vbus", mvotg);
801 if (retval) {
802 dev_info(&pdev->dev,
803 "Failed to request irq for VBUS, "
804 "disable clock gating\n");
805 mvotg->clock_gating = 0;
806 pdata->vbus = NULL;
807 }
808 }
809
810 if (pdata->disable_otg_clock_gating)
811 mvotg->clock_gating = 0;
812
813 mv_otg_reset(mvotg);
814 mv_otg_init_irq(mvotg);
815
816 r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
817 if (r == NULL) {
818 dev_err(&pdev->dev, "no IRQ resource defined\n");
819 retval = -ENODEV;
820 goto err_disable_clk;
821 }
822
823 mvotg->irq = r->start;
824 if (devm_request_irq(&pdev->dev, mvotg->irq, mv_otg_irq, IRQF_SHARED,
825 driver_name, mvotg)) {
826 dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
827 mvotg->irq);
828 mvotg->irq = 0;
829 retval = -ENODEV;
830 goto err_disable_clk;
831 }
832
833 retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
834 if (retval < 0) {
835 dev_err(&pdev->dev, "can't register transceiver, %d\n",
836 retval);
837 goto err_disable_clk;
838 }
839
840 retval = sysfs_create_group(&pdev->dev.kobj, &inputs_attr_group);
841 if (retval < 0) {
842 dev_dbg(&pdev->dev,
843 "Can't register sysfs attr group: %d\n", retval);
844 goto err_remove_phy;
845 }
846
847 spin_lock_init(&mvotg->wq_lock);
848 if (spin_trylock(&mvotg->wq_lock)) {
849 mv_otg_run_state_machine(mvotg, 2 * HZ);
850 spin_unlock(&mvotg->wq_lock);
851 }
852
853 dev_info(&pdev->dev,
854 "successful probe OTG device %s clock gating.\n",
855 mvotg->clock_gating ? "with" : "without");
856
857 return 0;
858
859err_remove_phy:
860 usb_remove_phy(&mvotg->phy);
861err_disable_clk:
862 mv_otg_disable_internal(mvotg);
863err_destroy_workqueue:
864 flush_workqueue(mvotg->qwork);
865 destroy_workqueue(mvotg->qwork);
866
867 platform_set_drvdata(pdev, NULL);
868
869 return retval;
870}
871
872#ifdef CONFIG_PM
873static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
874{
875 struct mv_otg *mvotg = platform_get_drvdata(pdev);
876
877 if (mvotg->phy.state != OTG_STATE_B_IDLE) {
878 dev_info(&pdev->dev,
879 "OTG state is not B_IDLE, it is %d!\n",
880 mvotg->phy.state);
881 return -EAGAIN;
882 }
883
884 if (!mvotg->clock_gating)
885 mv_otg_disable_internal(mvotg);
886
887 return 0;
888}
889
890static int mv_otg_resume(struct platform_device *pdev)
891{
892 struct mv_otg *mvotg = platform_get_drvdata(pdev);
893 u32 otgsc;
894
895 if (!mvotg->clock_gating) {
896 mv_otg_enable_internal(mvotg);
897
898 otgsc = readl(&mvotg->op_regs->otgsc);
899 otgsc |= mvotg->irq_en;
900 writel(otgsc, &mvotg->op_regs->otgsc);
901
902 if (spin_trylock(&mvotg->wq_lock)) {
903 mv_otg_run_state_machine(mvotg, 0);
904 spin_unlock(&mvotg->wq_lock);
905 }
906 }
907 return 0;
908}
909#endif
910
911static struct platform_driver mv_otg_driver = {
912 .probe = mv_otg_probe,
913 .remove = __exit_p(mv_otg_remove),
914 .driver = {
915 .owner = THIS_MODULE,
916 .name = driver_name,
917 },
918#ifdef CONFIG_PM
919 .suspend = mv_otg_suspend,
920 .resume = mv_otg_resume,
921#endif
922};
923module_platform_driver(mv_otg_driver);
diff --git a/drivers/usb/phy/mv_otg.h b/drivers/usb/phy/mv_otg.h
new file mode 100644
index 000000000000..8a9e351b36ba
--- /dev/null
+++ b/drivers/usb/phy/mv_otg.h
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __MV_USB_OTG_CONTROLLER__
11#define __MV_USB_OTG_CONTROLLER__
12
13#include <linux/types.h>
14
15/* Command Register Bit Masks */
16#define USBCMD_RUN_STOP (0x00000001)
17#define USBCMD_CTRL_RESET (0x00000002)
18
19/* otgsc Register Bit Masks */
20#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
21#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
22#define OTGSC_CTRL_OTG_TERM 0x00000008
23#define OTGSC_CTRL_DATA_PULSING 0x00000010
24#define OTGSC_STS_USB_ID 0x00000100
25#define OTGSC_STS_A_VBUS_VALID 0x00000200
26#define OTGSC_STS_A_SESSION_VALID 0x00000400
27#define OTGSC_STS_B_SESSION_VALID 0x00000800
28#define OTGSC_STS_B_SESSION_END 0x00001000
29#define OTGSC_STS_1MS_TOGGLE 0x00002000
30#define OTGSC_STS_DATA_PULSING 0x00004000
31#define OTGSC_INTSTS_USB_ID 0x00010000
32#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
33#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
34#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
35#define OTGSC_INTSTS_B_SESSION_END 0x00100000
36#define OTGSC_INTSTS_1MS 0x00200000
37#define OTGSC_INTSTS_DATA_PULSING 0x00400000
38#define OTGSC_INTR_USB_ID 0x01000000
39#define OTGSC_INTR_A_VBUS_VALID 0x02000000
40#define OTGSC_INTR_A_SESSION_VALID 0x04000000
41#define OTGSC_INTR_B_SESSION_VALID 0x08000000
42#define OTGSC_INTR_B_SESSION_END 0x10000000
43#define OTGSC_INTR_1MS_TIMER 0x20000000
44#define OTGSC_INTR_DATA_PULSING 0x40000000
45
46#define CAPLENGTH_MASK (0xff)
47
48/* Timer's interval, unit 10ms */
49#define T_A_WAIT_VRISE 100
50#define T_A_WAIT_BCON 2000
51#define T_A_AIDL_BDIS 100
52#define T_A_BIDL_ADIS 20
53#define T_B_ASE0_BRST 400
54#define T_B_SE0_SRP 300
55#define T_B_SRP_FAIL 2000
56#define T_B_DATA_PLS 10
57#define T_B_SRP_INIT 100
58#define T_A_SRP_RSPNS 10
59#define T_A_DRV_RSM 5
60
61enum otg_function {
62 OTG_B_DEVICE = 0,
63 OTG_A_DEVICE
64};
65
66enum mv_otg_timer {
67 A_WAIT_BCON_TIMER = 0,
68 OTG_TIMER_NUM
69};
70
71/* PXA OTG state machine */
72struct mv_otg_ctrl {
73 /* internal variables */
74 u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */
75 u8 b_srp_done;
76 u8 b_hnp_en;
77
78 /* OTG inputs */
79 u8 a_bus_drop;
80 u8 a_bus_req;
81 u8 a_clr_err;
82 u8 a_bus_resume;
83 u8 a_bus_suspend;
84 u8 a_conn;
85 u8 a_sess_vld;
86 u8 a_srp_det;
87 u8 a_vbus_vld;
88 u8 b_bus_req; /* B-Device Require Bus */
89 u8 b_bus_resume;
90 u8 b_bus_suspend;
91 u8 b_conn;
92 u8 b_se0_srp;
93 u8 b_sess_end;
94 u8 b_sess_vld;
95 u8 id;
96 u8 a_suspend_req;
97
98 /*Timer event */
99 u8 a_aidl_bdis_timeout;
100 u8 b_ase0_brst_timeout;
101 u8 a_bidl_adis_timeout;
102 u8 a_wait_bcon_timeout;
103
104 struct timer_list timer[OTG_TIMER_NUM];
105};
106
107#define VUSBHS_MAX_PORTS 8
108
109struct mv_otg_regs {
110 u32 usbcmd; /* Command register */
111 u32 usbsts; /* Status register */
112 u32 usbintr; /* Interrupt enable */
113 u32 frindex; /* Frame index */
114 u32 reserved1[1];
115 u32 deviceaddr; /* Device Address */
116 u32 eplistaddr; /* Endpoint List Address */
117 u32 ttctrl; /* HOST TT status and control */
118 u32 burstsize; /* Programmable Burst Size */
119 u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
120 u32 reserved[4];
121 u32 epnak; /* Endpoint NAK */
122 u32 epnaken; /* Endpoint NAK Enable */
123 u32 configflag; /* Configured Flag register */
124 u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
125 u32 otgsc;
126 u32 usbmode; /* USB Host/Device mode */
127 u32 epsetupstat; /* Endpoint Setup Status */
128 u32 epprime; /* Endpoint Initialize */
129 u32 epflush; /* Endpoint De-initialize */
130 u32 epstatus; /* Endpoint Status */
131 u32 epcomplete; /* Endpoint Interrupt On Complete */
132 u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
133 u32 mcr; /* Mux Control */
134 u32 isr; /* Interrupt Status */
135 u32 ier; /* Interrupt Enable */
136};
137
138struct mv_otg {
139 struct usb_phy phy;
140 struct mv_otg_ctrl otg_ctrl;
141
142 /* base address */
143 void __iomem *phy_regs;
144 void __iomem *cap_regs;
145 struct mv_otg_regs __iomem *op_regs;
146
147 struct platform_device *pdev;
148 int irq;
149 u32 irq_status;
150 u32 irq_en;
151
152 struct delayed_work work;
153 struct workqueue_struct *qwork;
154
155 spinlock_t wq_lock;
156
157 struct mv_usb_platform_data *pdata;
158
159 unsigned int active;
160 unsigned int clock_gating;
161 unsigned int clknum;
162 struct clk *clk[0];
163};
164
165#endif
diff --git a/drivers/usb/phy/mxs-phy.c b/drivers/usb/phy/mxs-phy.c
new file mode 100644
index 000000000000..9d4381e64d51
--- /dev/null
+++ b/drivers/usb/phy/mxs-phy.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
4 * on behalf of DENX Software Engineering GmbH
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/usb/otg.h>
19#include <linux/stmp_device.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/io.h>
23
24#define DRIVER_NAME "mxs_phy"
25
26#define HW_USBPHY_PWD 0x00
27#define HW_USBPHY_CTRL 0x30
28#define HW_USBPHY_CTRL_SET 0x34
29#define HW_USBPHY_CTRL_CLR 0x38
30
31#define BM_USBPHY_CTRL_SFTRST BIT(31)
32#define BM_USBPHY_CTRL_CLKGATE BIT(30)
33#define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
34#define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
35#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
36
37struct mxs_phy {
38 struct usb_phy phy;
39 struct clk *clk;
40};
41
42#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
43
44static void mxs_phy_hw_init(struct mxs_phy *mxs_phy)
45{
46 void __iomem *base = mxs_phy->phy.io_priv;
47
48 stmp_reset_block(base + HW_USBPHY_CTRL);
49
50 /* Power up the PHY */
51 writel(0, base + HW_USBPHY_PWD);
52
53 /* enable FS/LS device */
54 writel(BM_USBPHY_CTRL_ENUTMILEVEL2 |
55 BM_USBPHY_CTRL_ENUTMILEVEL3,
56 base + HW_USBPHY_CTRL_SET);
57}
58
59static int mxs_phy_init(struct usb_phy *phy)
60{
61 struct mxs_phy *mxs_phy = to_mxs_phy(phy);
62
63 clk_prepare_enable(mxs_phy->clk);
64 mxs_phy_hw_init(mxs_phy);
65
66 return 0;
67}
68
69static void mxs_phy_shutdown(struct usb_phy *phy)
70{
71 struct mxs_phy *mxs_phy = to_mxs_phy(phy);
72
73 writel(BM_USBPHY_CTRL_CLKGATE,
74 phy->io_priv + HW_USBPHY_CTRL_SET);
75
76 clk_disable_unprepare(mxs_phy->clk);
77}
78
79static int mxs_phy_suspend(struct usb_phy *x, int suspend)
80{
81 struct mxs_phy *mxs_phy = to_mxs_phy(x);
82
83 if (suspend) {
84 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
85 writel(BM_USBPHY_CTRL_CLKGATE,
86 x->io_priv + HW_USBPHY_CTRL_SET);
87 clk_disable_unprepare(mxs_phy->clk);
88 } else {
89 clk_prepare_enable(mxs_phy->clk);
90 writel(BM_USBPHY_CTRL_CLKGATE,
91 x->io_priv + HW_USBPHY_CTRL_CLR);
92 writel(0, x->io_priv + HW_USBPHY_PWD);
93 }
94
95 return 0;
96}
97
98static int mxs_phy_on_connect(struct usb_phy *phy,
99 enum usb_device_speed speed)
100{
101 dev_dbg(phy->dev, "%s speed device has connected\n",
102 (speed == USB_SPEED_HIGH) ? "high" : "non-high");
103
104 if (speed == USB_SPEED_HIGH)
105 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
106 phy->io_priv + HW_USBPHY_CTRL_SET);
107
108 return 0;
109}
110
111static int mxs_phy_on_disconnect(struct usb_phy *phy,
112 enum usb_device_speed speed)
113{
114 dev_dbg(phy->dev, "%s speed device has disconnected\n",
115 (speed == USB_SPEED_HIGH) ? "high" : "non-high");
116
117 if (speed == USB_SPEED_HIGH)
118 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
119 phy->io_priv + HW_USBPHY_CTRL_CLR);
120
121 return 0;
122}
123
124static int mxs_phy_probe(struct platform_device *pdev)
125{
126 struct resource *res;
127 void __iomem *base;
128 struct clk *clk;
129 struct mxs_phy *mxs_phy;
130 int ret;
131
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133 if (!res) {
134 dev_err(&pdev->dev, "can't get device resources\n");
135 return -ENOENT;
136 }
137
138 base = devm_ioremap_resource(&pdev->dev, res);
139 if (IS_ERR(base))
140 return PTR_ERR(base);
141
142 clk = devm_clk_get(&pdev->dev, NULL);
143 if (IS_ERR(clk)) {
144 dev_err(&pdev->dev,
145 "can't get the clock, err=%ld", PTR_ERR(clk));
146 return PTR_ERR(clk);
147 }
148
149 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
150 if (!mxs_phy) {
151 dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n");
152 return -ENOMEM;
153 }
154
155 mxs_phy->phy.io_priv = base;
156 mxs_phy->phy.dev = &pdev->dev;
157 mxs_phy->phy.label = DRIVER_NAME;
158 mxs_phy->phy.init = mxs_phy_init;
159 mxs_phy->phy.shutdown = mxs_phy_shutdown;
160 mxs_phy->phy.set_suspend = mxs_phy_suspend;
161 mxs_phy->phy.notify_connect = mxs_phy_on_connect;
162 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect;
163
164 ATOMIC_INIT_NOTIFIER_HEAD(&mxs_phy->phy.notifier);
165
166 mxs_phy->clk = clk;
167
168 platform_set_drvdata(pdev, &mxs_phy->phy);
169
170 ret = usb_add_phy_dev(&mxs_phy->phy);
171 if (ret)
172 return ret;
173
174 return 0;
175}
176
177static int mxs_phy_remove(struct platform_device *pdev)
178{
179 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
180
181 usb_remove_phy(&mxs_phy->phy);
182
183 platform_set_drvdata(pdev, NULL);
184
185 return 0;
186}
187
188static const struct of_device_id mxs_phy_dt_ids[] = {
189 { .compatible = "fsl,imx23-usbphy", },
190 { /* sentinel */ }
191};
192MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
193
194static struct platform_driver mxs_phy_driver = {
195 .probe = mxs_phy_probe,
196 .remove = mxs_phy_remove,
197 .driver = {
198 .name = DRIVER_NAME,
199 .owner = THIS_MODULE,
200 .of_match_table = mxs_phy_dt_ids,
201 },
202};
203
204static int __init mxs_phy_module_init(void)
205{
206 return platform_driver_register(&mxs_phy_driver);
207}
208postcore_initcall(mxs_phy_module_init);
209
210static void __exit mxs_phy_module_exit(void)
211{
212 platform_driver_unregister(&mxs_phy_driver);
213}
214module_exit(mxs_phy_module_exit);
215
216MODULE_ALIAS("platform:mxs-usb-phy");
217MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
218MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
219MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
220MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/nop-usb-xceiv.c b/drivers/usb/phy/nop-usb-xceiv.c
new file mode 100644
index 000000000000..2b10cc969bbb
--- /dev/null
+++ b/drivers/usb/phy/nop-usb-xceiv.c
@@ -0,0 +1,294 @@
1/*
2 * drivers/usb/otg/nop-usb-xceiv.c
3 *
4 * NOP USB transceiver for all USB transceiver which are either built-in
5 * into USB IP or which are mostly autonomous.
6 *
7 * Copyright (C) 2009 Texas Instruments Inc
8 * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * Current status:
25 * This provides a "nop" transceiver for PHYs which are
26 * autonomous such as isp1504, isp1707, etc.
27 */
28
29#include <linux/module.h>
30#include <linux/platform_device.h>
31#include <linux/dma-mapping.h>
32#include <linux/usb/otg.h>
33#include <linux/usb/nop-usb-xceiv.h>
34#include <linux/slab.h>
35#include <linux/clk.h>
36#include <linux/regulator/consumer.h>
37#include <linux/of.h>
38
39struct nop_usb_xceiv {
40 struct usb_phy phy;
41 struct device *dev;
42 struct clk *clk;
43 struct regulator *vcc;
44 struct regulator *reset;
45};
46
47static struct platform_device *pd;
48
49void usb_nop_xceiv_register(void)
50{
51 if (pd)
52 return;
53 pd = platform_device_register_simple("nop_usb_xceiv", -1, NULL, 0);
54 if (!pd) {
55 printk(KERN_ERR "Unable to register usb nop transceiver\n");
56 return;
57 }
58}
59EXPORT_SYMBOL(usb_nop_xceiv_register);
60
61void usb_nop_xceiv_unregister(void)
62{
63 platform_device_unregister(pd);
64 pd = NULL;
65}
66EXPORT_SYMBOL(usb_nop_xceiv_unregister);
67
68static int nop_set_suspend(struct usb_phy *x, int suspend)
69{
70 return 0;
71}
72
73static int nop_init(struct usb_phy *phy)
74{
75 struct nop_usb_xceiv *nop = dev_get_drvdata(phy->dev);
76
77 if (!IS_ERR(nop->vcc)) {
78 if (regulator_enable(nop->vcc))
79 dev_err(phy->dev, "Failed to enable power\n");
80 }
81
82 if (!IS_ERR(nop->clk))
83 clk_enable(nop->clk);
84
85 if (!IS_ERR(nop->reset)) {
86 /* De-assert RESET */
87 if (regulator_enable(nop->reset))
88 dev_err(phy->dev, "Failed to de-assert reset\n");
89 }
90
91 return 0;
92}
93
94static void nop_shutdown(struct usb_phy *phy)
95{
96 struct nop_usb_xceiv *nop = dev_get_drvdata(phy->dev);
97
98 if (!IS_ERR(nop->reset)) {
99 /* Assert RESET */
100 if (regulator_disable(nop->reset))
101 dev_err(phy->dev, "Failed to assert reset\n");
102 }
103
104 if (!IS_ERR(nop->clk))
105 clk_disable(nop->clk);
106
107 if (!IS_ERR(nop->vcc)) {
108 if (regulator_disable(nop->vcc))
109 dev_err(phy->dev, "Failed to disable power\n");
110 }
111}
112
113static int nop_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget)
114{
115 if (!otg)
116 return -ENODEV;
117
118 if (!gadget) {
119 otg->gadget = NULL;
120 return -ENODEV;
121 }
122
123 otg->gadget = gadget;
124 otg->phy->state = OTG_STATE_B_IDLE;
125 return 0;
126}
127
128static int nop_set_host(struct usb_otg *otg, struct usb_bus *host)
129{
130 if (!otg)
131 return -ENODEV;
132
133 if (!host) {
134 otg->host = NULL;
135 return -ENODEV;
136 }
137
138 otg->host = host;
139 return 0;
140}
141
142static int nop_usb_xceiv_probe(struct platform_device *pdev)
143{
144 struct device *dev = &pdev->dev;
145 struct nop_usb_xceiv_platform_data *pdata = pdev->dev.platform_data;
146 struct nop_usb_xceiv *nop;
147 enum usb_phy_type type = USB_PHY_TYPE_USB2;
148 int err;
149 u32 clk_rate = 0;
150 bool needs_vcc = false;
151 bool needs_reset = false;
152
153 nop = devm_kzalloc(&pdev->dev, sizeof(*nop), GFP_KERNEL);
154 if (!nop)
155 return -ENOMEM;
156
157 nop->phy.otg = devm_kzalloc(&pdev->dev, sizeof(*nop->phy.otg),
158 GFP_KERNEL);
159 if (!nop->phy.otg)
160 return -ENOMEM;
161
162 if (dev->of_node) {
163 struct device_node *node = dev->of_node;
164
165 if (of_property_read_u32(node, "clock-frequency", &clk_rate))
166 clk_rate = 0;
167
168 needs_vcc = of_property_read_bool(node, "vcc-supply");
169 needs_reset = of_property_read_bool(node, "reset-supply");
170
171 } else if (pdata) {
172 type = pdata->type;
173 clk_rate = pdata->clk_rate;
174 needs_vcc = pdata->needs_vcc;
175 needs_reset = pdata->needs_reset;
176 }
177
178 nop->clk = devm_clk_get(&pdev->dev, "main_clk");
179 if (IS_ERR(nop->clk)) {
180 dev_dbg(&pdev->dev, "Can't get phy clock: %ld\n",
181 PTR_ERR(nop->clk));
182 }
183
184 if (!IS_ERR(nop->clk) && clk_rate) {
185 err = clk_set_rate(nop->clk, clk_rate);
186 if (err) {
187 dev_err(&pdev->dev, "Error setting clock rate\n");
188 return err;
189 }
190 }
191
192 if (!IS_ERR(nop->clk)) {
193 err = clk_prepare(nop->clk);
194 if (err) {
195 dev_err(&pdev->dev, "Error preparing clock\n");
196 return err;
197 }
198 }
199
200 nop->vcc = devm_regulator_get(&pdev->dev, "vcc");
201 if (IS_ERR(nop->vcc)) {
202 dev_dbg(&pdev->dev, "Error getting vcc regulator: %ld\n",
203 PTR_ERR(nop->vcc));
204 if (needs_vcc)
205 return -EPROBE_DEFER;
206 }
207
208 nop->reset = devm_regulator_get(&pdev->dev, "reset");
209 if (IS_ERR(nop->reset)) {
210 dev_dbg(&pdev->dev, "Error getting reset regulator: %ld\n",
211 PTR_ERR(nop->reset));
212 if (needs_reset)
213 return -EPROBE_DEFER;
214 }
215
216 nop->dev = &pdev->dev;
217 nop->phy.dev = nop->dev;
218 nop->phy.label = "nop-xceiv";
219 nop->phy.set_suspend = nop_set_suspend;
220 nop->phy.init = nop_init;
221 nop->phy.shutdown = nop_shutdown;
222 nop->phy.state = OTG_STATE_UNDEFINED;
223 nop->phy.type = type;
224
225 nop->phy.otg->phy = &nop->phy;
226 nop->phy.otg->set_host = nop_set_host;
227 nop->phy.otg->set_peripheral = nop_set_peripheral;
228
229 err = usb_add_phy_dev(&nop->phy);
230 if (err) {
231 dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
232 err);
233 goto err_add;
234 }
235
236 platform_set_drvdata(pdev, nop);
237
238 ATOMIC_INIT_NOTIFIER_HEAD(&nop->phy.notifier);
239
240 return 0;
241
242err_add:
243 if (!IS_ERR(nop->clk))
244 clk_unprepare(nop->clk);
245 return err;
246}
247
248static int nop_usb_xceiv_remove(struct platform_device *pdev)
249{
250 struct nop_usb_xceiv *nop = platform_get_drvdata(pdev);
251
252 if (!IS_ERR(nop->clk))
253 clk_unprepare(nop->clk);
254
255 usb_remove_phy(&nop->phy);
256
257 platform_set_drvdata(pdev, NULL);
258
259 return 0;
260}
261
262static const struct of_device_id nop_xceiv_dt_ids[] = {
263 { .compatible = "usb-nop-xceiv" },
264 { }
265};
266
267MODULE_DEVICE_TABLE(of, nop_xceiv_dt_ids);
268
269static struct platform_driver nop_usb_xceiv_driver = {
270 .probe = nop_usb_xceiv_probe,
271 .remove = nop_usb_xceiv_remove,
272 .driver = {
273 .name = "nop_usb_xceiv",
274 .owner = THIS_MODULE,
275 .of_match_table = of_match_ptr(nop_xceiv_dt_ids),
276 },
277};
278
279static int __init nop_usb_xceiv_init(void)
280{
281 return platform_driver_register(&nop_usb_xceiv_driver);
282}
283subsys_initcall(nop_usb_xceiv_init);
284
285static void __exit nop_usb_xceiv_exit(void)
286{
287 platform_driver_unregister(&nop_usb_xceiv_driver);
288}
289module_exit(nop_usb_xceiv_exit);
290
291MODULE_ALIAS("platform:nop_usb_xceiv");
292MODULE_AUTHOR("Texas Instruments Inc");
293MODULE_DESCRIPTION("NOP USB Transceiver driver");
294MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/otg_fsm.c b/drivers/usb/phy/otg_fsm.c
new file mode 100644
index 000000000000..1f729a15decb
--- /dev/null
+++ b/drivers/usb/phy/otg_fsm.c
@@ -0,0 +1,348 @@
1/*
2 * OTG Finite State Machine from OTG spec
3 *
4 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
5 *
6 * Author: Li Yang <LeoLi@freescale.com>
7 * Jerry Huang <Chang-Ming.Huang@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/spinlock.h>
27#include <linux/delay.h>
28#include <linux/usb.h>
29#include <linux/usb/gadget.h>
30#include <linux/usb/otg.h>
31
32#include "otg_fsm.h"
33
34/* Change USB protocol when there is a protocol change */
35static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
36{
37 int ret = 0;
38
39 if (fsm->protocol != protocol) {
40 VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
41 fsm->protocol, protocol);
42 /* stop old protocol */
43 if (fsm->protocol == PROTO_HOST)
44 ret = fsm->ops->start_host(fsm, 0);
45 else if (fsm->protocol == PROTO_GADGET)
46 ret = fsm->ops->start_gadget(fsm, 0);
47 if (ret)
48 return ret;
49
50 /* start new protocol */
51 if (protocol == PROTO_HOST)
52 ret = fsm->ops->start_host(fsm, 1);
53 else if (protocol == PROTO_GADGET)
54 ret = fsm->ops->start_gadget(fsm, 1);
55 if (ret)
56 return ret;
57
58 fsm->protocol = protocol;
59 return 0;
60 }
61
62 return 0;
63}
64
65static int state_changed;
66
67/* Called when leaving a state. Do state clean up jobs here */
68void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
69{
70 switch (old_state) {
71 case OTG_STATE_B_IDLE:
72 otg_del_timer(fsm, b_se0_srp_tmr);
73 fsm->b_se0_srp = 0;
74 break;
75 case OTG_STATE_B_SRP_INIT:
76 fsm->b_srp_done = 0;
77 break;
78 case OTG_STATE_B_PERIPHERAL:
79 break;
80 case OTG_STATE_B_WAIT_ACON:
81 otg_del_timer(fsm, b_ase0_brst_tmr);
82 fsm->b_ase0_brst_tmout = 0;
83 break;
84 case OTG_STATE_B_HOST:
85 break;
86 case OTG_STATE_A_IDLE:
87 break;
88 case OTG_STATE_A_WAIT_VRISE:
89 otg_del_timer(fsm, a_wait_vrise_tmr);
90 fsm->a_wait_vrise_tmout = 0;
91 break;
92 case OTG_STATE_A_WAIT_BCON:
93 otg_del_timer(fsm, a_wait_bcon_tmr);
94 fsm->a_wait_bcon_tmout = 0;
95 break;
96 case OTG_STATE_A_HOST:
97 otg_del_timer(fsm, a_wait_enum_tmr);
98 break;
99 case OTG_STATE_A_SUSPEND:
100 otg_del_timer(fsm, a_aidl_bdis_tmr);
101 fsm->a_aidl_bdis_tmout = 0;
102 fsm->a_suspend_req = 0;
103 break;
104 case OTG_STATE_A_PERIPHERAL:
105 break;
106 case OTG_STATE_A_WAIT_VFALL:
107 otg_del_timer(fsm, a_wait_vrise_tmr);
108 break;
109 case OTG_STATE_A_VBUS_ERR:
110 break;
111 default:
112 break;
113 }
114}
115
116/* Called when entering a state */
117int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
118{
119 state_changed = 1;
120 if (fsm->otg->phy->state == new_state)
121 return 0;
122 VDBG("Set state: %s\n", usb_otg_state_string(new_state));
123 otg_leave_state(fsm, fsm->otg->phy->state);
124 switch (new_state) {
125 case OTG_STATE_B_IDLE:
126 otg_drv_vbus(fsm, 0);
127 otg_chrg_vbus(fsm, 0);
128 otg_loc_conn(fsm, 0);
129 otg_loc_sof(fsm, 0);
130 otg_set_protocol(fsm, PROTO_UNDEF);
131 otg_add_timer(fsm, b_se0_srp_tmr);
132 break;
133 case OTG_STATE_B_SRP_INIT:
134 otg_start_pulse(fsm);
135 otg_loc_sof(fsm, 0);
136 otg_set_protocol(fsm, PROTO_UNDEF);
137 otg_add_timer(fsm, b_srp_fail_tmr);
138 break;
139 case OTG_STATE_B_PERIPHERAL:
140 otg_chrg_vbus(fsm, 0);
141 otg_loc_conn(fsm, 1);
142 otg_loc_sof(fsm, 0);
143 otg_set_protocol(fsm, PROTO_GADGET);
144 break;
145 case OTG_STATE_B_WAIT_ACON:
146 otg_chrg_vbus(fsm, 0);
147 otg_loc_conn(fsm, 0);
148 otg_loc_sof(fsm, 0);
149 otg_set_protocol(fsm, PROTO_HOST);
150 otg_add_timer(fsm, b_ase0_brst_tmr);
151 fsm->a_bus_suspend = 0;
152 break;
153 case OTG_STATE_B_HOST:
154 otg_chrg_vbus(fsm, 0);
155 otg_loc_conn(fsm, 0);
156 otg_loc_sof(fsm, 1);
157 otg_set_protocol(fsm, PROTO_HOST);
158 usb_bus_start_enum(fsm->otg->host,
159 fsm->otg->host->otg_port);
160 break;
161 case OTG_STATE_A_IDLE:
162 otg_drv_vbus(fsm, 0);
163 otg_chrg_vbus(fsm, 0);
164 otg_loc_conn(fsm, 0);
165 otg_loc_sof(fsm, 0);
166 otg_set_protocol(fsm, PROTO_HOST);
167 break;
168 case OTG_STATE_A_WAIT_VRISE:
169 otg_drv_vbus(fsm, 1);
170 otg_loc_conn(fsm, 0);
171 otg_loc_sof(fsm, 0);
172 otg_set_protocol(fsm, PROTO_HOST);
173 otg_add_timer(fsm, a_wait_vrise_tmr);
174 break;
175 case OTG_STATE_A_WAIT_BCON:
176 otg_drv_vbus(fsm, 1);
177 otg_loc_conn(fsm, 0);
178 otg_loc_sof(fsm, 0);
179 otg_set_protocol(fsm, PROTO_HOST);
180 otg_add_timer(fsm, a_wait_bcon_tmr);
181 break;
182 case OTG_STATE_A_HOST:
183 otg_drv_vbus(fsm, 1);
184 otg_loc_conn(fsm, 0);
185 otg_loc_sof(fsm, 1);
186 otg_set_protocol(fsm, PROTO_HOST);
187 /*
188 * When HNP is triggered while a_bus_req = 0, a_host will
189 * suspend too fast to complete a_set_b_hnp_en
190 */
191 if (!fsm->a_bus_req || fsm->a_suspend_req)
192 otg_add_timer(fsm, a_wait_enum_tmr);
193 break;
194 case OTG_STATE_A_SUSPEND:
195 otg_drv_vbus(fsm, 1);
196 otg_loc_conn(fsm, 0);
197 otg_loc_sof(fsm, 0);
198 otg_set_protocol(fsm, PROTO_HOST);
199 otg_add_timer(fsm, a_aidl_bdis_tmr);
200
201 break;
202 case OTG_STATE_A_PERIPHERAL:
203 otg_loc_conn(fsm, 1);
204 otg_loc_sof(fsm, 0);
205 otg_set_protocol(fsm, PROTO_GADGET);
206 otg_drv_vbus(fsm, 1);
207 break;
208 case OTG_STATE_A_WAIT_VFALL:
209 otg_drv_vbus(fsm, 0);
210 otg_loc_conn(fsm, 0);
211 otg_loc_sof(fsm, 0);
212 otg_set_protocol(fsm, PROTO_HOST);
213 break;
214 case OTG_STATE_A_VBUS_ERR:
215 otg_drv_vbus(fsm, 0);
216 otg_loc_conn(fsm, 0);
217 otg_loc_sof(fsm, 0);
218 otg_set_protocol(fsm, PROTO_UNDEF);
219 break;
220 default:
221 break;
222 }
223
224 fsm->otg->phy->state = new_state;
225 return 0;
226}
227
228/* State change judgement */
229int otg_statemachine(struct otg_fsm *fsm)
230{
231 enum usb_otg_state state;
232 unsigned long flags;
233
234 spin_lock_irqsave(&fsm->lock, flags);
235
236 state = fsm->otg->phy->state;
237 state_changed = 0;
238 /* State machine state change judgement */
239
240 switch (state) {
241 case OTG_STATE_UNDEFINED:
242 VDBG("fsm->id = %d\n", fsm->id);
243 if (fsm->id)
244 otg_set_state(fsm, OTG_STATE_B_IDLE);
245 else
246 otg_set_state(fsm, OTG_STATE_A_IDLE);
247 break;
248 case OTG_STATE_B_IDLE:
249 if (!fsm->id)
250 otg_set_state(fsm, OTG_STATE_A_IDLE);
251 else if (fsm->b_sess_vld && fsm->otg->gadget)
252 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
253 else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
254 otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
255 break;
256 case OTG_STATE_B_SRP_INIT:
257 if (!fsm->id || fsm->b_srp_done)
258 otg_set_state(fsm, OTG_STATE_B_IDLE);
259 break;
260 case OTG_STATE_B_PERIPHERAL:
261 if (!fsm->id || !fsm->b_sess_vld)
262 otg_set_state(fsm, OTG_STATE_B_IDLE);
263 else if (fsm->b_bus_req && fsm->otg->
264 gadget->b_hnp_enable && fsm->a_bus_suspend)
265 otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
266 break;
267 case OTG_STATE_B_WAIT_ACON:
268 if (fsm->a_conn)
269 otg_set_state(fsm, OTG_STATE_B_HOST);
270 else if (!fsm->id || !fsm->b_sess_vld)
271 otg_set_state(fsm, OTG_STATE_B_IDLE);
272 else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
273 fsm->b_ase0_brst_tmout = 0;
274 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
275 }
276 break;
277 case OTG_STATE_B_HOST:
278 if (!fsm->id || !fsm->b_sess_vld)
279 otg_set_state(fsm, OTG_STATE_B_IDLE);
280 else if (!fsm->b_bus_req || !fsm->a_conn)
281 otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
282 break;
283 case OTG_STATE_A_IDLE:
284 if (fsm->id)
285 otg_set_state(fsm, OTG_STATE_B_IDLE);
286 else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
287 otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
288 break;
289 case OTG_STATE_A_WAIT_VRISE:
290 if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
291 fsm->a_wait_vrise_tmout) {
292 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
293 }
294 break;
295 case OTG_STATE_A_WAIT_BCON:
296 if (!fsm->a_vbus_vld)
297 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
298 else if (fsm->b_conn)
299 otg_set_state(fsm, OTG_STATE_A_HOST);
300 else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
301 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
302 break;
303 case OTG_STATE_A_HOST:
304 if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
305 fsm->otg->host->b_hnp_enable)
306 otg_set_state(fsm, OTG_STATE_A_SUSPEND);
307 else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
308 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
309 else if (!fsm->a_vbus_vld)
310 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
311 break;
312 case OTG_STATE_A_SUSPEND:
313 if (!fsm->b_conn && fsm->otg->host->b_hnp_enable)
314 otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
315 else if (!fsm->b_conn && !fsm->otg->host->b_hnp_enable)
316 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
317 else if (fsm->a_bus_req || fsm->b_bus_resume)
318 otg_set_state(fsm, OTG_STATE_A_HOST);
319 else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
320 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
321 else if (!fsm->a_vbus_vld)
322 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
323 break;
324 case OTG_STATE_A_PERIPHERAL:
325 if (fsm->id || fsm->a_bus_drop)
326 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
327 else if (fsm->b_bus_suspend)
328 otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
329 else if (!fsm->a_vbus_vld)
330 otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
331 break;
332 case OTG_STATE_A_WAIT_VFALL:
333 if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
334 !fsm->b_conn))
335 otg_set_state(fsm, OTG_STATE_A_IDLE);
336 break;
337 case OTG_STATE_A_VBUS_ERR:
338 if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
339 otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
340 break;
341 default:
342 break;
343 }
344 spin_unlock_irqrestore(&fsm->lock, flags);
345
346 VDBG("quit statemachine, changed = %d\n", state_changed);
347 return state_changed;
348}
diff --git a/drivers/usb/phy/otg_fsm.h b/drivers/usb/phy/otg_fsm.h
new file mode 100644
index 000000000000..c30a2e1d9e46
--- /dev/null
+++ b/drivers/usb/phy/otg_fsm.h
@@ -0,0 +1,154 @@
1/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify it
4 * under the terms of the GNU General Public License as published by the
5 * Free Software Foundation; either version 2 of the License, or (at your
6 * option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 */
17
18#undef DEBUG
19#undef VERBOSE
20
21#ifdef DEBUG
22#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt , \
23 __func__, ## args)
24#else
25#define DBG(fmt, args...) do {} while (0)
26#endif
27
28#ifdef VERBOSE
29#define VDBG DBG
30#else
31#define VDBG(stuff...) do {} while (0)
32#endif
33
34#ifdef VERBOSE
35#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__)
36#else
37#define MPC_LOC do {} while (0)
38#endif
39
40#define PROTO_UNDEF (0)
41#define PROTO_HOST (1)
42#define PROTO_GADGET (2)
43
44/* OTG state machine according to the OTG spec */
45struct otg_fsm {
46 /* Input */
47 int a_bus_resume;
48 int a_bus_suspend;
49 int a_conn;
50 int a_sess_vld;
51 int a_srp_det;
52 int a_vbus_vld;
53 int b_bus_resume;
54 int b_bus_suspend;
55 int b_conn;
56 int b_se0_srp;
57 int b_sess_end;
58 int b_sess_vld;
59 int id;
60
61 /* Internal variables */
62 int a_set_b_hnp_en;
63 int b_srp_done;
64 int b_hnp_enable;
65
66 /* Timeout indicator for timers */
67 int a_wait_vrise_tmout;
68 int a_wait_bcon_tmout;
69 int a_aidl_bdis_tmout;
70 int b_ase0_brst_tmout;
71
72 /* Informative variables */
73 int a_bus_drop;
74 int a_bus_req;
75 int a_clr_err;
76 int a_suspend_req;
77 int b_bus_req;
78
79 /* Output */
80 int drv_vbus;
81 int loc_conn;
82 int loc_sof;
83
84 struct otg_fsm_ops *ops;
85 struct usb_otg *otg;
86
87 /* Current usb protocol used: 0:undefine; 1:host; 2:client */
88 int protocol;
89 spinlock_t lock;
90};
91
92struct otg_fsm_ops {
93 void (*chrg_vbus)(int on);
94 void (*drv_vbus)(int on);
95 void (*loc_conn)(int on);
96 void (*loc_sof)(int on);
97 void (*start_pulse)(void);
98 void (*add_timer)(void *timer);
99 void (*del_timer)(void *timer);
100 int (*start_host)(struct otg_fsm *fsm, int on);
101 int (*start_gadget)(struct otg_fsm *fsm, int on);
102};
103
104
105static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
106{
107 fsm->ops->chrg_vbus(on);
108}
109
110static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
111{
112 if (fsm->drv_vbus != on) {
113 fsm->drv_vbus = on;
114 fsm->ops->drv_vbus(on);
115 }
116}
117
118static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
119{
120 if (fsm->loc_conn != on) {
121 fsm->loc_conn = on;
122 fsm->ops->loc_conn(on);
123 }
124}
125
126static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
127{
128 if (fsm->loc_sof != on) {
129 fsm->loc_sof = on;
130 fsm->ops->loc_sof(on);
131 }
132}
133
134static inline void otg_start_pulse(struct otg_fsm *fsm)
135{
136 fsm->ops->start_pulse();
137}
138
139static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
140{
141 fsm->ops->add_timer(timer);
142}
143
144static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
145{
146 fsm->ops->del_timer(timer);
147}
148
149int otg_statemachine(struct otg_fsm *fsm);
150
151/* Defined by device specific driver, for different timer implementation */
152extern struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr,
153 *a_aidl_bdis_tmr, *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr,
154 *a_wait_enum_tmr;
diff --git a/drivers/usb/phy/twl4030-usb.c b/drivers/usb/phy/twl4030-usb.c
new file mode 100644
index 000000000000..a994715a3101
--- /dev/null
+++ b/drivers/usb/phy/twl4030-usb.c
@@ -0,0 +1,728 @@
1/*
2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
3 *
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Current status:
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
25 */
26
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/platform_device.h>
31#include <linux/spinlock.h>
32#include <linux/workqueue.h>
33#include <linux/io.h>
34#include <linux/delay.h>
35#include <linux/usb/otg.h>
36#include <linux/usb/musb-omap.h>
37#include <linux/usb/ulpi.h>
38#include <linux/i2c/twl.h>
39#include <linux/regulator/consumer.h>
40#include <linux/err.h>
41#include <linux/slab.h>
42
43/* Register defines */
44
45#define MCPC_CTRL 0x30
46#define MCPC_CTRL_RTSOL (1 << 7)
47#define MCPC_CTRL_EXTSWR (1 << 6)
48#define MCPC_CTRL_EXTSWC (1 << 5)
49#define MCPC_CTRL_VOICESW (1 << 4)
50#define MCPC_CTRL_OUT64K (1 << 3)
51#define MCPC_CTRL_RTSCTSSW (1 << 2)
52#define MCPC_CTRL_HS_UART (1 << 0)
53
54#define MCPC_IO_CTRL 0x33
55#define MCPC_IO_CTRL_MICBIASEN (1 << 5)
56#define MCPC_IO_CTRL_CTS_NPU (1 << 4)
57#define MCPC_IO_CTRL_RXD_PU (1 << 3)
58#define MCPC_IO_CTRL_TXDTYP (1 << 2)
59#define MCPC_IO_CTRL_CTSTYP (1 << 1)
60#define MCPC_IO_CTRL_RTSTYP (1 << 0)
61
62#define MCPC_CTRL2 0x36
63#define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
64
65#define OTHER_FUNC_CTRL 0x80
66#define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
67#define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
68
69#define OTHER_IFC_CTRL 0x83
70#define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
71#define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
72#define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
73#define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
74#define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
75#define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
76
77#define OTHER_INT_EN_RISE 0x86
78#define OTHER_INT_EN_FALL 0x89
79#define OTHER_INT_STS 0x8C
80#define OTHER_INT_LATCH 0x8D
81#define OTHER_INT_VB_SESS_VLD (1 << 7)
82#define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
83#define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
84#define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
85#define OTHER_INT_MANU (1 << 1)
86#define OTHER_INT_ABNORMAL_STRESS (1 << 0)
87
88#define ID_STATUS 0x96
89#define ID_RES_FLOAT (1 << 4)
90#define ID_RES_440K (1 << 3)
91#define ID_RES_200K (1 << 2)
92#define ID_RES_102K (1 << 1)
93#define ID_RES_GND (1 << 0)
94
95#define POWER_CTRL 0xAC
96#define POWER_CTRL_OTG_ENAB (1 << 5)
97
98#define OTHER_IFC_CTRL2 0xAF
99#define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
100#define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
101#define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
102#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
103#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
104#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
105
106#define REG_CTRL_EN 0xB2
107#define REG_CTRL_ERROR 0xB5
108#define ULPI_I2C_CONFLICT_INTEN (1 << 0)
109
110#define OTHER_FUNC_CTRL2 0xB8
111#define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
112
113/* following registers do not have separate _clr and _set registers */
114#define VBUS_DEBOUNCE 0xC0
115#define ID_DEBOUNCE 0xC1
116#define VBAT_TIMER 0xD3
117#define PHY_PWR_CTRL 0xFD
118#define PHY_PWR_PHYPWD (1 << 0)
119#define PHY_CLK_CTRL 0xFE
120#define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
121#define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
122#define REQ_PHY_DPLL_CLK (1 << 0)
123#define PHY_CLK_CTRL_STS 0xFF
124#define PHY_DPLL_CLK (1 << 0)
125
126/* In module TWL_MODULE_PM_MASTER */
127#define STS_HW_CONDITIONS 0x0F
128
129/* In module TWL_MODULE_PM_RECEIVER */
130#define VUSB_DEDICATED1 0x7D
131#define VUSB_DEDICATED2 0x7E
132#define VUSB1V5_DEV_GRP 0x71
133#define VUSB1V5_TYPE 0x72
134#define VUSB1V5_REMAP 0x73
135#define VUSB1V8_DEV_GRP 0x74
136#define VUSB1V8_TYPE 0x75
137#define VUSB1V8_REMAP 0x76
138#define VUSB3V1_DEV_GRP 0x77
139#define VUSB3V1_TYPE 0x78
140#define VUSB3V1_REMAP 0x79
141
142/* In module TWL4030_MODULE_INTBR */
143#define PMBR1 0x0D
144#define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
145
146struct twl4030_usb {
147 struct usb_phy phy;
148 struct device *dev;
149
150 /* TWL4030 internal USB regulator supplies */
151 struct regulator *usb1v5;
152 struct regulator *usb1v8;
153 struct regulator *usb3v1;
154
155 /* for vbus reporting with irqs disabled */
156 spinlock_t lock;
157
158 /* pin configuration */
159 enum twl4030_usb_mode usb_mode;
160
161 int irq;
162 enum omap_musb_vbus_id_status linkstat;
163 bool vbus_supplied;
164 u8 asleep;
165 bool irq_enabled;
166};
167
168/* internal define on top of container_of */
169#define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
170
171/*-------------------------------------------------------------------------*/
172
173static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
174 u8 module, u8 data, u8 address)
175{
176 u8 check;
177
178 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
179 (twl_i2c_read_u8(module, &check, address) >= 0) &&
180 (check == data))
181 return 0;
182 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
183 1, module, address, check, data);
184
185 /* Failed once: Try again */
186 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
187 (twl_i2c_read_u8(module, &check, address) >= 0) &&
188 (check == data))
189 return 0;
190 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
191 2, module, address, check, data);
192
193 /* Failed again: Return error */
194 return -EBUSY;
195}
196
197#define twl4030_usb_write_verify(twl, address, data) \
198 twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
199
200static inline int twl4030_usb_write(struct twl4030_usb *twl,
201 u8 address, u8 data)
202{
203 int ret = 0;
204
205 ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
206 if (ret < 0)
207 dev_dbg(twl->dev,
208 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
209 return ret;
210}
211
212static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
213{
214 u8 data;
215 int ret = 0;
216
217 ret = twl_i2c_read_u8(module, &data, address);
218 if (ret >= 0)
219 ret = data;
220 else
221 dev_dbg(twl->dev,
222 "TWL4030:readb[0x%x,0x%x] Error %d\n",
223 module, address, ret);
224
225 return ret;
226}
227
228static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
229{
230 return twl4030_readb(twl, TWL_MODULE_USB, address);
231}
232
233/*-------------------------------------------------------------------------*/
234
235static inline int
236twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
237{
238 return twl4030_usb_write(twl, ULPI_SET(reg), bits);
239}
240
241static inline int
242twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
243{
244 return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
245}
246
247/*-------------------------------------------------------------------------*/
248
249static enum omap_musb_vbus_id_status
250 twl4030_usb_linkstat(struct twl4030_usb *twl)
251{
252 int status;
253 enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
254
255 twl->vbus_supplied = false;
256
257 /*
258 * For ID/VBUS sensing, see manual section 15.4.8 ...
259 * except when using only battery backup power, two
260 * comparators produce VBUS_PRES and ID_PRES signals,
261 * which don't match docs elsewhere. But ... BIT(7)
262 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
263 * seem to match up. If either is true the USB_PRES
264 * signal is active, the OTG module is activated, and
265 * its interrupt may be raised (may wake the system).
266 */
267 status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
268 if (status < 0)
269 dev_err(twl->dev, "USB link status err %d\n", status);
270 else if (status & (BIT(7) | BIT(2))) {
271 if (status & (BIT(7)))
272 twl->vbus_supplied = true;
273
274 if (status & BIT(2))
275 linkstat = OMAP_MUSB_ID_GROUND;
276 else
277 linkstat = OMAP_MUSB_VBUS_VALID;
278 } else {
279 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
280 linkstat = OMAP_MUSB_VBUS_OFF;
281 }
282
283 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
284 status, status, linkstat);
285
286 /* REVISIT this assumes host and peripheral controllers
287 * are registered, and that both are active...
288 */
289
290 spin_lock_irq(&twl->lock);
291 twl->linkstat = linkstat;
292 spin_unlock_irq(&twl->lock);
293
294 return linkstat;
295}
296
297static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
298{
299 twl->usb_mode = mode;
300
301 switch (mode) {
302 case T2_USB_MODE_ULPI:
303 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
304 ULPI_IFC_CTRL_CARKITMODE);
305 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
306 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
307 ULPI_FUNC_CTRL_XCVRSEL_MASK |
308 ULPI_FUNC_CTRL_OPMODE_MASK);
309 break;
310 case -1:
311 /* FIXME: power on defaults */
312 break;
313 default:
314 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
315 mode);
316 break;
317 };
318}
319
320static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
321{
322 unsigned long timeout;
323 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
324
325 if (val >= 0) {
326 if (on) {
327 /* enable DPLL to access PHY registers over I2C */
328 val |= REQ_PHY_DPLL_CLK;
329 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
330 (u8)val) < 0);
331
332 timeout = jiffies + HZ;
333 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
334 PHY_DPLL_CLK)
335 && time_before(jiffies, timeout))
336 udelay(10);
337 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
338 PHY_DPLL_CLK))
339 dev_err(twl->dev, "Timeout setting T2 HSUSB "
340 "PHY DPLL clock\n");
341 } else {
342 /* let ULPI control the DPLL clock */
343 val &= ~REQ_PHY_DPLL_CLK;
344 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
345 (u8)val) < 0);
346 }
347 }
348}
349
350static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
351{
352 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
353
354 if (on)
355 pwr &= ~PHY_PWR_PHYPWD;
356 else
357 pwr |= PHY_PWR_PHYPWD;
358
359 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
360}
361
362static void twl4030_phy_power(struct twl4030_usb *twl, int on)
363{
364 if (on) {
365 regulator_enable(twl->usb3v1);
366 regulator_enable(twl->usb1v8);
367 /*
368 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
369 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
370 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
371 * SLEEP. We work around this by clearing the bit after usv3v1
372 * is re-activated. This ensures that VUSB3V1 is really active.
373 */
374 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
375 regulator_enable(twl->usb1v5);
376 __twl4030_phy_power(twl, 1);
377 twl4030_usb_write(twl, PHY_CLK_CTRL,
378 twl4030_usb_read(twl, PHY_CLK_CTRL) |
379 (PHY_CLK_CTRL_CLOCKGATING_EN |
380 PHY_CLK_CTRL_CLK32K_EN));
381 } else {
382 __twl4030_phy_power(twl, 0);
383 regulator_disable(twl->usb1v5);
384 regulator_disable(twl->usb1v8);
385 regulator_disable(twl->usb3v1);
386 }
387}
388
389static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
390{
391 if (twl->asleep)
392 return;
393
394 twl4030_phy_power(twl, 0);
395 twl->asleep = 1;
396 dev_dbg(twl->dev, "%s\n", __func__);
397}
398
399static void __twl4030_phy_resume(struct twl4030_usb *twl)
400{
401 twl4030_phy_power(twl, 1);
402 twl4030_i2c_access(twl, 1);
403 twl4030_usb_set_mode(twl, twl->usb_mode);
404 if (twl->usb_mode == T2_USB_MODE_ULPI)
405 twl4030_i2c_access(twl, 0);
406}
407
408static void twl4030_phy_resume(struct twl4030_usb *twl)
409{
410 if (!twl->asleep)
411 return;
412 __twl4030_phy_resume(twl);
413 twl->asleep = 0;
414 dev_dbg(twl->dev, "%s\n", __func__);
415}
416
417static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
418{
419 /* Enable writing to power configuration registers */
420 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
421 TWL4030_PM_MASTER_PROTECT_KEY);
422
423 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
424 TWL4030_PM_MASTER_PROTECT_KEY);
425
426 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
427 /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
428
429 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
430 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
431
432 /* Initialize 3.1V regulator */
433 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
434
435 twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
436 if (IS_ERR(twl->usb3v1))
437 return -ENODEV;
438
439 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
440
441 /* Initialize 1.5V regulator */
442 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
443
444 twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
445 if (IS_ERR(twl->usb1v5))
446 goto fail1;
447
448 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
449
450 /* Initialize 1.8V regulator */
451 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
452
453 twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
454 if (IS_ERR(twl->usb1v8))
455 goto fail2;
456
457 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
458
459 /* disable access to power configuration registers */
460 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
461 TWL4030_PM_MASTER_PROTECT_KEY);
462
463 return 0;
464
465fail2:
466 regulator_put(twl->usb1v5);
467 twl->usb1v5 = NULL;
468fail1:
469 regulator_put(twl->usb3v1);
470 twl->usb3v1 = NULL;
471 return -ENODEV;
472}
473
474static ssize_t twl4030_usb_vbus_show(struct device *dev,
475 struct device_attribute *attr, char *buf)
476{
477 struct twl4030_usb *twl = dev_get_drvdata(dev);
478 unsigned long flags;
479 int ret = -EINVAL;
480
481 spin_lock_irqsave(&twl->lock, flags);
482 ret = sprintf(buf, "%s\n",
483 twl->vbus_supplied ? "on" : "off");
484 spin_unlock_irqrestore(&twl->lock, flags);
485
486 return ret;
487}
488static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
489
490static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
491{
492 struct twl4030_usb *twl = _twl;
493 enum omap_musb_vbus_id_status status;
494
495 status = twl4030_usb_linkstat(twl);
496 if (status > 0) {
497 /* FIXME add a set_power() method so that B-devices can
498 * configure the charger appropriately. It's not always
499 * correct to consume VBUS power, and how much current to
500 * consume is a function of the USB configuration chosen
501 * by the host.
502 *
503 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
504 * its disconnect() sibling, when changing to/from the
505 * USB_LINK_VBUS state. musb_hdrc won't care until it
506 * starts to handle softconnect right.
507 */
508 if (status == OMAP_MUSB_VBUS_OFF ||
509 status == OMAP_MUSB_ID_FLOAT)
510 twl4030_phy_suspend(twl, 0);
511 else
512 twl4030_phy_resume(twl);
513
514 omap_musb_mailbox(twl->linkstat);
515 }
516 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
517
518 return IRQ_HANDLED;
519}
520
521static void twl4030_usb_phy_init(struct twl4030_usb *twl)
522{
523 enum omap_musb_vbus_id_status status;
524
525 status = twl4030_usb_linkstat(twl);
526 if (status > 0) {
527 if (status == OMAP_MUSB_VBUS_OFF ||
528 status == OMAP_MUSB_ID_FLOAT) {
529 __twl4030_phy_power(twl, 0);
530 twl->asleep = 1;
531 } else {
532 __twl4030_phy_resume(twl);
533 twl->asleep = 0;
534 }
535
536 omap_musb_mailbox(twl->linkstat);
537 }
538 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
539}
540
541static int twl4030_set_suspend(struct usb_phy *x, int suspend)
542{
543 struct twl4030_usb *twl = phy_to_twl(x);
544
545 if (suspend)
546 twl4030_phy_suspend(twl, 1);
547 else
548 twl4030_phy_resume(twl);
549
550 return 0;
551}
552
553static int twl4030_set_peripheral(struct usb_otg *otg,
554 struct usb_gadget *gadget)
555{
556 if (!otg)
557 return -ENODEV;
558
559 otg->gadget = gadget;
560 if (!gadget)
561 otg->phy->state = OTG_STATE_UNDEFINED;
562
563 return 0;
564}
565
566static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
567{
568 if (!otg)
569 return -ENODEV;
570
571 otg->host = host;
572 if (!host)
573 otg->phy->state = OTG_STATE_UNDEFINED;
574
575 return 0;
576}
577
578static int twl4030_usb_probe(struct platform_device *pdev)
579{
580 struct twl4030_usb_data *pdata = pdev->dev.platform_data;
581 struct twl4030_usb *twl;
582 int status, err;
583 struct usb_otg *otg;
584 struct device_node *np = pdev->dev.of_node;
585
586 twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
587 if (!twl)
588 return -ENOMEM;
589
590 if (np)
591 of_property_read_u32(np, "usb_mode",
592 (enum twl4030_usb_mode *)&twl->usb_mode);
593 else if (pdata)
594 twl->usb_mode = pdata->usb_mode;
595 else {
596 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
597 return -EINVAL;
598 }
599
600 otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
601 if (!otg)
602 return -ENOMEM;
603
604 twl->dev = &pdev->dev;
605 twl->irq = platform_get_irq(pdev, 0);
606 twl->vbus_supplied = false;
607 twl->asleep = 1;
608 twl->linkstat = OMAP_MUSB_UNKNOWN;
609
610 twl->phy.dev = twl->dev;
611 twl->phy.label = "twl4030";
612 twl->phy.otg = otg;
613 twl->phy.type = USB_PHY_TYPE_USB2;
614 twl->phy.set_suspend = twl4030_set_suspend;
615
616 otg->phy = &twl->phy;
617 otg->set_host = twl4030_set_host;
618 otg->set_peripheral = twl4030_set_peripheral;
619
620 /* init spinlock for workqueue */
621 spin_lock_init(&twl->lock);
622
623 err = twl4030_usb_ldo_init(twl);
624 if (err) {
625 dev_err(&pdev->dev, "ldo init failed\n");
626 return err;
627 }
628 usb_add_phy_dev(&twl->phy);
629
630 platform_set_drvdata(pdev, twl);
631 if (device_create_file(&pdev->dev, &dev_attr_vbus))
632 dev_warn(&pdev->dev, "could not create sysfs file\n");
633
634 /* Our job is to use irqs and status from the power module
635 * to keep the transceiver disabled when nothing's connected.
636 *
637 * FIXME we actually shouldn't start enabling it until the
638 * USB controller drivers have said they're ready, by calling
639 * set_host() and/or set_peripheral() ... OTG_capable boards
640 * need both handles, otherwise just one suffices.
641 */
642 twl->irq_enabled = true;
643 status = request_threaded_irq(twl->irq, NULL, twl4030_usb_irq,
644 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
645 IRQF_ONESHOT, "twl4030_usb", twl);
646 if (status < 0) {
647 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
648 twl->irq, status);
649 return status;
650 }
651
652 /* Power down phy or make it work according to
653 * current link state.
654 */
655 twl4030_usb_phy_init(twl);
656
657 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
658 return 0;
659}
660
661static int __exit twl4030_usb_remove(struct platform_device *pdev)
662{
663 struct twl4030_usb *twl = platform_get_drvdata(pdev);
664 int val;
665
666 free_irq(twl->irq, twl);
667 device_remove_file(twl->dev, &dev_attr_vbus);
668
669 /* set transceiver mode to power on defaults */
670 twl4030_usb_set_mode(twl, -1);
671
672 /* autogate 60MHz ULPI clock,
673 * clear dpll clock request for i2c access,
674 * disable 32KHz
675 */
676 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
677 if (val >= 0) {
678 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
679 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
680 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
681 }
682
683 /* disable complete OTG block */
684 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
685
686 if (!twl->asleep)
687 twl4030_phy_power(twl, 0);
688 regulator_put(twl->usb1v5);
689 regulator_put(twl->usb1v8);
690 regulator_put(twl->usb3v1);
691
692 return 0;
693}
694
695#ifdef CONFIG_OF
696static const struct of_device_id twl4030_usb_id_table[] = {
697 { .compatible = "ti,twl4030-usb" },
698 {}
699};
700MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
701#endif
702
703static struct platform_driver twl4030_usb_driver = {
704 .probe = twl4030_usb_probe,
705 .remove = __exit_p(twl4030_usb_remove),
706 .driver = {
707 .name = "twl4030_usb",
708 .owner = THIS_MODULE,
709 .of_match_table = of_match_ptr(twl4030_usb_id_table),
710 },
711};
712
713static int __init twl4030_usb_init(void)
714{
715 return platform_driver_register(&twl4030_usb_driver);
716}
717subsys_initcall(twl4030_usb_init);
718
719static void __exit twl4030_usb_exit(void)
720{
721 platform_driver_unregister(&twl4030_usb_driver);
722}
723module_exit(twl4030_usb_exit);
724
725MODULE_ALIAS("platform:twl4030_usb");
726MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
727MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
728MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/twl6030-usb.c b/drivers/usb/phy/twl6030-usb.c
new file mode 100644
index 000000000000..8cd6cf49bdbd
--- /dev/null
+++ b/drivers/usb/phy/twl6030-usb.c
@@ -0,0 +1,446 @@
1/*
2 * twl6030_usb - TWL6030 USB transceiver, talking to OMAP OTG driver.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * Author: Hema HK <hemahk@ti.com>
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/usb/musb-omap.h>
29#include <linux/usb/phy_companion.h>
30#include <linux/usb/omap_usb.h>
31#include <linux/i2c/twl.h>
32#include <linux/regulator/consumer.h>
33#include <linux/err.h>
34#include <linux/slab.h>
35#include <linux/delay.h>
36
37/* usb register definitions */
38#define USB_VENDOR_ID_LSB 0x00
39#define USB_VENDOR_ID_MSB 0x01
40#define USB_PRODUCT_ID_LSB 0x02
41#define USB_PRODUCT_ID_MSB 0x03
42#define USB_VBUS_CTRL_SET 0x04
43#define USB_VBUS_CTRL_CLR 0x05
44#define USB_ID_CTRL_SET 0x06
45#define USB_ID_CTRL_CLR 0x07
46#define USB_VBUS_INT_SRC 0x08
47#define USB_VBUS_INT_LATCH_SET 0x09
48#define USB_VBUS_INT_LATCH_CLR 0x0A
49#define USB_VBUS_INT_EN_LO_SET 0x0B
50#define USB_VBUS_INT_EN_LO_CLR 0x0C
51#define USB_VBUS_INT_EN_HI_SET 0x0D
52#define USB_VBUS_INT_EN_HI_CLR 0x0E
53#define USB_ID_INT_SRC 0x0F
54#define USB_ID_INT_LATCH_SET 0x10
55#define USB_ID_INT_LATCH_CLR 0x11
56
57#define USB_ID_INT_EN_LO_SET 0x12
58#define USB_ID_INT_EN_LO_CLR 0x13
59#define USB_ID_INT_EN_HI_SET 0x14
60#define USB_ID_INT_EN_HI_CLR 0x15
61#define USB_OTG_ADP_CTRL 0x16
62#define USB_OTG_ADP_HIGH 0x17
63#define USB_OTG_ADP_LOW 0x18
64#define USB_OTG_ADP_RISE 0x19
65#define USB_OTG_REVISION 0x1A
66
67/* to be moved to LDO */
68#define TWL6030_MISC2 0xE5
69#define TWL6030_CFG_LDO_PD2 0xF5
70#define TWL6030_BACKUP_REG 0xFA
71
72#define STS_HW_CONDITIONS 0x21
73
74/* In module TWL6030_MODULE_PM_MASTER */
75#define STS_HW_CONDITIONS 0x21
76#define STS_USB_ID BIT(2)
77
78/* In module TWL6030_MODULE_PM_RECEIVER */
79#define VUSB_CFG_TRANS 0x71
80#define VUSB_CFG_STATE 0x72
81#define VUSB_CFG_VOLTAGE 0x73
82
83/* in module TWL6030_MODULE_MAIN_CHARGE */
84
85#define CHARGERUSB_CTRL1 0x8
86
87#define CONTROLLER_STAT1 0x03
88#define VBUS_DET BIT(2)
89
90struct twl6030_usb {
91 struct phy_companion comparator;
92 struct device *dev;
93
94 /* for vbus reporting with irqs disabled */
95 spinlock_t lock;
96
97 struct regulator *usb3v3;
98
99 /* used to set vbus, in atomic path */
100 struct work_struct set_vbus_work;
101
102 int irq1;
103 int irq2;
104 enum omap_musb_vbus_id_status linkstat;
105 u8 asleep;
106 bool irq_enabled;
107 bool vbus_enable;
108 const char *regulator;
109};
110
111#define comparator_to_twl(x) container_of((x), struct twl6030_usb, comparator)
112
113/*-------------------------------------------------------------------------*/
114
115static inline int twl6030_writeb(struct twl6030_usb *twl, u8 module,
116 u8 data, u8 address)
117{
118 int ret = 0;
119
120 ret = twl_i2c_write_u8(module, data, address);
121 if (ret < 0)
122 dev_err(twl->dev,
123 "Write[0x%x] Error %d\n", address, ret);
124 return ret;
125}
126
127static inline u8 twl6030_readb(struct twl6030_usb *twl, u8 module, u8 address)
128{
129 u8 data, ret = 0;
130
131 ret = twl_i2c_read_u8(module, &data, address);
132 if (ret >= 0)
133 ret = data;
134 else
135 dev_err(twl->dev,
136 "readb[0x%x,0x%x] Error %d\n",
137 module, address, ret);
138 return ret;
139}
140
141static int twl6030_start_srp(struct phy_companion *comparator)
142{
143 struct twl6030_usb *twl = comparator_to_twl(comparator);
144
145 twl6030_writeb(twl, TWL_MODULE_USB, 0x24, USB_VBUS_CTRL_SET);
146 twl6030_writeb(twl, TWL_MODULE_USB, 0x84, USB_VBUS_CTRL_SET);
147
148 mdelay(100);
149 twl6030_writeb(twl, TWL_MODULE_USB, 0xa0, USB_VBUS_CTRL_CLR);
150
151 return 0;
152}
153
154static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
155{
156 /* Set to OTG_REV 1.3 and turn on the ID_WAKEUP_COMP */
157 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x1, TWL6030_BACKUP_REG);
158
159 /* Program CFG_LDO_PD2 register and set VUSB bit */
160 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x1, TWL6030_CFG_LDO_PD2);
161
162 /* Program MISC2 register and set bit VUSB_IN_VBAT */
163 twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x10, TWL6030_MISC2);
164
165 twl->usb3v3 = regulator_get(twl->dev, twl->regulator);
166 if (IS_ERR(twl->usb3v3))
167 return -ENODEV;
168
169 /* Program the USB_VBUS_CTRL_SET and set VBUS_ACT_COMP bit */
170 twl6030_writeb(twl, TWL_MODULE_USB, 0x4, USB_VBUS_CTRL_SET);
171
172 /*
173 * Program the USB_ID_CTRL_SET register to enable GND drive
174 * and the ID comparators
175 */
176 twl6030_writeb(twl, TWL_MODULE_USB, 0x14, USB_ID_CTRL_SET);
177
178 return 0;
179}
180
181static ssize_t twl6030_usb_vbus_show(struct device *dev,
182 struct device_attribute *attr, char *buf)
183{
184 struct twl6030_usb *twl = dev_get_drvdata(dev);
185 unsigned long flags;
186 int ret = -EINVAL;
187
188 spin_lock_irqsave(&twl->lock, flags);
189
190 switch (twl->linkstat) {
191 case OMAP_MUSB_VBUS_VALID:
192 ret = snprintf(buf, PAGE_SIZE, "vbus\n");
193 break;
194 case OMAP_MUSB_ID_GROUND:
195 ret = snprintf(buf, PAGE_SIZE, "id\n");
196 break;
197 case OMAP_MUSB_VBUS_OFF:
198 ret = snprintf(buf, PAGE_SIZE, "none\n");
199 break;
200 default:
201 ret = snprintf(buf, PAGE_SIZE, "UNKNOWN\n");
202 }
203 spin_unlock_irqrestore(&twl->lock, flags);
204
205 return ret;
206}
207static DEVICE_ATTR(vbus, 0444, twl6030_usb_vbus_show, NULL);
208
209static irqreturn_t twl6030_usb_irq(int irq, void *_twl)
210{
211 struct twl6030_usb *twl = _twl;
212 enum omap_musb_vbus_id_status status = OMAP_MUSB_UNKNOWN;
213 u8 vbus_state, hw_state;
214
215 hw_state = twl6030_readb(twl, TWL6030_MODULE_ID0, STS_HW_CONDITIONS);
216
217 vbus_state = twl6030_readb(twl, TWL_MODULE_MAIN_CHARGE,
218 CONTROLLER_STAT1);
219 if (!(hw_state & STS_USB_ID)) {
220 if (vbus_state & VBUS_DET) {
221 regulator_enable(twl->usb3v3);
222 twl->asleep = 1;
223 status = OMAP_MUSB_VBUS_VALID;
224 twl->linkstat = status;
225 omap_musb_mailbox(status);
226 } else {
227 if (twl->linkstat != OMAP_MUSB_UNKNOWN) {
228 status = OMAP_MUSB_VBUS_OFF;
229 twl->linkstat = status;
230 omap_musb_mailbox(status);
231 if (twl->asleep) {
232 regulator_disable(twl->usb3v3);
233 twl->asleep = 0;
234 }
235 }
236 }
237 }
238 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
239
240 return IRQ_HANDLED;
241}
242
243static irqreturn_t twl6030_usbotg_irq(int irq, void *_twl)
244{
245 struct twl6030_usb *twl = _twl;
246 enum omap_musb_vbus_id_status status = OMAP_MUSB_UNKNOWN;
247 u8 hw_state;
248
249 hw_state = twl6030_readb(twl, TWL6030_MODULE_ID0, STS_HW_CONDITIONS);
250
251 if (hw_state & STS_USB_ID) {
252
253 regulator_enable(twl->usb3v3);
254 twl->asleep = 1;
255 twl6030_writeb(twl, TWL_MODULE_USB, 0x1, USB_ID_INT_EN_HI_CLR);
256 twl6030_writeb(twl, TWL_MODULE_USB, 0x10, USB_ID_INT_EN_HI_SET);
257 status = OMAP_MUSB_ID_GROUND;
258 twl->linkstat = status;
259 omap_musb_mailbox(status);
260 } else {
261 twl6030_writeb(twl, TWL_MODULE_USB, 0x10, USB_ID_INT_EN_HI_CLR);
262 twl6030_writeb(twl, TWL_MODULE_USB, 0x1, USB_ID_INT_EN_HI_SET);
263 }
264 twl6030_writeb(twl, TWL_MODULE_USB, status, USB_ID_INT_LATCH_CLR);
265
266 return IRQ_HANDLED;
267}
268
269static int twl6030_enable_irq(struct twl6030_usb *twl)
270{
271 twl6030_writeb(twl, TWL_MODULE_USB, 0x1, USB_ID_INT_EN_HI_SET);
272 twl6030_interrupt_unmask(0x05, REG_INT_MSK_LINE_C);
273 twl6030_interrupt_unmask(0x05, REG_INT_MSK_STS_C);
274
275 twl6030_interrupt_unmask(TWL6030_CHARGER_CTRL_INT_MASK,
276 REG_INT_MSK_LINE_C);
277 twl6030_interrupt_unmask(TWL6030_CHARGER_CTRL_INT_MASK,
278 REG_INT_MSK_STS_C);
279 twl6030_usb_irq(twl->irq2, twl);
280 twl6030_usbotg_irq(twl->irq1, twl);
281
282 return 0;
283}
284
285static void otg_set_vbus_work(struct work_struct *data)
286{
287 struct twl6030_usb *twl = container_of(data, struct twl6030_usb,
288 set_vbus_work);
289
290 /*
291 * Start driving VBUS. Set OPA_MODE bit in CHARGERUSB_CTRL1
292 * register. This enables boost mode.
293 */
294
295 if (twl->vbus_enable)
296 twl6030_writeb(twl, TWL_MODULE_MAIN_CHARGE , 0x40,
297 CHARGERUSB_CTRL1);
298 else
299 twl6030_writeb(twl, TWL_MODULE_MAIN_CHARGE , 0x00,
300 CHARGERUSB_CTRL1);
301}
302
303static int twl6030_set_vbus(struct phy_companion *comparator, bool enabled)
304{
305 struct twl6030_usb *twl = comparator_to_twl(comparator);
306
307 twl->vbus_enable = enabled;
308 schedule_work(&twl->set_vbus_work);
309
310 return 0;
311}
312
313static int twl6030_usb_probe(struct platform_device *pdev)
314{
315 u32 ret;
316 struct twl6030_usb *twl;
317 int status, err;
318 struct device_node *np = pdev->dev.of_node;
319 struct device *dev = &pdev->dev;
320 struct twl4030_usb_data *pdata = dev->platform_data;
321
322 twl = devm_kzalloc(dev, sizeof *twl, GFP_KERNEL);
323 if (!twl)
324 return -ENOMEM;
325
326 twl->dev = &pdev->dev;
327 twl->irq1 = platform_get_irq(pdev, 0);
328 twl->irq2 = platform_get_irq(pdev, 1);
329 twl->linkstat = OMAP_MUSB_UNKNOWN;
330
331 twl->comparator.set_vbus = twl6030_set_vbus;
332 twl->comparator.start_srp = twl6030_start_srp;
333
334 ret = omap_usb2_set_comparator(&twl->comparator);
335 if (ret == -ENODEV) {
336 dev_info(&pdev->dev, "phy not ready, deferring probe");
337 return -EPROBE_DEFER;
338 }
339
340 if (np) {
341 twl->regulator = "usb";
342 } else if (pdata) {
343 if (pdata->features & TWL6025_SUBCLASS)
344 twl->regulator = "ldousb";
345 else
346 twl->regulator = "vusb";
347 } else {
348 dev_err(&pdev->dev, "twl6030 initialized without pdata\n");
349 return -EINVAL;
350 }
351
352 /* init spinlock for workqueue */
353 spin_lock_init(&twl->lock);
354
355 err = twl6030_usb_ldo_init(twl);
356 if (err) {
357 dev_err(&pdev->dev, "ldo init failed\n");
358 return err;
359 }
360
361 platform_set_drvdata(pdev, twl);
362 if (device_create_file(&pdev->dev, &dev_attr_vbus))
363 dev_warn(&pdev->dev, "could not create sysfs file\n");
364
365 INIT_WORK(&twl->set_vbus_work, otg_set_vbus_work);
366
367 twl->irq_enabled = true;
368 status = request_threaded_irq(twl->irq1, NULL, twl6030_usbotg_irq,
369 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
370 "twl6030_usb", twl);
371 if (status < 0) {
372 dev_err(&pdev->dev, "can't get IRQ %d, err %d\n",
373 twl->irq1, status);
374 device_remove_file(twl->dev, &dev_attr_vbus);
375 return status;
376 }
377
378 status = request_threaded_irq(twl->irq2, NULL, twl6030_usb_irq,
379 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
380 "twl6030_usb", twl);
381 if (status < 0) {
382 dev_err(&pdev->dev, "can't get IRQ %d, err %d\n",
383 twl->irq2, status);
384 free_irq(twl->irq1, twl);
385 device_remove_file(twl->dev, &dev_attr_vbus);
386 return status;
387 }
388
389 twl->asleep = 0;
390 twl6030_enable_irq(twl);
391 dev_info(&pdev->dev, "Initialized TWL6030 USB module\n");
392
393 return 0;
394}
395
396static int __exit twl6030_usb_remove(struct platform_device *pdev)
397{
398 struct twl6030_usb *twl = platform_get_drvdata(pdev);
399
400 twl6030_interrupt_mask(TWL6030_USBOTG_INT_MASK,
401 REG_INT_MSK_LINE_C);
402 twl6030_interrupt_mask(TWL6030_USBOTG_INT_MASK,
403 REG_INT_MSK_STS_C);
404 free_irq(twl->irq1, twl);
405 free_irq(twl->irq2, twl);
406 regulator_put(twl->usb3v3);
407 device_remove_file(twl->dev, &dev_attr_vbus);
408 cancel_work_sync(&twl->set_vbus_work);
409
410 return 0;
411}
412
413#ifdef CONFIG_OF
414static const struct of_device_id twl6030_usb_id_table[] = {
415 { .compatible = "ti,twl6030-usb" },
416 {}
417};
418MODULE_DEVICE_TABLE(of, twl6030_usb_id_table);
419#endif
420
421static struct platform_driver twl6030_usb_driver = {
422 .probe = twl6030_usb_probe,
423 .remove = __exit_p(twl6030_usb_remove),
424 .driver = {
425 .name = "twl6030_usb",
426 .owner = THIS_MODULE,
427 .of_match_table = of_match_ptr(twl6030_usb_id_table),
428 },
429};
430
431static int __init twl6030_usb_init(void)
432{
433 return platform_driver_register(&twl6030_usb_driver);
434}
435subsys_initcall(twl6030_usb_init);
436
437static void __exit twl6030_usb_exit(void)
438{
439 platform_driver_unregister(&twl6030_usb_driver);
440}
441module_exit(twl6030_usb_exit);
442
443MODULE_ALIAS("platform:twl6030_usb");
444MODULE_AUTHOR("Hema HK <hemahk@ti.com>");
445MODULE_DESCRIPTION("TWL6030 USB transceiver driver");
446MODULE_LICENSE("GPL");
diff --git a/drivers/usb/phy/ulpi.c b/drivers/usb/phy/ulpi.c
new file mode 100644
index 000000000000..217339dd7a90
--- /dev/null
+++ b/drivers/usb/phy/ulpi.c
@@ -0,0 +1,283 @@
1/*
2 * Generic ULPI USB transceiver support
3 *
4 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * Based on sources from
7 *
8 * Sascha Hauer <s.hauer@pengutronix.de>
9 * Freescale Semiconductors
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/export.h>
29#include <linux/usb.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32
33
34struct ulpi_info {
35 unsigned int id;
36 char *name;
37};
38
39#define ULPI_ID(vendor, product) (((vendor) << 16) | (product))
40#define ULPI_INFO(_id, _name) \
41 { \
42 .id = (_id), \
43 .name = (_name), \
44 }
45
46/* ULPI hardcoded IDs, used for probing */
47static struct ulpi_info ulpi_ids[] = {
48 ULPI_INFO(ULPI_ID(0x04cc, 0x1504), "NXP ISP1504"),
49 ULPI_INFO(ULPI_ID(0x0424, 0x0006), "SMSC USB331x"),
50};
51
52static int ulpi_set_otg_flags(struct usb_phy *phy)
53{
54 unsigned int flags = ULPI_OTG_CTRL_DP_PULLDOWN |
55 ULPI_OTG_CTRL_DM_PULLDOWN;
56
57 if (phy->flags & ULPI_OTG_ID_PULLUP)
58 flags |= ULPI_OTG_CTRL_ID_PULLUP;
59
60 /*
61 * ULPI Specification rev.1.1 default
62 * for Dp/DmPulldown is enabled.
63 */
64 if (phy->flags & ULPI_OTG_DP_PULLDOWN_DIS)
65 flags &= ~ULPI_OTG_CTRL_DP_PULLDOWN;
66
67 if (phy->flags & ULPI_OTG_DM_PULLDOWN_DIS)
68 flags &= ~ULPI_OTG_CTRL_DM_PULLDOWN;
69
70 if (phy->flags & ULPI_OTG_EXTVBUSIND)
71 flags |= ULPI_OTG_CTRL_EXTVBUSIND;
72
73 return usb_phy_io_write(phy, flags, ULPI_OTG_CTRL);
74}
75
76static int ulpi_set_fc_flags(struct usb_phy *phy)
77{
78 unsigned int flags = 0;
79
80 /*
81 * ULPI Specification rev.1.1 default
82 * for XcvrSelect is Full Speed.
83 */
84 if (phy->flags & ULPI_FC_HS)
85 flags |= ULPI_FUNC_CTRL_HIGH_SPEED;
86 else if (phy->flags & ULPI_FC_LS)
87 flags |= ULPI_FUNC_CTRL_LOW_SPEED;
88 else if (phy->flags & ULPI_FC_FS4LS)
89 flags |= ULPI_FUNC_CTRL_FS4LS;
90 else
91 flags |= ULPI_FUNC_CTRL_FULL_SPEED;
92
93 if (phy->flags & ULPI_FC_TERMSEL)
94 flags |= ULPI_FUNC_CTRL_TERMSELECT;
95
96 /*
97 * ULPI Specification rev.1.1 default
98 * for OpMode is Normal Operation.
99 */
100 if (phy->flags & ULPI_FC_OP_NODRV)
101 flags |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
102 else if (phy->flags & ULPI_FC_OP_DIS_NRZI)
103 flags |= ULPI_FUNC_CTRL_OPMODE_DISABLE_NRZI;
104 else if (phy->flags & ULPI_FC_OP_NSYNC_NEOP)
105 flags |= ULPI_FUNC_CTRL_OPMODE_NOSYNC_NOEOP;
106 else
107 flags |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
108
109 /*
110 * ULPI Specification rev.1.1 default
111 * for SuspendM is Powered.
112 */
113 flags |= ULPI_FUNC_CTRL_SUSPENDM;
114
115 return usb_phy_io_write(phy, flags, ULPI_FUNC_CTRL);
116}
117
118static int ulpi_set_ic_flags(struct usb_phy *phy)
119{
120 unsigned int flags = 0;
121
122 if (phy->flags & ULPI_IC_AUTORESUME)
123 flags |= ULPI_IFC_CTRL_AUTORESUME;
124
125 if (phy->flags & ULPI_IC_EXTVBUS_INDINV)
126 flags |= ULPI_IFC_CTRL_EXTERNAL_VBUS;
127
128 if (phy->flags & ULPI_IC_IND_PASSTHRU)
129 flags |= ULPI_IFC_CTRL_PASSTHRU;
130
131 if (phy->flags & ULPI_IC_PROTECT_DIS)
132 flags |= ULPI_IFC_CTRL_PROTECT_IFC_DISABLE;
133
134 return usb_phy_io_write(phy, flags, ULPI_IFC_CTRL);
135}
136
137static int ulpi_set_flags(struct usb_phy *phy)
138{
139 int ret;
140
141 ret = ulpi_set_otg_flags(phy);
142 if (ret)
143 return ret;
144
145 ret = ulpi_set_ic_flags(phy);
146 if (ret)
147 return ret;
148
149 return ulpi_set_fc_flags(phy);
150}
151
152static int ulpi_check_integrity(struct usb_phy *phy)
153{
154 int ret, i;
155 unsigned int val = 0x55;
156
157 for (i = 0; i < 2; i++) {
158 ret = usb_phy_io_write(phy, val, ULPI_SCRATCH);
159 if (ret < 0)
160 return ret;
161
162 ret = usb_phy_io_read(phy, ULPI_SCRATCH);
163 if (ret < 0)
164 return ret;
165
166 if (ret != val) {
167 pr_err("ULPI integrity check: failed!");
168 return -ENODEV;
169 }
170 val = val << 1;
171 }
172
173 pr_info("ULPI integrity check: passed.\n");
174
175 return 0;
176}
177
178static int ulpi_init(struct usb_phy *phy)
179{
180 int i, vid, pid, ret;
181 u32 ulpi_id = 0;
182
183 for (i = 0; i < 4; i++) {
184 ret = usb_phy_io_read(phy, ULPI_PRODUCT_ID_HIGH - i);
185 if (ret < 0)
186 return ret;
187 ulpi_id = (ulpi_id << 8) | ret;
188 }
189 vid = ulpi_id & 0xffff;
190 pid = ulpi_id >> 16;
191
192 pr_info("ULPI transceiver vendor/product ID 0x%04x/0x%04x\n", vid, pid);
193
194 for (i = 0; i < ARRAY_SIZE(ulpi_ids); i++) {
195 if (ulpi_ids[i].id == ULPI_ID(vid, pid)) {
196 pr_info("Found %s ULPI transceiver.\n",
197 ulpi_ids[i].name);
198 break;
199 }
200 }
201
202 ret = ulpi_check_integrity(phy);
203 if (ret)
204 return ret;
205
206 return ulpi_set_flags(phy);
207}
208
209static int ulpi_set_host(struct usb_otg *otg, struct usb_bus *host)
210{
211 struct usb_phy *phy = otg->phy;
212 unsigned int flags = usb_phy_io_read(phy, ULPI_IFC_CTRL);
213
214 if (!host) {
215 otg->host = NULL;
216 return 0;
217 }
218
219 otg->host = host;
220
221 flags &= ~(ULPI_IFC_CTRL_6_PIN_SERIAL_MODE |
222 ULPI_IFC_CTRL_3_PIN_SERIAL_MODE |
223 ULPI_IFC_CTRL_CARKITMODE);
224
225 if (phy->flags & ULPI_IC_6PIN_SERIAL)
226 flags |= ULPI_IFC_CTRL_6_PIN_SERIAL_MODE;
227 else if (phy->flags & ULPI_IC_3PIN_SERIAL)
228 flags |= ULPI_IFC_CTRL_3_PIN_SERIAL_MODE;
229 else if (phy->flags & ULPI_IC_CARKIT)
230 flags |= ULPI_IFC_CTRL_CARKITMODE;
231
232 return usb_phy_io_write(phy, flags, ULPI_IFC_CTRL);
233}
234
235static int ulpi_set_vbus(struct usb_otg *otg, bool on)
236{
237 struct usb_phy *phy = otg->phy;
238 unsigned int flags = usb_phy_io_read(phy, ULPI_OTG_CTRL);
239
240 flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT);
241
242 if (on) {
243 if (phy->flags & ULPI_OTG_DRVVBUS)
244 flags |= ULPI_OTG_CTRL_DRVVBUS;
245
246 if (phy->flags & ULPI_OTG_DRVVBUS_EXT)
247 flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
248 }
249
250 return usb_phy_io_write(phy, flags, ULPI_OTG_CTRL);
251}
252
253struct usb_phy *
254otg_ulpi_create(struct usb_phy_io_ops *ops,
255 unsigned int flags)
256{
257 struct usb_phy *phy;
258 struct usb_otg *otg;
259
260 phy = kzalloc(sizeof(*phy), GFP_KERNEL);
261 if (!phy)
262 return NULL;
263
264 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
265 if (!otg) {
266 kfree(phy);
267 return NULL;
268 }
269
270 phy->label = "ULPI";
271 phy->flags = flags;
272 phy->io_ops = ops;
273 phy->otg = otg;
274 phy->init = ulpi_init;
275
276 otg->phy = phy;
277 otg->set_host = ulpi_set_host;
278 otg->set_vbus = ulpi_set_vbus;
279
280 return phy;
281}
282EXPORT_SYMBOL_GPL(otg_ulpi_create);
283
diff --git a/drivers/usb/phy/ulpi_viewport.c b/drivers/usb/phy/ulpi_viewport.c
new file mode 100644
index 000000000000..c5ba7e5423fc
--- /dev/null
+++ b/drivers/usb/phy/ulpi_viewport.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright (C) 2011 Google, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/usb.h>
17#include <linux/io.h>
18#include <linux/usb/otg.h>
19#include <linux/usb/ulpi.h>
20
21#define ULPI_VIEW_WAKEUP (1 << 31)
22#define ULPI_VIEW_RUN (1 << 30)
23#define ULPI_VIEW_WRITE (1 << 29)
24#define ULPI_VIEW_READ (0 << 29)
25#define ULPI_VIEW_ADDR(x) (((x) & 0xff) << 16)
26#define ULPI_VIEW_DATA_READ(x) (((x) >> 8) & 0xff)
27#define ULPI_VIEW_DATA_WRITE(x) ((x) & 0xff)
28
29static int ulpi_viewport_wait(void __iomem *view, u32 mask)
30{
31 unsigned long usec = 2000;
32
33 while (usec--) {
34 if (!(readl(view) & mask))
35 return 0;
36
37 udelay(1);
38 };
39
40 return -ETIMEDOUT;
41}
42
43static int ulpi_viewport_read(struct usb_phy *otg, u32 reg)
44{
45 int ret;
46 void __iomem *view = otg->io_priv;
47
48 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view);
49 ret = ulpi_viewport_wait(view, ULPI_VIEW_WAKEUP);
50 if (ret)
51 return ret;
52
53 writel(ULPI_VIEW_RUN | ULPI_VIEW_READ | ULPI_VIEW_ADDR(reg), view);
54 ret = ulpi_viewport_wait(view, ULPI_VIEW_RUN);
55 if (ret)
56 return ret;
57
58 return ULPI_VIEW_DATA_READ(readl(view));
59}
60
61static int ulpi_viewport_write(struct usb_phy *otg, u32 val, u32 reg)
62{
63 int ret;
64 void __iomem *view = otg->io_priv;
65
66 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view);
67 ret = ulpi_viewport_wait(view, ULPI_VIEW_WAKEUP);
68 if (ret)
69 return ret;
70
71 writel(ULPI_VIEW_RUN | ULPI_VIEW_WRITE | ULPI_VIEW_DATA_WRITE(val) |
72 ULPI_VIEW_ADDR(reg), view);
73
74 return ulpi_viewport_wait(view, ULPI_VIEW_RUN);
75}
76
77struct usb_phy_io_ops ulpi_viewport_access_ops = {
78 .read = ulpi_viewport_read,
79 .write = ulpi_viewport_write,
80};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 16:57:40 -0500